Features: Three video anti-aliasing or reconstruction filters 2:1 mux input for YPBPR/RGB or YPBPR/YC-Cv input Supports D1, D2, D3 and D4 video D-connect (EIAJ CP-4120) selectable 8MHz/15MHz /30MHz Sixth Order Filter SD (480i), Progressive (480p) and HD Bypass (1080i/720p) AC Coupled Inputs Include DC Restoration/Bias Circuitry All outputs can drive AC or DC coupled 75Ω loads and provide 0dB or 6dB Gain 0.26% differential gain, 0.11° differential phase lead-free package

Applications: Progressive Scan Cable STB Satellite STB DVD Player HDTV Personal Video Recorder (PVR) Video on Demand (VOD)

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The FMS6407 provides full filter box or DVD applications for TVs, set-top boxes. This section consists of three sequential filter frequencies with 6 selectable 30MHz, 15MHz or 8MHz cutoffs. Filters can also be bypassed so that the bandwidth is limited only by the output amplifier. A 2-to-1 multiplexer is provided on each filter channel. Triple filters are applied to YPBPR, RGB and YC-cv signals. Set the DC clamp level mux select and cv_sel control input according to the input. The YPBPR sync tips were clamped at 250mV , 1.125V and 1.125V respectively while the rgb sync tips were all clamped to 250mV. Constant voltage mode clamps Y and Cv to 250mV and C clamps to 1.L25V. Sync clamp timing can be derived from the Y or Green input channel or from an external sync port. All channels nominally accept AC coupled 1vpp signals. Selectable 0dB or 6dB gain allows the output to drive a 1VPP or 2vpp signal input with an AC-DC coupled termination load using a 1vpp input. The input signal cannot exceed 1.5vpp and the output cannot exceed 2.5vpp. The FMS6407 draws 525MW from a 5.0V power supply.

Functional Description: 1. Introduction Next-generation filter solutions fail semiconductor expansion filters required for TV sets, set-top boxes, and DVD players including progressive scan capability The product offers selectable filtering with cut-off frequencies of 30MHz, 15MHz, and 8.0MHz on the YPBPR , RGB and YC-CV channels. Additionally, filters can be used for broadband applications. Allows consumer devices to support Variety of resolution standards with the same hardware. Provides further flexibility with multiplexers on YPBPR/RGB/YC-CV channels Synchronize TIP clamps from YPBPR to RGB mode when input multiplexer changes The voltage is Changed appropriately. All three channels are set to 250mv to reduce the DC-coupled power dissipation of the RGB input and output bias voltages are not suitable for the PBPR output. So for YPBPR inputs these signals are clamped to 1.125V, while Y is still clamped to 250MV. System runs YPBPR and YC-CV signals, Y and CV signals Will be clamped to 250mv while C is clamped to 1.125v. Sync TIP Compression voltage is forced to DC Bias level in current sync cycle No system provides external sync in green enter. If synchronization exists on the input signal, but not on the input signal. RGB and ext \ sync control inputs can be used together. On the synchronized source of the PCB and the input source switch. Both standard definition (bi-level) and high-definition (triple-level) sync in negative with sync dependent On the fsel[1:0] inputs. Standard definition with progressive signal press signal key to desired voltage during sync pulse for sync signal , the sync tip is forced by itself to the clamp voltage ("typically 250MV") when high definition sync is present. Duration is too short to allow this approach. In order to precisely clamp the high definition signal, the sync pulse starts for a period of time, and the actual Clamping happens over the next period of time. Sync Pulse This sync TIP will still be a typical location for 250MV. All three outputs are driven by amplifiers with selectable gain Of 0DB or +6DB. These amplifiers can drive two terminals Video loads (+7584886866) to 2VPP with a 1VPP input when set to 6DB; gain input range limited is 1.5vpp and the output range is limited to 2.5vpp. All control inputs must be connected to VSS or VCC. Don't leave Them floating. External sync mode FMS6407 can recover sync time from video in advance.

Signals including sync If the Y-Input Video signals does not include sync, the FMS6407 can be used in external sync mode. When the FMS6407 is used in external sync mode (external sync pin high), the pulse input must be applied to the sync pin. If no video signal is present, and therefore no sync signal, there must still be an input applied to the sync-in pin. When there is no video signal on the video input sync_in can be a sync pulse every 60 microseconds to simulate the slowest sync video signal. The following two sections discuss synchronization requiring more detailed processing and timing. SD and progressive scan video synchronization processing FMS6407 must control the DC offset of the AC coupling due to the average DC level of the video with the image content. If the input offset is allowed to drift, it can distort the signal beyond the common-mode input range of the amplifier. Reference DC offset adjustment as clamping or, in some cases, bias, must be done at the correct time on each video line. The best time is during the sync pulse as it is the lowest input voltage. This method works well for 480i and 480p signals because the sync cue duration is long enough to allow the DC offset to be compensated for row by row errors. The DC offset is shown by the current on the input during the forced sync pulse. The sync tip will clamp to about 250 mV. The symmetrical voltage range (±350mV) of signals like pb and pr will be clamped to 1.125V. Note that the graphs below indicate the output voltage levels for 0db and 6db gains (1VPP and 2VPP video signals on the FMS6407 output pins).

In some cases, the sync voltage may be compressed to a value greater than the nominal 300MV. The FMS6407 can successfully restore SD and progressive scan synchronization, the latter being greater than 100mV (compressed to 33% of nominal). The FMS6407 can correctly restore sync timing from Luma green including sync. If no video signal includes sync, the external sync control input can be set high. The external sync signal must be input on the sync input pin. See the External Synchronization section for details. The time required for this mode of operation is shown in the figure.

HD Video Sync Processing When the input signal is a high-definition signal, the tri-level sync pulse is too short for proper clamping. Instead of clamping during the sync pulse, the sync pulse locates and clamps the signal to the blanking level. This is still set to about 250mV with the sync tip. The external sync control input selects the sync stripper output to be used or the sync_-in pin via the clamp circuit. This means that synchronization is different for hd signals than for sd or ps signals. For HD signals, the sync signal must be high when the clamp must be activated. This time when the signal is at the blank level. This operation is shown in the figure. Note that the diagram below shows 0dB and 6dB gain (1VPP and 2VPP video signal FMS6407 output pins).

Synchronization Timing Normally, the FMS6407 will respond to two-stage synchronization and clamp the synchronization tip during cycle "b" in Figure 4(a). when? Filter switched to high definition mode (30MHz). The synchronization process will respond to three-level synchronization and clamp the blanking level during "c" in Figure (b).

The position of the tri-level sync pulse is such that the wide pulse does not trigger the clamp within the vertical interval. To improve the stability of the system when turned on, the wide pulses will be clamped to the ground. One large pulse (and three-level sync tip) is on the ground, and the normal clamping process takes over and clamps to cycle "c" in the blanking level diagram (b). The FMS6407 is designed to support video standards and associated synchronization timing (additional standards such as 483P59.94 also apply correctly).

Application Information: The DC recovery circuit in the input circuit FMS6407 requires a source impedance (Rsource=Rs Rt) less than or equal to 150Ω for proper operation. Driving the FMS6407 with a high impedance source (such as a DAC loaded with 330Ω) will not yield the best results. The output driver FMS6407 is specified to operate at output currents typically less than 60mA, over dual (75Ω) video loading. The current limit of the internal amplifier is about 100mA and should be able to withstand short time short circuit conditions, but this capability is not reassuring. The maximum specified input voltage for all inputs is 1.5vpp. This does not produce a meaningful output signal when the input voltage is fixed at 1.125V. With a gain of 6dB, the output should be 1.125V ± 1.5V possible, since the output cannot be driven below ground. This condition will not damage the part; however, the output will be clipped. This does not happen for signals clamped to 250mV. Signals at midscale during sync (PB, PR, C) must be clamped to 1.125V, and signals at the lowest value sync (Y, Cv, R, G, B) must be clamped to 250 mV for proper operation. Clamping the cv signal to 1.125v will result in clipping the top of the signal and clamping the PR signal to 250mV will result in clipping the bottom of the signal. A 220µf capacitor coupled with a 150Ω termination, as shown in the Typical Application Circuit, Table A, a high-pass filter, blocks DC frequencies and avoids tilt when transmitting video. Anything below 220 microF will cause issues such as video skew. Higher value, for example because 470µf-1000µf is the most ideal output coupling capacitor. With AC coupling, the average DC level is zero. Therefore, the output voltages of all channels will be centered around zero degrees. Sync recovery The FMS6407 will typically recover with amplitudes greater than 100mV (relative to the nominal 300mV amplitude). The FMS6407 looks for the lowest signal voltage and clamps it to approximately 250mV at the output. Tri-level sync cannot compress more than 5% (15MV) for proper operation. Operate the back porch gap clamp by finding the edge of the tri-level pulse and running the timer. Since only the y/g channel is processed for synchronization recovery, the ycv input must be synchronized.