Features: Low Power: 48mW+3V; Supply Range: +2.7V to +3.7V; Adjustable Full Scale Range with External Reference; No Missing Codes; Wideband Track/Hold: 350MHz; Power Down: 15MW SSOP-28 unit.

application

battery-operated equipment; video cameras; digital cameras; computer scanners; communications.

describe

The ADS901 is a high-speed pipeline analog-to-digital converter powered by a +3V supply. This complete converter includes a wideband track/hold and a 10-bit quantizer. The full-scale input range is set by the external reference.

The ADS901 uses digital error correction technology to provide excellent differential linearity for demanding imaging applications. Its low distortion and high signal-to-noise ratio provide additional headroom for telecom, video and test instrumentation applications. The ADS901 is available in the SSOP-28 package.

theory of operation

The ADS901 is a high-speed sampling analog-to-digital converter using a pipeline structure. Fully differential topology and digital error correction guarantee 10-bit resolution. The differential track/hold circuit is shown in Figure 1. The switches are controlled by an internal clock with non-overlapping two-phase signals φ1 and φ2. When sampling, the input signal is sampled on the bottom plate of the input capacitor. At the next clock stage, φ1, the bottom plates of the input capacitors are connected together and the feedback capacitor switches to the op amp output. At this point, the charge is redistributed between ci and ch, completing a track/hold cycle. The differential output is a held DC representation of the analog input at the time of sampling. The track/hold circuit can also convert the single-ended input signal to a fully differential signal for the quantizer. Hence, the SNR performance of the input. This stage also defines parameters such as small signal, full power bandwidth, and broadband noise.

To accommodate bipolar signal swings, the ADS901 operates with a common-mode voltage (VCM) derived from an external reference source. Due to the symmetrical resistor ladder inside the ADS901, VCM is located between the top and bottom reference voltages. Equation (1) can be used to calculate the common mode voltage level:

There is a 5.0 clock cycle data delay from the start of the conversion signal to valid output data. The standard output encoding is straight offset binary, where a full-scale input signal corresponds to all "1"s at the output. The digital outputs of the ADS901 can be set to a high impedance state by driving tri-state (pin 16) with logic "HI". Normal operation is via pin 16 "lo", or floating due to internal pull-down resistor. This function is used for testability purposes, but is not recommended for dynamic use.

application

Signal swing and common mode considerations

The ADS901 is designed to operate from a single +3V supply voltage. The nominal input signal swing is 1vp-p between +1v and +2v. This means that the signal swings ±0.5v (VCM=vs/2) around a common-mode voltage (half the supply voltage) of +1.5v. In some applications, it may be advantageous to increase the swing of the input signal. This will improve the achievable signal-to-noise performance. However, consideration should be given to keeping the signal swing within the linear range of operation of the driver circuit to avoid any excessive distortion. In extreme cases, the performance of the converter will begin to degrade as the on-resistance of the switch at the input varies with the input voltage. Therefore, during normal operation, the signal swing should be kept at about 0.5V from each rail.

The pipelined quantizer architecture has 9 stages, each of which contains a 2-bit quantizer and a 2-bit digital-to-analog converter, as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the subclock, which is at the same frequency as the externally applied clock. The output of each quantizer is input into its own delay line in order to time-align it with the data created from the following quantizer stages. These aligned data are fed into digital error correction circuitry that adjusts the output data based on information found on redundant bits. This technology provides ads901 with good differential linearity and guarantees no missing codes at the 10-bit level.

drive analog input

AC Coupled Drive

Figure 2 shows an example of an AC-coupled single-ended interface circuit using a high-speed op amp dual-supply (OPA650, OPA658). The midpoint reference voltage VCM makes the bipolar ground referenced input bias signal. Capacitor C1 and resistor R1 form a filter with a high pass frequency set to -3db:

The values of c1 and r1 are not important in most applications and can be set freely. The value shown corresponds to a frequency of 1.6kHz.

Figure 3 depicts a circuit that can be used in single-supply applications. The intermediate reference voltage biases the op amp to an appropriate common mode voltage, eg VCM=+1.5V. Using capacitor CG, the DC gain of the non-inverting op amp input is set to +1V/V. Therefore, the transfer function is modified to:

Likewise, the input coupling capacitor c1 and resistor r1 form a high pass filter. Meanwhile, the input impedance is defined by r1. Resistor RS isolates the output of the op amp from the capacitive load to avoid gain peaks or even oscillations. It can also be used to establish a defined bandwidth to reduce broadband noise. The recommended value is usually between 10Ω and 100Ω.

DC coupled interface circuit

Many systems now require A/D converters and their drivers to have a single supply capability of +3v. Figure 4 shows an example of a DC-coupled configuration that only operates from a +3V supply voltage. The opa632 provides excellent performance in this demanding application. Its wide input and output voltage range, low distortion, well support the ADS901. The OPA632 is configured for gain +2. The 374Ω and 2.26kΩ resistors at the input level shift the VIN (vin) so that when the VIN (vin) is 0, the VIN (vout) is within the allowable output voltage range. The input impedance of the driver circuit was set to match the 50Ω source impedance. The input level shifting is designed so that the VIN can be between 0V and 5V while delivering an output voltage of 1V to 2V to the ADS901. Both the opa632 and the ads901 have a power-down function pin with the same polarity for those systems that require power saving.

xref

The ADS901 requires an external reference on pin 22 (reference) and pin 24 (reference B). Internally, these pins are connected via a resistor ladder with a nominal resistance of 4kΩ (±15%). To establish the correct voltage drop across the ladder, the external reference circuit must typically be able to source 250 microamps. Using this current, the full-scale input range of the ADS901 is set between +1V and +2V or 1VP-P. Typically, the voltage drop between REFT and REFB determines the input full-scale range (FSR) of the ADS901. Equation (4) can be used to calculate the span.

Depending on the application, there are several options to provide an external reference voltage to the ADS901 without degrading typical performance.

Low cost reference solution

The easiest way to achieve the desired reference voltage is to place the reference ladder for the ADS901 between the supply rails, as shown in Figure 5. Two additional resistors (RT, RB) are required to set the correct current through the ladder. However, depending on the desired full-scale swing and supply voltage, different resistor values can be selected.

When choosing this reference circuit, the trade-off is the reference voltage variation due to component tolerances and power supply variation. In any case, it is recommended to bypass the reference ladder with at least 0.1µF ceramic capacitors, as shown in Figure 5. Capacitors serve a dual purpose. They will bypass most of the high frequency transient noise generated by clock feedthrough and T/H stage switching noise. Second, they act as charge banks to supply instantaneous currents to internal nodes.

Precision Reference Solution

For those applications that require a higher level of DC accuracy and drift, a reference circuit with precision reference components can be used (see Figure 6). A stable +1.2V reference voltage is established by a double-ended bandgap reference diode REF1004-1.2. Using a general-purpose single-supply dual op amp (A1), such as the OPA2237, OPA2234, or OPA2343, the two reference voltages required by the ADS901 can be generated by setting each op amp to the appropriate gain; for example: setting REFT to +2V, Set REFB to +1V.

clock input

The clock input of the ADS901 is designed to accommodate +5V or +3V CMOS logic levels. To drive the clock input with minimum duty cycle variation and support maximum sample rate (20msps), high speed or advanced cmos logic (hc/hct, ac/act) should be used. When digitizing at high sample rates, a 50% duty cycle clock with fast rise and fall times (2ns or less) is recommended to meet rated performance specifications. However, the performance of the ADS901 can tolerate up to ±10% duty cycle variation without degradation. For applications with input frequencies up to Nyquist or undersampling applications, special consideration must be given to providing a clock with very low jitter. Clock jitter results in aperture jitter (ta), which can be the ultimate limit to good SNR performance. Equation (5) shows the relationship between aperture jitter, input frequency, and signal-to-noise ratio:

For example, with a 10MHz full-scale input signal and aperture jitter ta=20ps, snr is clock jitter limited to 58db.

digital output

There is a 5.0 clock cycle data delay from the start of the conversion signal to valid output data. The standard output encoding is straight offset binary, where a full-scale input signal corresponds to all "1"s at the output. The digital outputs of the ADS901 can be set to a high impedance state by driving tri-state (pin 16) with logic "HI". Normal operation is via pin 16 "lo", or floating due to internal pull-down resistor. This function is used for testability purposes, but is not recommended for dynamic use.

The digital outputs of the ADS901 are standard CMOS grade and are designed to be compatible with high-speed TTL and CMOS logic families. The logic threshold is suitable for low voltage cmos: vol=0.4v, voh=2.4v, allowing ads901 to interface directly with 3v logic. The digital outputs of the ADS901 use a dedicated digital supply pin (pin 2, LVDD). By adjusting the voltage on the lvdd, the digital output level will change separately. In any case, it is recommended to limit the fanout to one to keep the capacitive loading on the data lines below the specified 15pF. If necessary, external buffers or latches can be used to provide the added benefit of isolating the A/D converter from any digital activity on the bus, coupling back high frequency noise and degrading performance.

Power down mode

Enabling power-down mode can further reduce the low power consumption of the ADS901. To do this, the PWRDN pin (pin 17) must be tied to logic "high" to reduce the current drawn from the power supply by about 70%. In normal operation, power-down mode is disabled by an internal pull-down resistor (50KΩ).

When powered down, the digital outputs are set to 3 states. With the application of the clock, the converter cannot process the sampled signal accurately. After the power is turned off, the output data is invalid (data delay) for the following 5 clock cycles.

Decoupling and Grounding Considerations

The ADS901 converter has several power pins, one of which is dedicated to providing only the output driver. The rest of the power pins are not divided into analog and digital power pins as is usually the case because they are connected internally on the chip. Therefore, it is recommended to treat the converter as an analog component and power it only from the analog supply. Digital power lines often carry high levels of noise that can couple back into the converter and limit the achievable performance.

Due to the pipelined structure, the converter also generates high-frequency transients and noise that feed back into the power and reference lines. This requires that the supply and reference pins be adequately bypassed. Figure 8 shows the recommended decoupling scheme for analog power supplies. In most cases, 0.1µf ceramic chip capacitors are sufficient to maintain low impedance over a wide frequency range. Their effectiveness depends heavily on proximity to a single supply pin. Therefore, they should be placed as close as possible to the power pins.