describe
The W3020 is a highly integrated GSM transceiver designed to work in dual-band handsets or single-band handsets in the 900 , 1800 and 1900 MHz bands (1900 MHz performance not proven in production). The integrated circuit architecture allows RF designers to provide solutions for three different frequency bands with minimal PCB changes, providing faster time-to-market and reduced development time.
The W3020 RF Transceiver and W3000 Phase Locked Loop are designed with SC1 (Radio Interface and Digital Signal Processor) to provide a complete GSM cellular solution. The W3020 interfaces with the W3000 UHF high-performance PLL IC. The W3020 combines with the W3000 to provide a transmitter, receiver and frequency synthesizer. Add power amplifiers, filters and VCO modules to complete the wireless channel.
The baseband modulated signal is differentially applied to the i/q double-balanced mixer. To obtain the desired modulation spectrum mask, the ±45° phase-shifted LO does not require fine tuning. At the same time, in order to obtain a signal with high phase accuracy, the I/Q input signal does not need DC offset calibration. The if signal outputs from the i/q mixers are summed and output to an external filter that reduces noise that can be intermodulated into the receive band. This signal is then applied to a low noise upconversion mixer and brought to the rf output.
The received signal is amplified by a low noise amplifier, which is combined with the previous filter to control the receiver sensitivity. This signal is then passed through another external filter to attenuate the image frequency to an acceptable level. The signal passes through the RF downconversion mixer to the IF frequency. It is then filtered with an external surface acoustic wave (saw) filter to bring the in-band blocking signal to an acceptable level. The signal is amplified in the intermediate frequency band of the receiver. The mid-band includes digital gain control (DGC) amplifiers and precision low-pass filters at the IF and baseband frequencies. This amplifies the signal while eliminating in-band blocking signals. A precision I/Q demodulator separates the signal into in-phase and quadrature. The I/Q signal is low pass filtered and further amplified. The I/Q amplifier contains integrated DC offset calibration circuitry. The output (I/Q) is fed to the ADC for further signal processing.
The second local oscillator (lo2) includes a buffer and phase locked loop (pll) for an external voltage controlled oscillator (vco), feeding the modulator and the if part of the receiver. The external reference voltage-controlled crystal oscillator (VCXO) is divided by a counter from 13MHz to 1MHz. 1 MHz is called the comparison frequency. The VCO frequency of 540 MHz is also divided into 1 MHz. Both signals are fed to a phase detector, and the resulting error signal is fed to the control input of the VCO through an external low-pass filter.
The RF transceiver mixer is driven by a two-band switchable external VCO module, buffered internally on the IC. The VCOs are all controlled by a W3000 phase-locked loop synthesizer and loop filter. Fast band lock is achieved using a proprietary scaling technique integrated in the W3000 PLL.
Description (continued)
Detailed block diagram

IF/BASEBAND AMPLIFIER The IF amplifier is a balanced input/balanced output type and is connected to a balanced saw filter. It consists of three gain stages: an IF amplifier and two baseband amplifiers. Gain can be changed in steps of 32, 16, 8 and 4db. The baseband also contains a level shifter stage to directly drive the A/D converter. The level shifter stage has 21dB of gain and can be turned off. The following specifications apply to both modes of operation.
Mid-band gain is programmed via a three-wire serial bus.
The IF amplifier contains a 32dB amplifier stage with 0 or 32dB gain. The IF amplifier is followed by a quadrature mixer with a fixed gain of 4db. The first baseband amplifiers (g3, g2, g6) after the low pass filter and demodulator have a gain selectable between 0, 4, 8, 12, 16, 20, 24 and 28db. Using other gain steps, the if and baseband gains can vary by 64db in 4db steps. The gain of the second baseband amplifier (g5, g1) is selectable between 0, 4, 21 and 25db. The 21db gain step in the second baseband amplifier section was not tested and should not be used.
The IF Amplifier Gain Step Baseband Amplifier section contains a dc correction circuit that minimizes the dc offset at the i/q output. The low-pass filter in the baseband contains a self-calibration circuit for tuning the filter cutoff frequency. Selectable gain settings via
tr register, as described in the Programming Information section. Filter tuning and DC calibration are also explained in this section.
To achieve the specified absolute gain accuracy, the total gain should be calibrated at room temperature. This is usually part of the overall phone calibration. Absolute gain accuracy measures the change in gain over a specified temperature range relative to room temperature measurements. In gsm systems, this specification relies on all rx function blocks, not just if clauses. Relative gain accuracy is a measure of gain stage accuracy over a 20 dB range. After calibrating the 32dB amplifier, determine the relative gain accuracy.
Actual vs Requested Gain The mid-band input impedance will change slightly as the 32dB amplifier switches between on and off states. We recommend matching the mid-band to a 32dB amplifier with power on to provide the best match to a SAW filter with minimal input levels. The input matching network can match the IF input directly to a SAW filter or 50Ω.
A network matched to 50Ω was selected for the evaluation committee to facilitate laboratory measurements. To keep the input impedance low and to minimize impedance changes between IF stage gain settings, a resistor is placed in parallel between the input terminals. The input network can then be matched to the desired input impedance. (The specified gain includes a resistor value of 500Ω.) For testing purposes, the input has been matched to 50Ω, and the if/baseband amplifier gains all refer to a 50Ω matched input impedance. The I/Q output is terminated in a high impedance load. The gain is the voltage gain and includes the voltage gain in the impedance transformation of the input matching network.

Modulators (continued)

IF Filtering Requirements for Broadband Noise Performance
LO2 specification
The W3020 contains an input buffer for an external VCO and a PLL for generating the second LO signal at 540 MHz. The output of the buffer is fed to the receive and transmit circuits where the signal is distributed to the if frequency. Phase noise includes the contribution of the VCO buffer to the transmit and receive circuits.

programming information
The W3020 and W3000 transceiver modes (IC RX/TX) as well as gain and band settings are programmed using a standard 3-wire bus (clock, data, latch). The W3020 and W3000 registers are addressable, so both ICs can share the same data, clock and latch times. The latch row initiates the download and execution of the current data word.

data word
The W3020 and W3000 chips are addressed by the bit content of a 24-bit serial word. Some words for time-critical interactions handle both W3020 and W3000, while some words for initialization handle W3020 and W3000 respectively.
The W3020 gets all its control information from the baseband IC via a three-wire serial bus. Serial data transfers always consist of 24 bits: the 3-bit address selects one of the 5 control registers, with up to 21 bits of data. When the latch enable signal goes high, the data is first shifted into the shift register and then loaded in parallel into the appropriate control register after the transfer is complete. The last bit is the bit immediately preceding the low-to-high latch input transition that occurs when the clock input is low. Bit 24 is loaded first and bit 1 is loaded last. The four control registers are defined as follows:
The transmit/receive registers of the W3020. Contains bits for setting various transmit and receive modes, setting receive gain, etc. It is expected that this register will be written to multiple times in a frame.
Configuration: Contains bits to control various options for DC offset correction, filter tuning, lock detection, and overload output. This register is expected to be written once at initialization and then updated rarely. Since it is not affected by the power-on reset circuit, when accessing the W3020 chip, a write operation to this register should be performed first. Also, it is not recommended to update the configuration registers during critical operations.
Main: Main counter and prescaler value of W3000 chip. Used to set the mode and bit function for W3020 when programming W3000.
Referee: Reference counter value for W3000. Nothing to do with W3020

Mode control
Various system modes of the W3020 are set by the mode control bits. They are active in both tr and main registers. The W3000 will also power up through the W3020 in any valid mode set by the TR or the mode bits in the main register. Table 15 shows the mode bit settings for each W3020 system mode. The corresponding typical supply current of the IC in each mode is shown in the supply current table on page 9.
In sleep mode, both the W3020 and W3000 are powered down and the supply current is in the microamp range. Use the transmit pll stabilization mode before the transmit burst in order to power up and lock the lo1 and lo2 vco/pll synthesizers and the corresponding rf and if lo buffers connected to the modulator circuit. In this mode, the LO2 divide circuit remains off. Similarly, use the receive pll setup mode prior to the receive dc calibration slot and subsequent receive burst to power up and lock the lo1 and lo2 vco/pll synthesizers and the corresponding rf and if lo connected to the rf mixer and if bar buffer. In this mode, the RF mixer can be turned on by setting the C9 (turn RF mixer on during setup) bit high in the configuration register. Transmitter-on mode turns on all the same circuits as transmit pll stabilization mode, while turning on the i/q modulator and upconversion mixer.
Receiver On Mode turns on all the same circuits as Receive PLL Stabilization Mode, but also turns on the LNA (if enabled by the G0 bit), RF mixer, IF amplifier and demodulator. When first entering receive mode, baseband lp filter tuning is performed by setting the FTR (Filter Tuning Request) bit in the TR register high and the C6 (Filter Tuning Disable) bit in the Configuration register low, if requested (and low-pass filter tuning section). Next, if the ds (dc correction skip) bit in the tr register is low and the c5 (dc correction disable) bit in the configuration register is low, a dc offset correction loop is performed. The default condition is that if the C2 (LNA mode during DC calibration) bit in the configuration register is low, the LNA is turned off during DC calibration. Another default condition is that the rf mixer lo1 buffer is turned off during dc calibration if the c3 (rx lo1 buffer mode during dc calibration) bit in the configuration register is low.

Filter Tuning and DC Offset Correction Timing Low Pass Filter Tuning
The W3020 has internal calibration to improve the accuracy of the low pass filter bandwidth. A filter tuning operation should be performed each time supply voltage is applied to the device and after a restart.
The low pass filter tuning operation is controlled by 3 bits in the control logic: n ftr: filter tuning request, in tr register n c4: low pass filter bandwidth, in configuration register n c6: filter tuning disable, in configuration register If the filter tuning disable bit (c6) is programmed high, the filter bandwidth is set to the programmed (nominal) value (see Table 35) and any filter tuning requests from the ftr bits are ignored.
By performing a filter tuning calibration, the accuracy of the filter bandwidth can be improved. Filter tuning can be performed by setting the filter tune request (ftr) bit in the tr register high and the filter tune disable bit (c6) in the configuration register low. This enables the 13/4mhz (3.25mhz) clock to enter the filter tuning state machine, which then runs until the tuning is complete and the new filter tuning value is stored. The filter optimization operation itself requires 16.5 cycles of the megahertz clock, or 5.1 microseconds.
The filter tuning operation should be done in receive mode. Receive mode needs to remain active for at least 20 µs to allow bias start-up.
If required, perform a DC offset calibration after filter tuning is complete. When requested at the same time as DC offset calibration, the filter tuning operation will add 5.1 microseconds to the total calibration time. If filter tuning is requested when the mod bits are not set to 111, only the receive bias circuit is turned on; the remaining receive channels remain powered down.
Filter Tuning and DC Offset Correction Timing (Continued)
DC offset calibration DC offset calibration operation is controlled by several bits in the configuration register and tr register: n ds: dc correction skipped, n tr register n dp: dc precharge only, n tr register n c5: dc correction disabled , in configuration register n c7: dc coarse/fine correction, in configuration register n dt: dc correction time, in configuration register When the dc correction disable bit (c5) in the configuration register is written high, the dc offset correction circuit Charge to the default value corresponding to 0 dc offset and ignore any request for dc offset correction. If dc correction disable=0, dc offset calibration is initiated by writing the mo bit in the tr (or main) register to a value of 111 when both dc correction skip (ds) and dc precharge only (dp) are low. As in the case of filter tuning, the start of dc offset calibration is delayed by about 15 μs when the bias circuit and input clock buffer are enabled.
If the FTR bit is also written high while entering RX mode, filter tuning is performed first, and then the DC offset calibration starts automatically.
The time that the DC offset calibration runs is determined by the DC offset correction time bits dt[0:2] in the configuration register. With three bits, the user can select eight different correction times.
After the DC offset calibration is completed, the 3.25 MHz baseband clock is stopped, the full receive mode is automatically entered, and the LO1 buffer and LNA are automatically enabled (if g0=1).
If RX mode is entered with DC precharge (dp=1) set high, the DC offset circuit will go through a shorter calibration procedure and then automatically enter normal receive mode. The function of the precharge-only operation is basically the same as the normal calibration operation because the LO1 buffer and LNA are disabled until the precharge operation is complete. Still resulting in a bias start-up time of 15µs.
Receive circuit conditions during DC calibration are also controlled by two other bits in the configuration register: n c2:lna is on during DC calibration, high c3:receive lo1 buffer is on during DC calibration, high during DC calibration For standard DC offset calibration loops and DC-only precharge operation, DC offset calibration can be performed with the LNA and/or LO1 buffers turned on by setting the C2 and C3 bits in the configuration register.
Programming Example This programming example demonstrates how to program the W3020 after power up and how to program it before receiving and transmitting a burst signal. The W3000's reference registers are individually initialized with the reference split ratio as described in the W3000 datasheet