Main features

Up to 600 MHz, 1.67 ns instruction cycle rate; 24M-bit internal on-chip DRAM memory; 25 mm x 25 mm (576-ball) thermally enhanced ball grid array package; dual compute blocks, each containing one ALU, one multiplier, one shifter Bit register, a register file and a communication logic unit (CLU); double integer arithmetic unit, provides data addressing and pointer operations; integrated I/O includes 14-channel DMA controller, external ports, four link ports, SDRAM control 1149.1 IEEE-compliant on-chip emulated jtag test access port; single-precision IEEE 32-bit and extended-precision 40-bit floating-point data format and 8, 16, 32, and 64-bit fixed-point data formats.

General Instructions

The ADSP-TS201S TIGERSHARC processor is an ultra-high performance static superscalar processor optimized for large signal processing tasks and communication infrastructures. The DSP combines a very wide memory width with dual computation blocks that support floating-point (ieee 32-bit and extended-precision 40-bit) and fixed-point (8-bit, 16-bit, 32-bit, and 64-bit) processing, designed for digital signal processors new performance standards. The TigerSharc static superscalar architecture allows the DSP to execute up to 4 instructions per cycle, performing 24 fixed-point (16-bit) operations or 6 floating-point operations.

Four independent 128-bit wide internal data buses, each connected to six 4M-bit memory banks, support quadword data, instruction and I/O access, and provide 33.6Gbytes per second of internal memory bandwidth. The core operating frequency of the ADSP-TS201S processor is 600 MHz and the instruction cycle is 1.67 nanoseconds. The ADSP-TS201S processor uses its Single Instruction Multiple Data (SIMD) capability to execute 4.8 billion, 40-bit Macs or 1.2 billion, 80-bit Macs per second. Table 1 shows the performance benchmarks for digital signal processors.

The ADSP-TS201S processor is code compatible with other TigerSharec processors. The functional block diagram shows the architectural blocks of the ADSP-TS201S processor. These blocks include:

(1), double calculation blocks, each block includes an ALU, multiple pliers, 64 bit shifters, 128-bit CLU, 32-word register files and related data alignment buffers (DAB);

(2), double integer ALU (IAlus), each ALU has its own 31-word register file for data addressing and status registers;

(3) Program sequencer (IAB) with instruction alignment buffer and branch target buffer (BTB);

(4) An interrupt controller that supports hardware and software interrupts, supports level or edge triggers, and supports priority nested interrupts;

(5), four 128-bit internal data buses, each connected to six 4M-bit memory banks; on-chip DRAM (24M-bit);

(7), provide external ports with host processor, multiprocessing space (DSP), off-chip memory mapping peripherals, and external SRAM and SDRAM interfaces; 14-channel DMA controller; four full-duplex LVDS link ports;

(8), two 64-bit interval timers and timer expiration pins; a 1149.1 IEEE compliant JTAG test access port for on-chip emulation.

Figure 2 shows a typical uniprocessor system with external sram and sdram. Figure 4 shows a typical multiprocessor system.

tigersharc dsp uses a static superscalar structure. This structure is superscalar because the core of the ADSP-TS201S processor can simultaneously execute one to four 32-bit instructions using the DSP's dual computation blocks, encoded in a very large instruction word (VLIW) instruction line middle. Since DSPs do not perform instruction reordering at run time - the order in which the programmer chooses which operations will execute instructions in parallel before the run is static.

With a few exceptions, an instruction line (whether it contains one, two, three, or four 32-bit instructions) executes at one-cycle throughput in a 10-deep processor pipeline.

For optimal DSP program execution, programmers must follow the DSP's set of instruction parallelism rules when coding instruction lines. In general, the choice of instructions that a dsp can execute in parallel per cycle depends on the instruction-line resources required for each instruction and the source and destination registers used in the instruction. Programmers have direct control over three core components: IAlus, Calculation Blocks, and Program Sequencer.

In most cases, the ADSP-TS201S processor has a fully interlocked two-cycle execution pipeline, so when the result of a computation cannot be used for another operation that depends on it, the DSP automatically inserts one or more pause cycles as needed . Efficient programming using dependency-free instructions can eliminate most computational and memory transfer data dependencies.

In addition, the ADSP-TS201S processor supports two modes of SIMD operations: SIMD computation block and SIMD computation. The programmer can load two computation blocks with the same data (broadcast distribution) or different data (merge distribution).

double computing block

The ADSP-TS201S processor has compute blocks that can perform computations individually or together as a single instruction multiple data (SIMD) engine. Each cycle, the DSP can issue up to two compute instructions per compute block, instructing the ALU, Multiplier, Shifter, or CLU to perform independent simultaneous operations. Each computation block can perform eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with operations in another block. These computational units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating-point, and 8, 16, 32, and 64-bit fixed-point processing.

In assembly syntax, blocks of computation are called x and y, and each block contains four computational units: alu, multiplier, 64-bit shifter, 128-bit clu, and a 32-word register file.

(1) Register file Each computing block has a multi-port 32-word full quadrature register file, which is used to transfer data between the computing unit and the data bus, and store intermediate results. Instructions can access registers in the register file individually (word-aligned), two groups (double-aligned), or four groups (quad-aligned).

(2), ALU ALU performs a standard set of arithmetic operations in fixed and floating-point format. It also performs logical operations.

(3) Multiplier The multiplier performs fixed-point and floating-point multiplication as well as fixed-point multiplication and accumulation.

(4) Shifter 64 The bit shifter performs logical and arithmetic shifts, bit and bit stream operations, and field storage and extraction operations.

(5) Communication Logic Unit (CLU) - This 128-bit unit provides trellis decoding (eg, Viterbi and turbo decoders) and performs complex correlations for CDMA communication applications (eg, chip rate and symbol rate functions) .

Using these functions, the calculation block can:

(1) 8 macs per cycle peak, 7.1 macs per cycle for 16-bit performance, 2 macs per cycle peak, and 1.8 macs per cycle for 32-bit performance (based on fir);

(2) Execute 6 single-precision floating-point or 24 fixed-point (16-bit) operations per cycle, providing 3.6G flip-flops or 14.4G/s regular operation performance of 600 MHz;

(3) Execute two complex 16-bit macs per cycle; execute eight grid butterflies in one cycle.

Data Alignment Buffer (DAB)

dab is a quadword fifo that allows loading quadword data from unaligned addresses. In general, a load instruction must be aligned to its data size in order to load a quadword from a quad-aligned address. Using dabs can significantly improve the efficiency of some applications, such as fir filters.

double integer arithmetic unit

The ADSP-TS201S processor has two IAlus that provide powerful address generation and perform many general-purpose integer operations. In assembly syntax, IAlus is called j and k and has the following properties:

(1) Provide memory addresses for data and update pointers • Support circular buffering and bit reverse addressing;

(2) Execute general integer operations to improve programming flexibility;

(3), include a 31-word register file for each IAlu;

As an address generator, IAlus performs immediate or indirect - gamma static superscalar is a trademark of Analog Devices Inc. rect (before and after modification) addressing. They perform modulo and bit-reversal operations, independent of the memory address where the modulo data buffer is placed. Each IAlu can specify single, double or quadword access from memory.

IAlus has hardware support for circular buffers, bit reversal, and zero-overhead loops. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, which are commonly used in digital filters and Fourier transforms. Each IAlu provides registers for four circular buffers, so an application can set up a total of eight circular buffers. IAlus automatically wraps address pointers, reducing overhead, improving performance, and simplifying implementation. A circular buffer can start and end at any memory location. Because ialu's computational pipeline is one loop deep, in most cases the integer result is available in the next loop. Hardware (register dependency checking) will cause a stall if the result is not available within a given cycle.

program sequencer

The program sequencer of the ADSP-TS201S processor supports the following functions:

Fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles high throughput and hardware interrupts without interrupting instruction cycles.

(1), 10-cycle instruction pipeline, four-cycle acquisition pipeline and six-cycle execution pipeline calculation results are available two cycles after operands are available;

(2) Provide instructions to fetch memory addresses; the sequencer's instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to be executed; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core components for execution;

(3) Management of program structure and program flow determined according to jumps, calls, rti, rts instructions, loop structures, conditions, interrupts and software exceptions;

(4), branch prediction and 128-entry branch target buffer (BTB) to reduce branch latency, effectively execute conditional and unconditional branch instructions and zero-overhead loops; correctly predicted branches appear zero-overhead loops, overcoming five to Nine-level branch penalty;

(5) Compress code without aligning code in memory; IAB handles alignment.

interrupt controller

dsp supports nested and non-nested interrupts. Each interrupt type has a register in the interrupt vector table. Additionally, there is one bit each in the Interrupt Latch Register and the Interrupt Mask Register. All interrupts are fixed to be level-sensitive or edge-sensitive, except for IRQ3–0 hardware interrupts, which are programmable.

dsp distinguishes between hardware interrupts and software exceptions and handles them differently. When a software exception occurs, the dsp aborts all other instructions in the instruction pipeline. When a hardware interrupt occurs, the dsp continues to execute instructions already in the instruction pipeline.

Flexible instruction set

The 128-bit instruction line can contain up to four 32-bit instructions, which can accommodate multiple parallel operations for concise programming. For example, an instruction line can instruct the dsp to conditionally perform multiplication, addition, and subtraction in two computational blocks, while it also branches to another location in the program. Some key features of the instruction set include:

(1), clu instruction for communication infrastructure for controlling trellis decoding (e.g. viterbi and turbo decoders) and despreading through complex dependencies; algebraic assembly language syntax; direct support for all digital signal processors, Image and video algorithm types;

(2) There is no need to switch the digital signal processor hardware mode, because the mode is supported as an option in the instruction (such as rounding, saturation and others);

(3), branch prediction encoded in instructions; enabling zero-overhead loops; parallelism encoded in instruction lines; conditional execution of all instructions is optional; user-defined partitioning between program and data memory.

DSP memory

The internal and external memory of the DSP is organized into a unified memory map that defines the locations (addresses) of all elements in the system, as shown in Figure 3.

The memory map is divided into four memory areas host space, external memory, multiprocessor space, and internal memory, and each memory space (except host memory) is subdivided into smaller memory spaces.

The internal memory of the ADSP-TS201S processor has a 24M-bit on-chip DRAM memory, which is divided into 6 4M-bit blocks (128K words × 32 bits). Each block m0, m2, m4, m6, m8, and m10 can store program instructions, data, or both, so applications can configure memory to meet specific needs. However, placing program instructions and data in separate memory blocks enables DSPs to access data when performing instruction fetches. Each memory segment contains a 128K-bit cache to enable single-cycle access to the internal DRAM.

Six internal memory blocks are cross-connected to four 128-bit wide internal buses, enabling the DSP to perform four memory transfers in the same cycle. The DSP's internal bus structure provides 33.6G bytes per second, enabling the core and I/O to access eight 32-bit data words and four 32-bit instructions per cycle. The flexible memory structure of the digital signal processor enables:

(1) In the same cycle, perform dsp core and i/o access to different memory blocks;

(2) dsp core access to three memory blocks with one instruction and two data accesses in parallel;

(3) Programmable partition of program and data memory;

(4) Program access to all memory in the form of 32-bit, 64-bit or 128-bit words (16-bit words) using DAB.

External ports (off-chip memory/peripheral interface)

The external port of the ADSP-TS201S processor provides the interface between the DSP and off-chip memory and peripheral devices. The address space of 4g words is contained in the unified address space of the DSP.

Independent on-chip bus Four 128-bit data buses and four 32-bit address buses are multiplexed at the soc interface and transmitted to external ports through the soc bus to create external system bus transactions. The external system bus provides a single 64-bit data bus and a single 32-bit address bus. The external port supports a data transfer rate of 1 gigabyte per second over the external bus.

The external bus can be configured for 32-bit or 64-bit littleendian operation. When the system bus is configured for 64-bit operation, the lower 32 bits of the external data bus are connected to even addresses and the upper 32 bits are connected to odd addresses.

External ports support pipelining, slow and sdram protocols. The bank select signal is generated by on-chip decoding of high-order address lines, thereby facilitating addressing of external memory devices and memory-mapped peripherals.

The ADSP-TS201S processor provides programmable memory, pipeline depth, and idle cycles for simultaneous access; and external acknowledgement controls to support communication with pipelined or slow devices, host processors, and other devices with variable access, hold, and disable time requirements Interface for storage peripherals.

host interface

The ADSP-TS201S processor provides an easily configurable interface between its external bus and the host processor through an external port (see Figure 4). In order to adapt to various host processors, the host interface supports pipeline or slow protocol, which is used to access the ADSP-TS201S processor of the host in a slave mode, or access the host of the ADSP-TS201S processor in a slave mode in a pipeline mode. Each protocol has programmable transfer parameters such as idle periods, pipe depth and internal wait periods.

The host interface supports burst transactions initiated by the host processor. The brst signal is asserted after the host has issued the starting address of the burst, and the dsp increments the address internally as the host continues to assert brst. The host interface provides a deadlock recovery mechanism that enables the host to recover from a digital signal processor. The boff signal provides a deadlock recovery mechanism. When the host asserts boff, the dsp aborts the current transaction and asserts the hbg and relinquishes the external bus. The host can directly read and write the internal memory of the ADSP-TS201S processor, and can access most of the DSP registers, including the DMA control (TCB) registers. Vectored interrupts support efficient execution of host commands.

multiprocessor interface

The ADSP-TS201S processor provides powerful functions for multiprocessing DSP systems through external ports and link ports (see Figure 4). This multiprocessing capability provides the highest bandwidth for interprocessor communication, including:

(1), up to 8 DSPs on the public bus;

(2) On-chip arbitration without glue and multiprocessing;

(3) Link port for point-to-point communication;

The external ports and link ports provide integrated glueless multiprocessing support, and the external ports support a unified address space (see Figure 3), enabling the internal memory and registers of each ADSP-TS201S processor to be accessed directly between processors. The DSP's on-chip distributed bus arbitration logic provides simple, glue-free connections for systems containing up to eight adsp-ts201s processors and a host processor. Bus arbitration has round-robin priority. The bus lock supports readmodify write sequences that are inseparable from the semaphore. The bus fairness feature prevents a DSP from occupying the external bus for too long.

The DSP's four link ports provide a second path for interprocessor communication with a throughput of 4Gbytes per second. The cluster bus provides 1 gigabytes per second of throughput, and the inter-processor bandwidth (limited by the soc bandwidth) totals 4.8 gigabytes per second.

SDRAM controller

The sdram controller uses the external port and sdram control pins to control the data transfer of the adsp-ts201s processor to and from external synchronous dram (sdram) with a throughput of 32 bits or 64 bits per sclk cycle.

The SDRAM interface provides a glueless interface, standard SDRAM-16M-bit, 64M-bit, 128M-bit, 256M-bit and 512M-bit. The digital signal processor directly supports up to 4 groups of sdram of 64M words x 32 bits. The sdram interface is mapped into external memory in the unified memory map of each dsp.

EPROM interface

The ADSP-TS201S processor can be configured to boot from an external 8-bit EPROM through the external port at reset. An automatic process (after reset) loads the program from the eprom into memory. This process uses 16 cycles to wait for each read access. During the startup process, the BMS pin acts as an EPROM chip select signal. The eprom boot process uses DMA channel 0, which packs bytes into 32-bit instructions. Applications can also access eprom (write flash) via DMA during normal operation.

The EPROM or flash interface is not mapped into the DSP's unified memory map. It is a byte address space with a maximum limit of 16Mbytes (24 address bits). The EPROM or flash interface can be used after booting via DMA.

DMA controller

The on-chip DMA controller of the ADSP-TS201S processor has 14 DMA channels, providing zero-overhead data transfer without processor intervention. The dma controller operates independently and invisible to the dsp core, such that dma operations occur while the dsp core continues to execute program instructions.

The DMA controller performs DMA transfers between internal memory, external memory, and memory-mapped peripherals; internal memory on a common bus, host processor, or other DSPs on link port I/O; between external memory and external peripherals or between link port i/o; and performing dma transfers between an external bus master and internal memory or link port i/o. The controller performs the following DMA operations:

(1), external port block transmission. Four dedicated bidirectional DMA channels transfer blocks of data between the DSP's internal memory and any external memory or memory-mapped peripherals on the external bus. These transports support master mode and handshake mode protocols.

(2), link port transmission. Eight dedicated DMA channels (four transmit and four receive) transfer only four words of data between link ports and between link ports and internal or external memory. These transfers use only the handshake mode protocol. DMA priority at four

Receive channel: Automatic DMA transfer. Two dedicated unidirectional DMA channels transfer data received from external bus masters to internal memory or link port I/O. These transfers use only the slave mode protocol, and the external bus master must initiate the transfer.

The DMA controller provides the following additional functions: On-the-fly transfers. Flyby operations are performed only through the external port (DMA channel 0) and do not involve the DSP core. The dma controller acts as a pipe for transferring data from the i/o device to the external sdram memory.

During a transaction, the dsp relinquishes the external data bus; outputs address and memory select (mssd3–0); outputs iord, iowr, ioen, and rd/wr strobes; and responds to ack.

(1), DMA link. DMA chaining operations enable applications to automatically chain one sequence of DMA transfers to another for sequential transfers. Sequences can occur on different dma channels and have different transmission properties.

(2), two-dimensional transfer. The dma controller can access and transmit two-dimensional memory arrays on any dma transmit or receive channel. These transfers are accomplished by indexing, counting, and modifying registers in the X and Y dimensions.

Link port (LVD)

The DSP's four full-duplex link ports use low-voltage differential signaling (LVDS) technology to provide an additional four-bit receive and four-bit transmit I/O capability, respectively. With the ability to operate at double data rate, locking data at up to 500 MHz on the rising and falling edges of the clock, each link port can support up to 500 Mbytes/sec/direction with a maximum throughput of 4 Gbytes/sec .

The link port provides an optional communication channel for point-to-point interprocessor communication in multiprocessor systems. Applications can also boot using the link port.

Each link port has its own triple-buffered quadword input and double-buffered quadword output registers. The core of the DSP can write directly to the link port's transmit register and read data from the receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedicated link port DMA channels.

Each link port direction has three signals that control its operation. For the transmitter, lxclkout is the output transmit clock, lxacki is the handshake input that controls the data flow, and the lxbcmpo output indicates that the block transfer is complete. For the receiver, lxclkin is the input receive clock, lxacko is the handshake output that controls the flow of data, and the lxbcmpi input indicates that the block transfer is complete. The LXDATO3–0 pins are the transmitter’s data output bus, and the LXDATI3–0 pins are the receiver’s input data bus.

The application can program separate error detection mechanisms for send and receive operations (the application can use the checksum mechanism to achieve continuous link port transfers), the size of the packets, and the transfer speed in bytes.

Timers and General Purpose I/O

The ADSP-TS201S processor has one timer pin (TMR0E) that produces an output when the programmed timer counter expires, and four programmable general-purpose I/O pins (Flag3–0) that can function as unit inputs or outputs. As outputs, these pins can send signals to peripherals; as inputs, they can provide tests for conditional branches.

reset and start

The ADSP-TS201S processor has three reset levels:

(1), power-on reset - after the system is powered on (SCLK, all static inputs, with pins stable), the RST U input pin must be asserted (low).

(2), normal reset - for any chip reset reset after power-on, the RST_IN pin must be asserted (low).

(3) DSP core reset - When the SWRST bit is set in EMUCTL, the DSP core is reset, but not external ports or I/Os.

For normal operation, connect the RST_OUT pin to Pin in PIN. After reset, the ADSP-TS201S processor has four boot options to begin operation:

(1), start from EPROM.

(2) Start through an external host (host or other ADSP-TS201S processor).

(3), press the link port to guide.

(4), do not choose to start from the memory address.

With the "no boot" option, the ADSP-TS201S processor must start running from memory when one of the interrupts is asserted. The DSP-TS201S processor core always comes out of reset in an idle state and waits for an interrupt. Some interrupts in the interrupt vector table are initialized and enabled after reset.

For more information on boot options, see ee-200:adsp-ts20x tigersharc processor bootloader kernel operations on the emulated devices website ( ).

clock domain

The digital signal processor operates using a calculated ratio of the SCLK clock, as shown in Figure 5. The instruction execution rate is equal to cclk. The pll from sclk generates cclk, which is phase locked. The SCLKRATX pin defines the SCLK to CCLK clock multiplier (see Table 4 on page 12). The link port clock is generated by cclk through a software programmable divisor, and the soc bus works at 1/2cclk. Memory transfers to external and link port buffers run at socclk rate. SCLK also provides the clock input for the external bus interface and defines the AC specification reference for the external bus signals. The external bus interface operates at the SCLK frequency. The maximum sclk frequency is one quarter of the internal dsp clock (cclk) frequency.

sphere of power

The ADSP-TS201S processor has separate power connections for internal logic (VDD), analog circuits (VDD_A), I/O buffers (VDD_IO), and internal DRAM (VDD_DRAM) power supplies.

Note: The analog (VDD_A) supply powers the clock generator PLL. In order to generate a stable clock, the system must provide a clean power supply to the power input. The design must take great care to bypass the power supply.

Filtered reference voltage and clock

Figures 6 and 7 show possible circuits for filtering vref and sclk-vref. These circuits provide reference voltages for the switch voltage reference and the system clock reference.

development tools

The ADSP-TS201S processor supports a complete set of cross-core software and hardware development tools, including an analog device simulator and the VisualDSP++ development environment. Emulator hardware supporting other TigerSharec processors also fully emulates the ADSP-TS201S processor.

The visualdsp++ project management environment allows programmers to develop and debug applications. The environment includes an easy-to-use assembler (based on algebraic syntax), archiver (librarian/library generator), linker, loader, loop-accurate instruction-level simulator, C/C++ compiler, and includes DSP and math functions C/C++ runtime library. A key point of these tools is C/C++ code efficiency. The compiler has been developed for efficient conversion of C/C++ code to DSP assembly. dsp has architectural features that improve compilation efficiency of C/C++ code.

The visualdsp++ debugger has many important features. Plotting packages provide great flexibility to enhance data visualization. This graphical representation of user data enables programmers to quickly determine the performance of an algorithm. As the complexity of the algorithm increases, this capability will have greater and greater significance for the designer's development schedule, thereby increasing productivity. Statistical analysis enables programmers to non-invasively poll the processor as it runs the program. This feature unique to visualdsp++ enables software developers to passively collect important code execution metrics without disrupting the real-time nature of the program. Essentially, developers can quickly and efficiently identify bottlenecks in software. By using the profiler, the programmer can focus on those areas of the program that affect performance and take corrective action.

Debug C/C++ and Assembler with the VisualDSP++ debugger, programmers can: View mixed C/C++ and assembly code (interleaved source and object information)

(1), insert breakpoints; set conditional breakpoints on registers, memory and stack;

(2), tracking instruction execution; executing linear or statistical analysis of program execution;

(3), fill, dump, and graphically draw memory contents; perform source-level debugging; create custom debugger windows.

visualdsp++ide allows programmers to define and manage dsp software development. Its dialogs and property pages allow programmers to configure and manage all tigersharc processor development tools, including color syntax highlighting in the visualdsp++ editor. This capability allows programmers to: control how the development tool handles input and generates output; maintains one-to-one communication with the tool's command-line switches.

The visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored specifically to address the memory and time constraints of dsp programming. These capabilities enable engineers to develop code more efficiently, eliminating the need to start from scratch when developing new application code. vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. The vdk also supports scheduling methods based on priority, preemption, cooperation and time segmentation. Also, vdk is designed to be extensible. If an application does not use a particular feature, the support code for that feature will be excluded from the target system.

Because vdk is a library, developers can decide whether to use it or not. The vdk is integrated into the visualdsp++ development environment, but can also be used via standard command line tools. The development environment helps developers perform many error-prone tasks when using vdk, and helps manage system resources, automatically generate various vdk-based objects, and visualize system state when debugging applications that use vdk.

VCSE is an analog device technology for creating, using, and reusing software components (independent modules with important functions) to assemble software applications quickly and reliably. It is also used to download components from the web, put them into applications, and publish component archives from visual dsp++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to intuitively manipulate the location of code and data on the embedded system, view memory usage in color-coded graphs, easily move code and data to different areas of the DSP or external memory with mouse drags, and Check runtime stack and heap usage. The expert linker is fully compatible with existing linker definition files (ldf), allowing developers to move between graphical and textual environments.

The simulation equipment dsp simulator uses the ieee 1149.1jtag of the adsp-ts201s processor to test the access port, and monitors the target board processor during the simulation process. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and the processor stack. Non-intrusive in-circuit emulation is ensured by using the processor's jtag interface. The emulator does not affect the loading or timing of the target system.

In addition to the software and hardware development tools provided by the emulation device, third parties also provide a range of tools that support the TigerSharec processor family. Hardware tools include tigersharc processor pc add-in cards. Third-party software tools include dsp libraries, real-time operating systems, and block diagram design tools.

Assessment Toolkit

Analog Devices offers a range of EZ-Kit Lite evaluation platforms as a cost-effective way to learn more about developing or prototyping applications using analog device processors, platforms and software tools. Each EZ-KIT Lite includes an evaluation board and an evaluation kit for the VisualDSP++ development and debugging environment, including a C/C++ compiler, assembler and linker. Also includes sample application, power supply and USB cable. Evaluation versions of all software tools are limited to use with EZ-Kit Lite products.

The USB controller on the EZ-Kit Lite board connects the board to the USB port of the user's PC, enabling the VisualDSP++ evaluation kit to emulate the on-board processor in the circuit. This allows customers to download, execute and debug programs for the EZ-Kit Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, allowing the board to operate as a standalone unit without being connected to a PC.

With the full version of visualdsp++ installed (sold separately), engineers can develop software for ez-kit lite or any custom system. Connecting one of the analog device JTAG emulators to the EZ-KIT Lite board enables high-speed, non-intrusive emulation.

Design a simulator-compatible digital signal processing board (target)

The Analog Devices Family Simulator is the tool every dsp developer needs to test and debug hardware and software systems. The emulated device provides the ieee 1149.1jtag test access port (tap) on each jtag dsp. The simulator uses taps to access the internal features of the DSP, allowing developers to load code, set breakpoints, watch variables, watch memory, and inspect registers. The dsp must be stopped to send data and commands, but once the emulator is done, the dsp system will be set to run at full speed without affecting system timing.

To use these emulators, the target board must contain a header that connects the DSP's jtag port to the emulator. For more information on target board design issues, including mechanical layout, uniprocessor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator POD logic, see EE-68: Emulated Devices on the Emulated Devices website ( ) JTAG Emulation Technical Reference - Use the string "EE-68" in website searches. This documentation is regularly updated to keep up with improvements in emulator support.

Additional Information

This data sheet provides an overview of the architecture and functionality of the ADSP-TS201S processor. For more information on the core architecture and instruction set of the ADSP-TS201S processor, see ADSP-TS201 Tigershar Processor Hardware Reference and ADSP-TS201 Tigershar Processor Programming Reference. For more information on the development tools for this processor, see the VisualDSP++ TigerSharec Processor User Guide.

Pin function description

While the input pins of most ADSP-TS201S processors are usually synchronous to a specific clock, some are asynchronous. For these asynchronous signals, on-chip synchronization circuitry prevents metastability issues. The AC specification for asynchronous signals is used when the system design requires predictable cyclic behavior of these signals.

With pin function description

Some pins have alternate functions at reset. With options to set the DSP operating mode. During reset, the digital signal processor samples the strap option pins. The strap pins have internal pull-ups or pull-downs with default values. During reset, the DSP samples the default value if the strap pins are not connected to an overdriven external pull-up, pull-down, or logic load.