Overview
Features of Zilog Z80C30 and Z85C30 devices include:
Z85C30 - Optimized for non-multiplexed bus microprocessors.
Z80C30 - Optimized for multi-bus microprocessors.
Pins compatible with NMOS version.
Two independent 0 to 4.1 Mbit/sec full duplex channels. Each channel features a separate crystal oscillator, baud rate generator (BRG), and digital phase-locked loop (DPLL) for clock recovery.
Multiprotocol operation under program control; programmable for NRZ, NRZI or FM data encoding.
Asynchronous mode with 5 to 8 bits and 1, 1.5 or 2 stop bits per character, programmable clock factor, interrupt detection and generation; parity, overflow and framing error detection.
Sync mode, internal or external character synchronization on one or two sync characters, CRC generation and checking, CRC-16 or CRC-CCITT preset to 1 or 0.
SDLC/HDLC mode with comprehensive frame-level control, automatic zero insertion and deletion, I-field remainder handling, abort generation and detection, CRC generation and checking, and SDLC looping.
Software interrupt acknowledgement function (not available for NMOS).
Local loopback and auto loopback modes.
T1 digital trunking is supported.
Enhanced DMA support (not available for NMOS) 10 x 19-bit status FIFO 14-bit byte counter.
speed:
– Z85C3O-8.5, 10, 16. 384 MHz – Z80C3O-8, 10 MHz Additional features of Z85C30 only By default, some of the features listed below are available. Some of these (features with *) are disabled by default to maintain compatibility with existing Serial Communication Controller (SCC) designs and "programs enabled via WR7":
New programmable WR7 (write to register 7 prime) to enable new functions. Improvements to sdlc mode that support synchronous communication:
- Improved functionality to facilitate sending frames back to back.
- Automatic SDLC open flag transfer.
– Automatically send underrun/EOM latch reset in SDLC mode.
– Automatically turn off RTS.
– After turning off the flag, the TXD pin is forced high in SDLC NRZI mode.
– Complete CRC reception.
- Improved response to status FIFO abort sequence.
– Automatically send CRC generator preset/reset.
– Extended read and write registers. * – Write data set timing improvements. Improved communication timing: ·
–3 to 3.6 pclk access recovery time.
– Programmable DTR/REQ timing.
– The falling edge required to write data to the WR setup time is now eliminated.
– Shorten internal timing. Additional features include: ·
– Extended read function to read the written value back into the write register. * – Lock error during read.
–RRO, bit D7 and RR10, bit D6 now have reset defaults.
General Instructions
The Z80C30/Z85C30 Serial Communication Controllers (SCCs) are pin and software compatible CMOS members of the SCC family introduced by Zilog® in 1981 . It is a dual-channel, multi-protocol data communication peripheral that easily interfaces to the CPU via a multiplexed or non-multiplexed address/data bus.
The advanced CMOS process has lower power consumption, higher performance and higher noise immunity. The programming flexibility of the internal registers allows the scc to be configured for various serial communication applications.
Block diagram of the SCC.

Many on-chip functions, such as baud rate generator (brg), digital phase-locked loop (dpll), and crystal oscillator, reduce the need for external logic.
Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high-speed SDLC transfers using a DMA controller.
scc handles asynchronous formats, synchronous byte-oriented protocols such as ibm bisync, and synchronous bit-oriented protocols such as hdlc and ibm sdlc. This device supports virtually any serial data transfer application (eg, cassette tapes, floppy disks, tape drives, etc.).
The device can generate and check CRC codes in any synchronization mode and can be programmed to check data integrity in various modes. The SCC also contains equipment for modem control in both channels. Modem controls can be used for general purpose I/O in applications that do not require these controls. Daisy-chain interrupt hierarchies are also supported.

Pin Description
Z85C30/Z80C30 Common Pin Functions The following sections describe the common pin functions of the Z85C30 and Z80C30 devices:
Clear to Send (input, active low) - If these pins are programmed to auto-enable, a low on the input will enable the corresponding transmitter. These pins can be used as general purpose inputs if not programmed to automatically enable. Both inputs are Schmitt trigger buffered to accommodate slow rise time inputs. The scc detects pulses on these inputs and can interrupt the cpu on two logic level transitions.
Data Carrier Detect (input, low) - These pins are enabled as receivers if programmed to auto-enable. Otherwise, these pins function as general-purpose input pins. Both pins are Schmitt Trigger buffered to accommodate slow rise time signals. The SCC detects pulses on these pins and can interrupt the CPU on two logic level transitions.
DTR/Demand, DTR/Demand Data Terminal Ready/Request (OUTPUT, LOW) - These outputs follow the state programmed into the DTR bit. They can also be used as general purpose outputs or request lines for dma controllers.
Interrupt Enable (input, high) - iei together with ieo form an interrupt daisy chain when there are multiple interrupt driven devices. A high iei indicates that no other high-priority device is servicing or requesting an interrupt.
Interrupt Enable Output (OUT, HIGH) - only when iei is high and
The CPU did not service the SCC interrupt, or the SCC did not request an interrupt (interrupt acknowledgement cycle only). ieo is connected to the iei input of the next lower priority device, so interrupts from lower priority devices are disabled.
International Interrupt Request (Output, Open Drain, Low) - This signal activates when the SCC requests an interrupt.
NETAK INTERRUPT ACK (input, LOW) - This signal indicates an active interrupt acknowledge cycle. During this cycle, the SCC interrupt daisy chain ends. When rd is active, scc places an interrupt vector on the data bus (if iei is high). The notch is latched by the rising edge of PCLK.
clock (input) - This is the main scc clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK does not need to have any phase relationship with the main system clock. The maximum transfer rate is 1/4 pclk.
Receive Data (input, high) - These signals receive serial data at standard ttl levels.
Receive/Transmit Clock (input, low) - These pins can be programmed for several different modes of operation. In each channel, rtxc can provide receive clock, transmit clock, baud rate generator clock or digital phase clock. -
Lock the loop. These pins can also be programmed to function as crystal oscillators along with the corresponding sync pins. In asynchronous mode, the receive clock can be 1, 16, 32 or 64 times the data rate.
Request to send (output, active low) - When the request to send (rts) bit is set to write to register 5 (see Figure 9 on page 19), the RTS signal goes low. When the RTS bit is reset in asynchronous mode and automatically enabled, the signal goes high after the transmitter is empty. In synchronous mode, it strictly follows the state of the rts bit.
When auto enable is off, the rts pin can be used as a general purpose output.
Synchrosync (input or output, LOW) - These pins are used as inputs, outputs or parts of the crystal oscillator circuit. In asynchronous receive mode (Crystal oscillator option unchecked), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the sync/seek status bits in read register 0, but have no other function.
These lines also function as inputs in external sync mode where the crystal oscillator is not selected. In this mode, the sync must be driven low for two receive clock cycles after the last bit in the sync character is received. The set of roles begins on the rising edge of the receive clock before synchronization is activated.
In internal sync modes where the crystal oscillator is not selected (single-sync and double-sync), these pins function as outputs and are only active during the portion of the receive clock cycle that recognizes the sync character. This synchronization condition is not locked. These outputs are active each time a sync pattern is recognized (regardless of character boundaries). In sdlc mode, these pins act as outputs and are valid when flags are received.
transmit_data(output, high) - These output signals transmit serial data at standard ttl levels.
Transmit/Receive Clock (input or output, low) - These pins can be programmed in several different modes of operation. The trxc can provide the receive clock or transmit clock in input mode, or the output of a digital phase-locked loop, crystal oscillator, baud rate generator, or transmit clock in output mode.
w/demand, w/demand wait/request (output, open drain when programmed for wait function, driven high or low when programmed for request function) - these dual purpose outputs can be programmed as the request lines of the dma controller, or programmed Wait line for synchronizing cpu with scc data rate. Reset state to wait.
Channel A/Channel B (Input) - This signal selects the channel on which a read or write operation occurs.
Chief Engineer Chip Enable (input, low) - This signal selects scc for read or write operations.
Data Bus (Bidirectional, Tri-State) - These lines carry data and commands to and from the SCC.
D/P Data/Control Selection (input) - This signal defines the type of information to be transmitted to or from the scc. High indicates data transfer; low indicates command.
RdRead(input, low) - This signal represents a read operation, and when SCC is selected, the bus driver for SCC is enabled. During the interrupt acknowledgement cycle, if the SCC is the highest priority device requesting an interrupt, this signal transfers the interrupt vector onto the bus.
write(input, low) - When SCC is selected, this signal indicates a write operation. The coincidence of rd and wr is interpreted as a reset.
Elf Address/Data Buses (Bidirectional, High, Tri-State) - These multiplexed lines carry register addresses as well as data or control information to the scc.
Address Strobe (input, low) - The address on AD7–AD0 is latched by the rising edge of this signal.
Elf Chip Select 0 (input, low) - This signal is locked at the same time as the address on AD7–AD0 and must be active for the expected bus transaction to occur.
Chip Select 1 (input, high) - The second select signal must also be active before the expected bus transaction occurs. CS1 must remain active throughout the transaction.
Data Strobe (input, low) - This signal provides timing for data transfers in and out of the SCC. If as and ds coincide, this sink is interpreted as a reset.
read/write (input) - This signal specifies whether the operation to be performed is a read or a write.

Function description

The architecture of SCC is described as follows:
As a data communication device that transmits and receives data in various protocols.
As a microprocessor peripheral, the SCC provides valuable functions such as vectored interrupts and DMA support.
The scc's peripherals and data communications are described in the following sections.

When polling, all interrupts are disabled. Three status registers in the SCC are automatically updated when any function is performed. For example, end of frame in sdlc mode sets a bit in one of the status registers. The purpose of polling is for the cpu to periodically read the status register until the register contents indicate that data needs to be transferred. Only one register is read, and depending on its contents, the CPU either writes data, reads data, or continues. Two bits in the register indicate that data transfer is required. Another method is to poll the interrupt pending register to determine the source of the interrupt. The status of both channels is in one register.
interrupt
SCC's interrupt structure supports vectorized and nested interrupts. The interrupt acknowledgement function (intack pin) of SCC supports nested interrupts.
This allows the CPU to recognize the occurrence of an interrupt and re-enable a higher priority -
Ority interrupted. A high-priority scc interrupt or another high-priority device can interrupt the cpu due to an intack cycle releasing the int pin from its active state.
When the scc responds to an interrupt acknowledge signal (intack) from the cpu, an interrupt vector can be placed on the data bus. This vector is written with wr2 and can be read with rr2a or rr2b. To speed up interrupt response time, scc can modify three bits in this vector to indicate status. If the vector is read in channel A, the state is never included. If the vector is read in channel B, the state is always included.
Each of the six interrupt sources in the SCC (transmit, receive, and external/status interrupts in both channels) has three bits associated with the interrupt source.
Interrupt Pending (IP), Interrupt Service (IUS) and Interrupt Enable (IE). Operation of the IE drill is straightforward. If the ie bit is set for a given interrupt source, that source can request an interrupt. The exception is when the MIE (Master Interrupt Enable) bit in WR9 is reset and an interrupt cannot be requested. The ie bit is write-only.
The other two are related to the interrupt priority chain. As a microprocessor peripheral, scc can only request an interrupt when no higher priority device is requesting an interrupt (ie, when iei is high). If the device in question requests an interrupt, it pulls the int low. The cpu responds with an stack and the interrupt device puts the vector on the data bus.

The SCC can also perform an interrupt acknowledgement cycle through software. In some CPU environments, it is difficult to create an interpolated signal with the necessary timing to acknowledge interrupts and allow interrupt nesting. In these cases, a software command to scc can be used to create the stack signal.
In scc, the interrupt pending (ip) bit indicates that interrupt servicing is required. when a
The IP bit is 1, the IEI input is high, the INT output is low, and an interrupt is requested. In scc, if the ie bit is not set by enabling interrupts, the source's ip is never set. The IP bits are readable in RR3A.
The IUS bit indicates that an interrupt request is being serviced. If an ius is set, all interrupt sources with lower priority in and outside scc will be blocked from requesting interrupts.
Internal interrupt sources are suppressed by the state of the internal daisy chain, while lower priority devices are suppressed by the SCC's IEO output being pulled low and propagated to subsequent peripherals. An IUS bit is set during the interrupt acknowledgement cycle if no higher priority device requests an interrupt.
There are three types of interrupts:
Transmit Receive External/Status Each interrupt type is enabled under program control, Channel A has priority over Channel B, and Receiver, Transmit, and External/Status interrupts are prioritized within each channel in that order.
When enabled, the receiver interrupts the CPU in one of three ways:
Interrupt on First Received Character or Special Receive Condition Interrupt on All Received Characters or Special Receive Condition Only on Special Received Condition Interrupt on First Character or Special Condition and Interrupt on Special Condition Usually used with block transfer mode . Special reception conditions are one of the following conditions. Receiver overflow, framing error in asynchronous mode, end of frame in sdlc mode, and optional parity error. The special receive condition interrupt is different from the normal receive character, the interrupt can be used only by the state in the vector during the interrupt acknowledgement cycle. In the interrupt of the first received character, any time after the interrupt of the first received character, the interrupt of the special receive condition will occur.
The primary function of the external/status interrupt is to monitor the external/status interrupts of the cts, dcd, and sync pins. interrupt (async mode), abort (sdlc mode) or eop (sdlc loop mode) sequence. Interrupts caused by an abort or EOP have a special feature that allows the SCC to interrupt when an abort or EOP sequence is detected or terminated. This feature facilitates proper termination of the current message in SDLC mode, proper initialization of the next message, and precise timing of abort conditions in external logic. In sdlc loop mode, this feature allows secondary stations to identify the master station, restoring control of the loop during the polling sequence.
Software interrupt acknowledgement

On the cmos version of scc, the scc interrupt acknowledgement cycle can be initiated by software. If Write Register 9 (WR9), Bit D5, is set, then Read Register 2 (RR2) will cause an interrupt acknowledge cycle to be executed internally. Like a hardware installation cycle,
A software acknowledgement causes the INT pin to return high and the IEO pin to return low, and sets the ius latch for the highest priority interrupt pending.
Similar to using hardware input signals, the software acknowledgement cycle requires a reset top IUS command to be issued in the interrupt service routine. The highest IUS command needs to be reset whenever an interrupt acknowledgement cycle (hardware or software) is used. If rr2 is read from channel A, an unmodified vector is returned. If rr2 is read from channel b, the vector is modified to indicate the source of the interrupt. When bit 05 is set to 1, the vector including state (vis) and no vector (nv) bits in wr9 are ignored.
When not in use, the Interpolate and IEI pins should be pulled to VCC through a resistor (10 kΩ typical).
CPU/DMA block transfer
scc provides block transfer mode to accommodate cpu block transfer function and dma controller. The block transfer mode uses the wait/reouest output in conjunction with the wait/request bits in wr1. Under software control, the wait/reouest output can be defined as a wait line in cpu block transfer mode or a request line in dma block transfer mode.
For the dma controller, the scc request output indicates that the scc is ready to transmit -
To transfer data to or from memory to the cpu, the wait line indicates that the escc is not ready to transfer data, thus requesting the cpu to extend the i/o cycle. DTR/
The request line allows full duplex operation under DMA control.
SCC data communication capability

The SCC provides two independent full-duplex programmable channels for any common asynchronous or synchronous data communication protocol. Each data communication channel has the same characteristics and capabilities.

Asynchronous mode transmission and reception are done independently on each channel, with 5 to 8 bits per character, plus optional parity. The transmitter can provide one, one and half or two stop bits per character and can provide an interrupt output at any time. The receiver interrupt detection logic interrupts the cpu when the start and end of an interrupt is received.
After a low level is detected at the receive data input (rxda or rxdb pins), the signal half-bit time is checked by a transient spike suppression mechanism to prevent receive spikes. If the low bit is not sustained (temporarily), the character assembly process will not start.
Framing and overflow errors are detected and buffered along with the part of the character where the error occurred. Vectored interrupts allow fast servicing of or error conditions using dedicated routines. A built-in checking process avoids framing errors being interpreted as new start bits. Framing errors cause a half-bit time to be added at the point where the search for the next start bit begins.
SCC does not require symmetrical transmit and receive clock signals - this feature allows the use of multiple clock sources. The transmitter and receiver process data at the rate provided to the receive and transmit clock inputs. In asynchronous mode, the sync pin can be programmed as an input for monitoring functions such as a ring indicator.
Sync mode
scc supports byte- and bit-oriented synchronous communication. There are several ways of handling byte-oriented synchronization protocols. They allow character synchronization using 6- or 8-bit sync characters (monosync), 12- or 16-bit sync patterns (bisync), or external sync signals. Remove leading sync characters without interrupting the CPU.
5-bit or 7-bit sync characters are detected in SCC with 8-bit or 16-bit patterns by overlapping the larger pattern onto multiple incoming sync characters

The crc check in synchronous byte-oriented mode is delayed by one character time so that the CPU can disable the crc check for a specific character. This feature allows protocols such as ibm bisync to be implemented.
Supports CRC-16 (x16+x15+x12+1) and CCITT (x16+x12+x5+1) error checking polynomials. Either polynomial can be selected in all synchronization modes. You can set the CRC generator and checker to "all 1s" or "all 0s". SCC also provides a function to automatically transmit CRC data when no other data is available for transmission. This feature allows high-speed transfers under DMA control without CPU intervention at the end of the message.
When no data or CRC is sent in sync mode, the transmitter inserts 6, 8 or 16 bit sync characters regardless of the programmed character length.
SDLC mode

scc supports synchronous bit-oriented protocols such as sdlc and hdlc by performing automatic flag sending, zero insertion, and crc generation. A special command is used to abort a frame in transit. At the end of the message, scc automatically sends the crc and trailing flags when the sender is running low. The transmitter can also be programmed to send idle lines consisting of consecutive marker characters or stable marker conditions.
If an undertransmission occurs in the middle of a message, an external/status interrupt alerts the CPU of this state change and issues an abort. scc can also be programmed to send an abort itself in case of underrun, freeing up the cpu for this task. One to eight bits can be sent per character, allowing messages to be received without a priori information about the structure of the character in the information field of the frame.
The receiver automatically acquires synchronization on the pre-mark of the frame
SDLC or HDLC and provide a sync signal on the sync pin (interrupts can also be programmed). The receiver can be programmed to search for frames addressed by a single byte (or four bits within a byte) of a user-selected address or the global broadcast address. In this mode, frames that do not match the user-selected or broadcast address are ignored.
The number of address bytes is expanded under software control. For receive data, you can select a break on the first received character, or a break on every character, or only in special cases (end of frame). The receiver automatically removes all 0s inserted by the transmitter during character combination, and crc is also calculated and automatically checked to verify frame transmission. At the end of the transmission, the status of the received frame is available in the status register. In sdlc mode, the scc must be programmed to use the sdlc crc polynomial, but the generator and checker can be preset to all 1s or all 0s. The crc is inverted before transmission and the receiver checks against the bit pattern 0001110100001111.
nrz, nrzi or fm encoding can be used in any 1x mode. The parity options available in asynchronous mode are available in synchronous mode.
SDLC loop mode In addition to normal sdlc, scc also supports sdlc loop mode. In an sdlc loop, the primary controller station manages the flow of message traffic and any number of secondary stations on the loop. In the sdlc loop mode, the scc performs the function of the auxiliary station, while the scc running in the regular sdlc mode acts as the controller. The SDLC loop mode can be selected by setting WR10 bit D1.
A secondary station in the sdlc loop always listens for messages sent around the loop and relays these messages to the rest of the loop by resending them with a one-bit time delay. Auxiliary stations only place their own messages on the loop at certain times.
The controller indicates that the secondary station can send a message by sending a special character called end of poll (EOP) around the loop. The EOP character is bit pattern 11111110. This bit pattern is unique and easy to identify due to zero insertion during the message.
When the secondary station contains the message to transmit and recognizes the EOP on the line, it changes the last binary 1 of the EOP to a 0 before transmitting. The effect of this change is to convert the EOP to a sequence of flags. The secondary station now puts its message on the loop and terminates the message with EOP. Any secondary station further down the loop, the message it sends appends its message to the message of the first secondary station through the same process. Any secondary station that has no message sent echoes the incoming message, and it is forbidden to place messages on loops (except when EOP is recognized). In sdlc loop mode, nrz, nrzi and fm encodings can be used.
The SCC's ability to receive high-speed back-to-back SDLC frames is maximized by a 10-deep 19-wide status FIFO. When enabled (via WR15, bit D2), it provides
DMA's ability to continue transferring data into memory so that the CPU can inspect the message later. For each sdlc frame, store a 14-bit byte count and 5 status/error bits. The byte count and status bits are accessed by reading registers 6 and 7. Read registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status fifo is separate from the 3-byte receive data fifo.
baud rate generator
Each channel in the SCC contains a programmable baud rate generator (BRG). Each generator consists of two 8-bit time constant registers, which form a 16-bit time constant, a 16-bit down-counter, and a flip-flop at the output to generate a square wave. At startup, the output flip-flop is set to a high state, the value in the time constant register is loaded into the counter, and the counter begins to count down. The output of the BRG toggles when it reaches 0, the value in the time constant register is loaded into the counter, and the process repeats. The time constant can be changed at any time, but the new value will not take effect until the next time the counter is loaded.
The output of brg can be used as transmit clock and/or receive clock. It can also drive digital phase-locked loops (see digital phase-locked loops).
If the receive clock or transmit clock is not programmed to come from the trxc pin, the output of brg can be echoed through the trxc pin. The following formula relates the time constant to the baud rate, where pclk or rtxc is the brg input frequency in Hertz. The clock mode is 1, 16, 32 or 64, as selected in bits d6 and d7 of write register 4.
Select 1 for synchronous operation mode and 16, 32 or 64 for asynchronous mode.

Automatic echo and local loopback
The SCC is able to automatically echo all information it receives. This feature is mainly useful in async mode, but also works in sync and sdlc modes. Auto-echo mode (tx0 is rx0) is used with nrzi or fm encoding, there is no additional delay because the data stream is not decoded before retransmission. In auto echo mode,
When the transmitter is enabled, the CTS input will be ignored (although transitions on this input will still cause an interrupt, if programmed). In this mode the transmitter is actually bypassed by the programmer who is responsible for turning off the transmitter interrupt and waiting/
send request.
scc can also do local loopback. In this mode, txd or rxd is like auto
echo mode. However, in local loopback mode, internal transmit data is bound to internal receive data, and rxd is ignored (except for echo via txd). CTS
The DCD input is also ignored when transmit and receive are enabled. However, transitions on these inputs still cause interrupts. The local loopback works in asynchronous, synchronous and sdlc modes, and the data stream is encoded in nrz, nrzi or fm.
sdlc fifo frame status fifo enhancement
The scc's ability to receive high-speed back-to-back sdlc frames is maximized by a 10-deep 19-wide state fifo. When enabled (via WR15, bit D2), it enables the DMA to continue transferring data into memory so that the CPU can check for messages later. For each sdlc frame, store a 14-bit byte count and 5 status/error bits. The byte count and status bits are accessed by reading registers 6 and 7. Read registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status fifo is separate from the 3-byte receive data fifo.
When the enhancements are enabled, the read status in register 1 (rr1) and the byte count of the sdlc frame are stored in a 10 x 19 bit status fifo. This arrangement allows the DMA controller to transfer the next frame to memory while the CPU verifies that the message was received correctly.
To summarize the operation; data is received, assembled and loaded into an 8-byte fifo before being transferred to memory by the DMA controller. When the flag is received at the end of the sdlc frame, the frame byte count from the 14-bit counter and 5 status bits is loaded into the status fifo for verification by the CPU. The crc checker resets automatically in preparation for the next frame to start immediately. Since the byte count and state are saved for each frame, the integrity of the message will be verified later. Up to 10 frames of status information are stored before a status fifo overflow occurs.
If a frame is terminated by an abort, the byte count will be loaded into the state fifo and the counter will be reset for the next frame.
FIFO detail enable/disable

This FIFO is enabled when WR15 bit D2 is set and the SCC is in SDLC/HDLC mode. Otherwise, the status register contents bypass the fifo and go directly to the bus interface (the fifo pointer logic is reset on disable or pass-through or power-on reset). scc is backward compatible with nmos z8530 when fifo mode is disabled. FIFO mode is disabled on power-up (WR15 D2 is set to 0 on reset). The effect of backward compatibility on the register set is that rr4 is the image of rr0, rr5 is the image of rr1, rr6 is the image of rr2, and rr7 is the image of rr3. See Figure 16 on page 30 for more details on the added registers. The state of the fifo enable signal is obtained by reading bit d2 of rr15. This bit is set to 1 if the fifo is enabled; otherwise, it is reset.
Read Operation When the WR15 bit D2 is set and the FIFO is not empty, the next read data from the status register RR1 or registers RR7 and RR6 comes from the FIFO. Reading the status register rr1 causes one position of the fifo to become empty. Read the status after reading the byte count, otherwise the count is incorrect. It is disabled until the fifo underflows. In this case, the multiplexer is toggled, allowing the status to be read directly from the status register. The data read from rr7 and rr6 contains undefined bits. Bit D6 of rr7 (fifo data available) determines whether the status data is from the fifo or directly from the status register, the status register is set to 1 when the fifo is not empty. Not all status bits are stored in the fifo. All transmit, parity and eof bits bypass the fifo. The status bits sent over the fifo are the remaining bits (3), overflow and crc errors.

The sequence of operations for the byte count and fifo logic is to read the registers in the following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic to prevent the fifo from being cleared when multiple reads from rr1. Read the lock fifo empty/full status bit (d6) from rr7 and direct the status multiplexer to read from the scc megacell, not from the status fifo (since the status fifo is empty). Reading from rr1 allows reading entries from the fifo (if the fifo is empty, add logic to prevent the fifo underflow condition).
Write When the end of the sdlc frame (eof) is received and the fifo is enabled, the contents of the status and byte count registers are loaded into the fifo. The eof signal is used to increase the fifo. If the fifo overflows, rr7, bit d7 (fifo overflow) is set to indicate overflow. This bit and the fifo control logic are reset by disabling and re-enabling the fifo control bit (wr15, bit 02).

programming
The scc contains write registers in each channel that are individually programmed by the system to configure the functional characteristics of the channel.
Z85 C30
In scc, the data register is directly addressed by selecting a high level on the d/c pin. For all other registers (except wr0 and rr0), writing a write register requires two writes, and reading a read register requires one write and one read. The first write is wr0 and contains three bits pointing to the selected register. The second write is the actual control word for the selected register, and if the read is the second operation, the selected read register is accessed. All scc registers, including data registers, can be accessed in this way. The pointer bits are automatically cleared after a read or write operation so that wr0 (or rr0) can be addressed again.
All SCC registers of the elf are directly addressable. Command control issued in wr0b
scc decodes the address placed on the address/data bus at the beginning of a read or write cycle. In right-shift mode, the channel selection A/B is taken from AD0 and the state of AD5 is ignored. In left shift mode, the channel selection A/B is taken from AD5 and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits, and the register addresses occupy AD4-AD1.
The Z85C30/Z80C30 setup initialization system program first issues a series of commands to initialize the basic operating mode. Next are other commands that qualify the conditions in the selected pattern. For example, in asynchronous mode, the character length, clock rate, number of stop bits, and parity must first be set. Set the interrupt mode and finally enable the receiver and transmitter.
write register
scc contains 15 write registers for the 80c30 and 16 write registers for the 85c30 (plus one more write register if calculating the transmit buffer). These write registers are individually programmed to configure the functional "personality" of the channel. The two channels share two registers (WR2 and WR9), which are accessed through one of the channels. WR2 contains interrupt vectors for both channels, while WR9 contains interrupt control bits and reset commands.
Write to Register 0 (non-multiplexed bus mode) Write to Register 1

Interrupt acknowledgement cycle timing. Time interval moves down, falling edge of rd, internal and external iei/ieo daisy chain is fixed.
If there is a pending interrupt in the SCC and IEI is high when RD falls, the acknowledge cycle is used for the SCC. In this case, the SCC can be programmed to respond by lowering rd by placing its interrupt vector on d7-d0. Then set the appropriate interrupt inside the service latch.
If an external daisy chain is not used, AC parameter 38 is required to account for the interrupt priority daisy chain inside the SCC. If an external daisy chain is used, the formula in "AC Characteristics, Read/Write Timing Table 6, Note 5" on page 47 must be followed to calculate the settling time for the desired daisy chain.

write register bit function read register
scc contains 10 read registers (11, counting the receive buffers (rr8) in each channel). Four of these can be read for status information (rr0, rr1, rr10, and rr15). Read two registers (RR12 and RR13) to learn the baud rate generator time constant. rr2 contains either the unmodified interrupt vector (channel a) or the vector modified by state information (channel b). RR3 contains the Interrupt Pending (IP) bit (Channel A only – Figure 19). rr6 and rr7 contain the information in the sdlc frame status fifo, but only read when wr15 d2 is set read register 0 read register 3
read register bit function
Z85C30 Timing
scc generates internal control signals related to pclk from wr and rd. pclk has no phase relationship with wr and rd, and the circuit that generates the internal control signal provides time for the metastable condition to disappear. This produces pclk-related recovery times. Recovery time only applies between bus transactions involving scc.
The recovery time required for correct operation is specified from the falling edge of wr or rd in the first transaction involving scc to the falling edge of wr or rd in the second transaction involving scc. Regardless of which register or channel is accessed, this time must be at least 3 PCLKs.
The Z85C30 timings are described below:
Read Cycle Timing Write Cycle Timing Interrupt Acknowledge Cycle Timing Read Cycle Timing. The address and state on A/B and D/C must remain stable throughout the cycle. If ce falls after rd falls, or ce rises before rd rises, effective rd shortens.
Read cycle timing Write cycle timing. The address and state on A/B and D/C must remain stable throughout the cycle. If ce falls after wr falls, or ce rises before wr rises, the effective wr shortens. Data must be valid before the rising edge of wr.
Write cycle timing interrupt acknowledgement cycle timing. Time interval moves down, falling edge of rd, internal and external iei/ieo daisy chain is fixed.
If there is a pending interrupt in the SCC and IEI is high when RD falls, the acknowledge cycle is used for the SCC. In this case, the SCC can be programmed to respond by lowering rd by placing its interrupt vector on d7-d0. Then set the appropriate interrupt inside the service latch.
If an external daisy chain is not used, AC parameter 38 is required to account for the interrupt priority daisy chain inside the SCC. If an external daisy chain is used, the formula in "AC Characteristics, Read/Write Timing Table 6, Note 5" on page 47 must be followed to calculate the settling time for the desired daisy chain.
Interrupt acknowledgement cycle timing
Z80C30 Timing
The SCC generates internal control signals from AS and DS associated with PCLK. Since pclk has no phase relationship with as and ds, the circuits that generate these internal control signals must provide time for the metastable condition to disappear. This produces pclk-related recovery times. Recovery time only applies between bus transactions involving scc. The recovery time required for proper operation is specified -
From the falling edge of ds in the first transaction involving scc to the falling edge of ds in the second transaction involving scc. The timing of the Z80C30 device is as follows:
Read Cycle Timing Write Cycle Timing Interrupt Acknowledge Cycle Timing Read Cycle Timing

read register bit function
Z85C30 Timing
scc generates internal control signals related to pclk from wr and rd. pclk has no phase relationship with wr and rd, and the circuit that generates the internal control signal provides time for the metastable condition to disappear. This produces pclk-related recovery times. Recovery time only applies between bus transactions involving scc.
The recovery time required for correct operation is specified from the falling edge of wr or rd in the first transaction involving scc to the falling edge of wr or rd in the second transaction involving scc. Regardless of which register or channel is accessed, this time must be at least 3 PCLKs.
The Z85C30 timings are described below:
Read Cycle Timing Write Cycle Timing Interrupt Acknowledge Cycle Timing Read Cycle Timing. The address and state on A/B and D/C must remain stable throughout the cycle. If ce falls after rd falls, or ce rises before rd rises, effective rd shortens.
Read Cycle Timing Write Cycle Timing
The address and state on A/B and D/C must remain stable throughout the cycle. If ce falls after wr falls, or ce rises before wr rises, the effective wr shortens. Data must be valid before the rising edge of wr.
Write cycle timing interrupt acknowledgement cycle timing. Time interval moves down, falling edge of rd, internal and external iei/ieo daisy chain is fixed.
If there is a pending interrupt in the SCC and IEI is high when RD falls, the acknowledge cycle is used for the SCC. In this case, the SCC can be programmed to respond by lowering rd by placing its interrupt vector on d7-d0. Then set the appropriate interrupt inside the service latch.
If an external daisy chain is not used, AC parameter 38 is required to account for the interrupt priority daisy chain inside the SCC. If an external daisy chain is used, the formula in "AC Characteristics, Read/Write Timing Table 6, Note 5" on page 47 must be followed to calculate the settling time for the desired daisy chain.
Interrupt acknowledgement cycle timing
Z80C30 Timing
The SCC generates internal control signals from AS and DS associated with PCLK. Since pclk has no phase relationship with as and ds, the circuits that generate these internal control signals must provide time for the metastable condition to disappear. This produces pclk-related recovery times. Recovery time only applies between bus transactions involving scc. The recovery time required for proper operation is specified -
From the falling edge of ds in the first transaction involving scc to the falling edge of ds in the second transaction involving scc. The timing of the Z80C30 device is as follows:
Write Cycle Timing Interrupt Acknowledge Cycle Timing Read Cycle Timing. The address on AD7-AD0 and the state of CS0 and built-in are latched by the rising edge of AS. R/W must be high to indicate a read cycle. CS1 must also be high for a read cycle to occur. The data bus driver in scc is then enabled when DS is low.
The read cycle counts the write cycle count. The address on AD7-AD0 and the state of CS0 and built-in are latched by the rising edge of AS. R/W must be low to indicate a write cycle. cs1 must be high for write cycle to occur ds low strobe data to write cycle timing interrupt acknowledge cycle timing
The address on AD7–AD0 and the state of CS0 and Intack are latched by the rising edge of AS. If the stack is low, address and cs0 are ignored. During the interrupt acknowledgement period, the status of R/W and CS1 is also ignored. Between the rising edge of as and the falling edge of ds, the internal and external IEI/IEO daisy chains are fixed. If there is
Interrupts in SCC are pending, IEI is high when DS falls, and the acknowledgment cycle is ready for SCC. In this case, the SCC is programmed to respond to RD low by setting the SCC's interrupt vector on D7-d0 and internally setting the appropriate interrupt under the service latch.
Interrupt Acknowledgement Period Timing Electrical Characteristics
The electrical characteristics of the Z80C30 and Z85C30 devices are described in the following sections.
Absolute Maximum Ratings greater than those listed in Table 3 may cause permanent damage to the device. This is the stress rating only. Operation of the device under any conditions beyond those described in the operating section of this specification is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Z85C30 read/write timing diagram

Z85C30 read/write timing parameters