feature

5V power supply; 50 MHz speed; on-chip cos look-up table On-chip, 10-bit DAC; serial loading; power down option; temperature range: -40°C to +85°C; 200 mW power consumption; 16-lead TSSOP.

application

Frequency stimulation/waveform generation; frequency phase tuning and modulation; low power RF/communication systems; liquid and gas flow measurement; sensory applications: proximity, motion and defect detection; testing and medical equipment.

General Instructions

The AD9835 is a numerically controlled oscillator that uses a phase accumulator, COS look-up table, and 10-bit digital-to-analog converter integrated on a single CMOS chip. Provides modulation capabilities for phase modulation and frequency modulation.

Supports clock frequencies up to 50 MHz. The frequency accuracy can be controlled at one part in 4 billion. Modulation is achieved by loading registers through the serial interface. A power down bit allows the user to power down the AD9835 when not in use; power consumption is reduced to 1.75 mW. This part is available in the 16-lead TSSOP package.

the term

Integral nonlinearity

This is the maximum deviation of any code from a straight line through the endpoints of the transfer function. The endpoint of the transfer function is zero scale, 0.5lsb below the first code transition (000). …00 to 000. ...01) and full scale, 0.5 LSB point above the last code transition (111). …10 to 111. …11). Errors are expressed in lsb.

Differential nonlinearity

This is the difference between the measured and ideal 1lsb variation between two adjacent codes in the DAC.

Signal to (Noise + Distortion)

Signal-to-noise ratio (noise + distortion) is the signal-to-noise ratio measured at the output of the dac. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (f/2), excluding the DC component. The signal to (noise + distortion) depends on the number of quantization levels used in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by MCLK

Signal to (Noise + Distortion) = (6.02N + 1.76) dB, where N is the number of bits. So, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the rms value of the harmonics to the rms value of the fundamental. For the AD9835, THD is defined as:

where v is the rms amplitude of the fundamental and v1, v2, v3 and v4 are the rms amplitudes of the second to sixth harmonics.

output compliance

Output compliance refers to the maximum voltage that can be produced at the output of the dac to meet specification requirements. When generating voltages greater than those specified for output compliance, the AD9835 may not meet the specifications listed in the data sheet.

Spurious free dynamic range

With the frequency of interest, the harmonics of the fundamental frequency and the image of the mclk frequency appear at the output of the dds device. Spurious-free dynamic range (sfdr) refers to the largest spur or harmonic present in the frequency band of interest. Broadband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth ±2 mhz fundamental frequency. Narrowband sfdr gives the attenuation of the largest spur or harmonic near the fundamental frequency within a ±50khz bandwidth.

clock feedthrough

There will be feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9835 output spectrum.

theory of operation

A sine wave is usually considered in terms of the magnitude of A(t) = sine (ωt). However, these are non-linear and not easy to generate except by piecewise construction. On the other hand, the angle information is linear in nature. That is, the phase angle rotates by a fixed angle per unit time. The angular rate depends on the frequency of the signal, the traditional rate is ω=2πf.

Knowing that the phase of a sine wave is linear, and given a reference interval (clock period), the phase rotation for that period can be determined by Δphase = ωδt

Solving for ω = ΔPhase/δt = 2 πf

Find f and substitute the reference clock frequency for the reference period (1/fMCLK = δt), f = ΔPhase × fMCLK/2 π

The AD9835 builds the output based on this simple equation. A simple DDS chip can implement this equation with three main subcircuits.

Circuit Description

The AD9835 offers RF communication system designers an exciting level of integration. The AD9835 integrates a numerically controlled oscillator (NCO), a COS look-up table, frequency and phase modulators, and a digital-to-analog converter on a single integrated circuit.

The internal circuit of the AD9835 consists of three main parts. These are numerically controlled oscillators (NCOs) and phase modulators; COS look-up tables; digital-to-analog converters.

The AD9835 is a fully integrated direct digital synthesis (DDS) chip. The chip requires a reference clock, a low-precision resistor, and eight decoupling capacitors to provide digitally processed sine waves up to 25 MHz. In addition to generating this RF signal, the chip is fully capable of implementing a wide range of simple and complex modulation schemes. These modulation schemes are implemented entirely in the digital domain, allowing sophisticated modulation algorithms to be implemented precisely and simply using DSP techniques.

Numerically Controlled Oscillators and Phase Modulators

This includes two frequency select registers, a phase accumulator and four phase offset registers. The main component of the nco is a 32-bit phase accumulator, which combines the phase components of the output signal. The phase range of a continuous time signal is 0π to 2π. Outside this range of numbers, sinusoidal functions repeat themselves in a periodic fashion.

Digital implementation is no exception. The accumulator simply scales the range of phase signs into a multi-digit word. The phase accumulator in the AD9835 is implemented with 32 bits. Therefore, in the AD9835, 2π=2. Likewise, scale the Δphase term to a range of numbers 0 < ΔPhase < 232 − 1. Substitute these into f = ΔPhase × fMCLK/232

where: 0 < ΔPhase < 232, the input to the phase accumulator (i.e. the phase step) can be selected from the freq0 register or the freq1 register, which is controlled by the fselect pin or the fselect bit. The nco inherently produces a continuous phase signal, thus avoiding any output discontinuities when switching between frequencies.

After nco, a phase offset can be added to perform phase modulation using a 12-bit phase register. The contents of this register are added to the most significant bits of nco. AD9835 has four phase registers, the resolution of these registers is 2π/4096.

cos lookup table (lut) For the output to be useful, the signal must be converted from phase information to a sine value. Since the phase information maps directly to the amplitude, the rom lut converts the phase information to the amplitude. For this purpose, the cos-rom lut is addressed using digital phase information. Although nco contains a 32-bit phase accumulator, the output of nco is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this requires a lookup table with 2 entries.

It is only necessary to have sufficient phase resolution in the LUT so that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the lookup table to have 2 more bits of phase resolution than a 10-bit DAC.

digital to analog converter

The AD9835 includes a high impedance current source 10-bit DAC capable of driving a wide range of loads at different speeds. By using a single external resistor (R), the full-scale output current can be adjusted for optimum power and external load requirements. gather

The DAC is configured for single-ended operation. The load resistance can be any value desired, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Since the full-scale current is controlled by R, adjustments to R can balance changes to the load resistance. However, if the dac full-scale output current is significantly less than 4ma, the dac's linearity may be degraded. collection collection

Function description

serial interface

The AD9835 has a serial interface that loads 16 bits per write cycle. sclk, sdata and fsync are used to load words into the ad9835.

When fsync goes low, the AD9835 is told that a word is being written to the device. The first bit is read into the device on the next falling edge of SCLK, and the remaining bits are read into the device on the next falling edge of SCLK. fsync frames 16 bits; so when 16 sclk falling edges occur, fsync should go high again. SCLK can be Table 5. Writes to the AD9835 data register serially or alternatively, SCLK can idle high or low between writes. When writing to the frequency/phase register, the first four bits identify whether to write to the frequency or phase register, the last four bits contain the address of the destination register, and the 8 lsbs contain the data.

Direct Data Transfer and Delayed Data Transfer

In the AD9835, a 16-bit transfer is used when loading the target frequency/phase register. There are two modes for loading registers: direct data transfer and delayed data transfer. With delayed data transfer, 8-bit words are loaded into delay registers (8 lsbs or 8 msbs). However, this data is not loaded into the 16-bit data register; therefore, the destination register is not updated. With direct data transfer, 8-bit words are loaded into the appropriate delay registers (8 lsbs or 8 msbs).

Immediately after the delay register is loaded, the full delay register contents are loaded into the 16-bit data register and the destination register is loaded on the next mclk rising edge. When the destination register is addressed, a delayed transfer is required first, followed by a direct transfer. When all 16 bits of the delay register contain the relevant data, the destination register can be updated using an 8-bit load instead of a 16-bit load, i.e. a direct data transfer can be used.

For example, after a new 16-bit word is loaded into a destination register, the delay register will also contain this word. If the next write instruction is to the same destination register, the user can use direct data transfer immediately.

When writing to the phase register, the 4 msbs of the 16-bit word loaded into the data register should be zero (the phase register is 12 bits wide).

To change the entire contents of the frequency register, four writes are required. However, the 16 msbs of the frequency word are contained in separate registers of the 16 lsbs. Therefore, the 16 msbs of the frequency word can be changed independently of the 16 lsbs.

Use the fselect, psel0, and psel1 pins to select the phase and frequency registers to use, or you can use the corresponding bits. bit selsrc determines whether to use bits or pins. When selsrc=0, pins are used; when selsrc=1, bits are used. When CLR is set high, selsrc is set to 0, so the pin is the default source. The data transfer from the serial (delay) register to the 16-bit data register and the fselect and psel registers occurs after the 16th falling sclk edge.

1X = don't care.

A data transfer from the 16-bit data register to the destination register or from the fselect/psel register to the corresponding multiplexer occurs on the next rising edge of mclk. Since sclk and mclk are asynchronous, a rising edge of mclk may occur when a data bit is in a transition state. If the register to be written to is generating dac output, this may result in short-lived false dac output. To avoid this spurious output, the AD9835 includes synchronization circuitry.

When the sync bit is set to 1, the synchronizer is enabled, data is transferred from the serial register (delay register) to the 16-bit data register, and the fselect/psel register occurs after a two-stage pipeline delay triggered on the falling edge of mclk. Pipeline latency ensures that the data is valid when the transfer occurs. Similarly, when sync=1, use the fselect/pselx pins to select the frequency/phase registers to synchronize with the rising edge of mclk. When sync=0, the synchronizer will be bypassed.

When sync=1, the pin-select frequency/phase registers are used to synchronize internally with mclk to ensure that these inputs are valid on the rising edge of mclk. If times t and t are met, the input will be in a stable state at the rising edge of mclk. However, if time and time are violated, an internal synchronization circuit will delay the instant the pin is sampled, ensuring that the input is valid at the instant of sampling.

waiting time

Associated with each operation is a delay. When the input fselect/psel changes value, there is a pipeline delay before control is transferred to the selected register; there is a pipeline delay before the analog output is controlled by the selected register. When time t and t are satisfied, when sync=0, psel0, psel1 and fselect have a delay of 6 mclk cycles.

When sync=1, the delay increases to 8 mclk cycles. When times t and t are not met, the delay can be increased by one mclk cycle. Similarly, every write operation has a delay. If the selected frequency/phase register is loaded with a new word, there is a delay of 6 to 7 mclk cycles before the analog output changes (there is an uncertainty of one mclk cycle on the rising edge of mclk that loads data into the destination register ). When sync=1, the delay is 8 or 9 mclk cycles.

flow chart

The flowchart in Figure 22 shows the operating procedure for the AD9835. When the AD9835 is powered up, this section should reset, which resets the phase accumulator to zero so that the analog output is at midscale. To avoid spurious DAC outputs when initializing the AD9835, the reset bit should be set to 1 until the part is ready to begin producing outputs. Set clr high to sync and selsrc to 0 to use the fselect/pselx pins to select the frequency/phase registers and bypass the sync circuitry. A write to the sync/selsrc register is required to enable the sync circuit or to change control to the fselect/psel bits.

A reset does not reset the phase and frequency registers. These registers will contain invalid data, so the user should set them to known values. Then set the reset bit to 0 to start generating output. After reset is set to 0, a signal will appear at the DAC output for 6 mclk cycles.

The analog output is f/2 × freg, where freg is the value loaded into the selected frequency register. The signal is phase shifted by the amount specified in the selected phase register (2π/4096 × Phasex Reg, where Phasex Reg is the value contained in the selected phase register). Control of the MCLK32 frequency/phase registers can be swapped in place from the pins.

application information

The AD9835 includes features that make it suitable for modulation applications. This section can be used to do simple modulations like fsk. More complex modulation schemes, such as gmsk and qpsk, can also be implemented using the ad9835. In the fsk application, the two frequency registers of the AD9835 are loaded with different values; one frequency represents the space frequency and the other represents the mark frequency. The digital data stream is fed to the fselect pin, which will cause the AD9835 to modulate the carrier frequency between two values.

The AD9835 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, changing the phase by an amount related to the bit stream input to the modulator. The presence of four shift registers simplifies the required interaction between the DSP and the AD9835.

The AD9835 is also suitable for signal generator applications. Due to its low current consumption, this part is suitable for local oscillator applications.

Grounding and Arrangement

The printed circuit board housing the AD9835 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of easily separated ground planes. The minimum etch technique is usually best for the ground plane because it provides the best shielding. Digital and analog ground can only be connected in one place. If the AD9835 is the only device that requires an AgNd to DGNd connection, the ground plane should be connected at the AgNd and DGNd pins of the AD9835. If the AD9835 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at only one point, a star ground point should be established as close to the AD9835 as possible.

Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should allow operation under the AD9835 to avoid noise coupling. The power lines to the AD9835 should use the largest possible track to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should use digital ground shields to avoid radiating noise to other parts of the board. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This will reduce feedthrough effects through the board. Microstrip technology is by far the best, but not always possible on double-sided panels. In this technique, the component side of the board is dedicated to ground, while the signals are placed on the other side.

Good decoupling is important. The analog and digital power supplies for the AD9835 are independent and fixed separately to minimize coupling between the analog and digital portions of the device. All analog and digital supplies should be disconnected from agnd and dgnd, respectively, with 0.1 mf ceramic capacitors in parallel with 10 mf tantalum capacitors. To get the best results from decoupling capacitors, they should be placed as close to the device as possible, ideally right against the device. In systems that use a common supply to drive the AD9835's AVDD and DVD, it is recommended to use the system's AVDD supply. This supply should have the recommended analog supply decoupling between the AD9835 and the AVDD pin of AGND and the recommended digital supply decoupling capacitor between the DVD pin and DGND.

Interface between AD9835 and Microprocessor

The AD9835 has a standard serial interface that allows the part to interface directly with multiple microprocessors. The device uses an external serial clock to write data/control information to the device. The frequency of the serial clock can be up to 20 MHz. The serial clock can be continuous or idle high or low between writes. When data/control information is written to the AD9835, fsync is taken low and held low, while 16-bit data is written to the AD9835. The 16-bit information of the fsync signal frame is loaded into the ad9835.

AD9835-TO-ADSP-21XX interface

Figure 26 shows the serial interface between the AD9835 and the ADSP-21xx. The ADSP-21XX should be set to operate in Motion Transmission Alternate Frame Mode (TFSW=1). The ADSP-21XX is programmed through the motion control register and should be configured as follows: internal clock operation (ISCLK=1), active low frame (INVTFs=1), 16-bit word length (SLEN=15), internal frame sync signal (ITFs=1) , Generate frame sync (TFSR=1) for each write operation. After enabling motion, a transfer is initiated by writing a word to the TX register. Data is clocked to the AD9835 on each rising edge of the serial clock and to the AD9835 on the falling edge of SCLK.

AD9835-to-68HC11/68L11 interface

Figure 27 shows the serial interface between the AD9835 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting bit mstr in scr to 1, which provides the serial clock on sck, while the mosi output drives the serial data line sdata. Since the microcontroller does not have a dedicated frame sync pin, the fsync signal comes from the port line (pc7). The setup conditions for correct operation of the interface are as follows: SCK is idle high (cpol=0) between write operations, and data is valid on the falling edge of SCK (cpha=1). When data is being transferred to the AD9835, the fsync line is taken low (pc7). Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle. First transmit data msb. To load data into the AD9835, pc7 is held low after the first 8 bits have been transferred and a second serial write is performed to the AD9835. Only after the second 8 bits have been transferred should fsync be brought up again.

AD9835-to-80C51/80L51 interface

Figure 28 shows the serial interface between the AD9835 and the 80C51/80L51 microcontroller. The microcontroller operates in Mode 0 so that the TXD of the 80C51/80L51 drives the SCLK of the AD9835 and the RXD drives the serial data line SData. The fsync signal again comes from a bit programmable pin on the port (P3.3 is used in the picture). When data is to be transmitted to aad9835, p3.3 is taken low. The 80c51/80l51 transmits data in 8-bit bytes, so there are only 8 falling sclk edges per cycle.

To load the remaining 8 bits into the AD9835, p3.3 is held low after the first 8 bits have been sent, and a second write operation is initiated to send the second byte of data. After the second write operation is completed, P3.3 is taken high. SCLK should idle high between write operations. The 80c51/80l51 outputs serial data in a format with lsb first. AD9835 accepts msb first (4 msb is control information, next 4 bits is address, and 8 lsb contains data when writing to destination register). So the 80c51/80l51's transmit routines have to take this into account and rearrange the bits so that the msb is output first.

AD9835-to-DSP56002 interface

Figure 29 shows the interface between the AD9835 and the DSP56002. The DSP56002 is configured for normal mode asynchronous operation with gated internal clocks (syn=0, gck=1, sckd=1). The frame synchronization pin is generated internally (sc2=1), the transmission width is 16 bits (wl1=1, wl0=0), and the frame synchronization signal will be framed in 16 bits (fsl=0).

The frame sync signal is available on pin SC2 but needs to be inverted before being applied to the AD9835. The interface of DSP56000/DSP56001 is similar to that of DSP56002.

Evaluation Committee

System Demonstration Platform

The System Demonstration Platform (SDP) is a hardware and software evaluation tool that can be used with product evaluation boards. The SDP board is based on the Blackfin® BF527 processor and connects to the PC via a USB 2.0 high-speed port. Note that the SDP board is sold separately from the AD9835 evaluation board.

AD9835 to motion interface

The Analog Devices SDP board has a motion serial port for controlling the serial input of the AD9835. The connections are shown in Figure 30.

The AD9835 evaluation board allows designers to evaluate the high performance AD9835 DDS modulator with minimal effort. The graphical user interface of the AD9835 evaluation board is shown in Figure 31.

The DDS evaluation kit includes a populated, tested AD9835 PCB. The evaluation board provides software that allows the user to easily program the AD9835. The schematics and layout of the AD9835 evaluation board are shown in Figure 32 through Figure 36.

The AD9835 can operate from a master clock up to 50 MHz. A 50 MHz general purpose oscillator is included on the evaluation board. However, the oscillator can be removed and an external cmos clock can be connected to this part if desired.

There are two options for general oscillators: AEL 301 series crystal oscillator (AEL Crystal Co., Ltd.); SG-310SCN oscillator (Epson Toyota).

power supply

Power to the AD9835 evaluation board can be supplied via the USB connector or externally via pin connections. Power cords should be twisted to reduce ground loops.