Features: Initiate operation to +600 V for floating channels Typical 350mA /650mA source/sink Current drive capability extension for all channels Allows negative voltage vs swing to -9.8 V

Signal propagation at VDD=VBS= 15V Output asynchronous to input signal Overcurrent shutdown shuts down all six drivers Matched propagation delay on all channels compatible with 3.3 V and 5.0 V input logic Mode prevention logic Built-in soft-off function Common mode dv/dt noise cancellation circuit Built-in uvlo function for all channels

Applications: Three-phase motor inverter drives Air conditioners, washing machines, refrigerators, dishwashers Industrial inverters - general purpose three-phase inverters for sewing machines, power tools

Description: FAN73892 is an integral three-phase half-bridge gate driver IC, designed for high voltage, high speed driving mosfet and igbt, operating voltage up to +600v. Fairchild's high voltage process and common mode noise cancellation technology provides high side drivers in high dv/dt noise environments. Advanced level shifting circuitry allows high-side gates to operate up to VS=-9.8V (typ) when VBS=15V. Protection features include undervoltage lockout and inverter overcurrent trip with automatic fault clearing. To terminate all overcurrent protection six outputs can be derived from an external current sense resistor. An open drain fault signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. The UVLO circuit prevents faults when vdd and vbs are below the threshold voltage. The output drivers typically source and sink 350 mA and 650 mA respectively; suitable for three-phase half-bridge applications in motor drive systems.

Application information: 1. Dead time, time is automatically inserted into dead time The time of the two external input signals (in and signal) is shorter than the internal fixed dead time (DT1 and DT2). Otherwise, the external dead time is greater than the internal dead time is not modified. Gate Driver and Internal Dead Time Waveform Definition

2. Protection functions 2.1 Fault output () and undervoltage lockout The high and low voltage side drivers include undervoltage drive lockout (uvlo) protection circuits for monitoring the voltages independently supplied to VDD and VBS. Probably designed to prevent falling below specified threshold voltages when VDD and VBs fail. Ultraviolet radiation hysteresis prevents jitter transitions during power supply. In addition, the fault signal (supply voltage) goes into a low state for reliable operation when the power supply (VDD) is below the low voltage to lock the high threshold voltage for the circuit (during T1~T2). uvlo circuit is not otherwise active

2.2 Penetration protection Penetration protection circuit prevents high side and low side switching at the same time 2.3 Enable input When the en pin is in high state, the gate driver works normally. When a condition occurs to turn off the gate driver, the en pin should be low. The enable circuit has an input filter; the minimum input duration is specified by tfltin (typically 250 ns).

2.4 Fault Clearance and Overcurrent Protection An integrated fault output ( ) and an adjustable fault clear timer (TFLTCR) are provided. There are two lead gate drivers through the pins. The first is a brown-out condition on the low-side gate driver supply voltage (VDD) and the second is a fault identified by the current sense pin (CS). If a fault occurs, the pin is internally pulled to COM, the fault clear timer is activated, and all gate driver outputs (HO1, 2, 3 and LO1, 2, 3) are off. The fault output remains low until the fault condition has been removed, and the fault clears the timer. maturity. Once the fault clear timer expires, the voltage returns to the pull-up voltage on the pin. The fault clear time (TFLTCR) is determined internally. current source (IRcin = 5µA) and RCin pin as shown: The rdsrcin of the mosfet is a characteristic of the discharge curve of the external capacitor Kersin. The time constant is defined externally. Capacitor crcin and rdsrcin of mosfet. The output of the current sense comparator (CS U comp) is passed through a noise filter to suppress shutdown caused by overcurrent VCS parasitic voltage spikes. This is equivalent to the voltage level on the comparator VCSTH +-VCSHYS=500mV-60mV= 440mV , where vcshys=60mV is the current hysteresis comparator (cs_comp),

Waveform definition of rcin, and low-speed driver; gate driver supply voltage (VDD) or current sense pin (CS) to identify faults under low-side undervoltage conditions using a soft-shutdown method. If a fault occurs, the pins are internally pulled to COM and all output gate drivers (HO1, 2, 3 and LO1, 2, 3) are turned off. Low-Side Output Linear Down Soft-Off Current Source Through Internal Receiver (ISOFT=40mA)

3. Noise filter 3.1 Input noise filter shows the input noise filtering method The input signal (tinput) and output signal (toutput) help suppress noise spikes and short pulses. This input filter applies to hinx, linx and en inputs. The previous pair of waveforms (Example a) shows that the input signal duration (tinput) is longer than the input filter time (TFLTIN); it is roughly the same duration between inputs. Signal time (Tin) and output signal time (Tout). The next pair of waveforms (Example B) shows that the input signal time (TIN) is slightly longer than the input filter time (TFLTIN); it is about the same duration. The time between the input signal time (Tin) and the output signal (tout). 3.2. Burst input noise suppression method The input filter circuit provides protection on the burst input signal (, and en) by applying noise signal to the input signal line. If the input signal duration is less than the input filter time (tfltin), the output does not change state. Examples A and B show a short pulse noise spike output waveform duration less than the input screening time; the output does not change state. The characteristics of the input filter also receive narrow switching pulses. The pulse duration PWIN of the intermediate frequency input signal is less than the input filter time, tfltin; the output pulse pwout is zero. The input signal was rejected by the input filter. Once the input signal pulse duration, PWIN, exceeds the input filter time, TFLTIN, the output pulse duration pwout matches the input pulse duration, pwin. The FAN738 92 input filter time, TFLTIN, is about 250ns for the high and low side outputs.