Features: 3MHz fixed frequency operation for optimal load transient 3A output current capability 2.7V to 5.5V input voltage range Adjustable output voltage: 0.8 to vin0.9 light load high efficiency pfm mode (force pwm mode pin available) Minimum pfm Frequency avoids audible noise Typical quiescent current of 270 µA in pfm mode External frequency synchronization Low ripple light load pfm mode PWM control Power good output Internal soft start input 12 lead 3x3.5mm MLP

Application: Set-top box hard disk drive communication card digital signal processor power supply

Description: 5354 -ic/" title="FAN5354 Product Parameters, Documentation and Sourcing Information" target="_blank">FAN5354 is a step-down switching voltage regulator providing from 2.7V to 5.5V. Using a proprietary architecture, synchronous rectification, The FAN5354 is capable of delivering 3A at over 85% efficiency while maintaining load currents as low as 2mA. The regulator operates at 3MHz, reduces the output inductance of external components to 470nh, and the output is a 10µf capacitor. Additional output capacitors can be added at Impact stability up to 1.2µh and inductance can be combined with additional output capacitance. At moderate and light loads, pulse frequency modulation (pfm) is used to operate the device in power save mode. Typical quiescent current is 270µA. Even this low quiescent current current, the part exhibits good transient response during large load swings. At higher loads, the system automatically switches to fixed frequency control, operating at 3MHz. In shutdown mode, the supply current drops below 1µA , reduces power consumption. pfm mode can be disabled if constant frequency is required. Avoids audible noise, regulator limits its minimum PFM frequency. Fan 5354 has 12 lead 3x3.5mm MLP package.

Operating Instructions: The FAN5354 is a step-down switching voltage regulator supplied from 2.7V to 5.5V. Using a proprietary architecture for synchronous rectification, the FAN5354 is capable of delivering 3A with over 80% efficiency. The regulator operates at full load and is rated at 3MHz, which reduces the external components of the output to a value of 470nh inductor and 20µF of the output capacitor. High efficiency is maintained at light loads in single-pulse pfm mode. The control scheme FAN5354 uses a proprietary nonlinear fixed frequency pwm modulator to provide fast load transient response while maintaining a constant switching frequency over a wide range of operating conditions. The regulator performance is independent of the output capacitor ESR, allowing the use of ceramic output capacitors. Although this type of operation typically causes the switching frequency to vary with input voltage and load current, an internal frequency loop keeps the switching frequency constant over a wide range of input voltage and load current. For very light loads, the FAN5354 discontinuous operating current (DCM) single-pulse power factor modulation mode produces low output ripple compared to other pfm architectures. Transitions between pwm and pfm are seamless, with a glitch less than 18mV during VOUT transitions in DCM and CCM modes. The regulator limits the minimum pfm frequency to typically 26 kHz. Holding the mode pin high disables pfm mode. The IC is frequency synchronized with the mode pin. when? Synchronized to the mode pin, pfm mode is disabled. Note: Table 1 recommends 0805 capacitors, but 0603 capacitors may work if space is good. Due to voltage effects, the in-circuit capacitance of 0603 capacitors is lower than that of 0805 packets, which reduces transient response and output ripple. Increasing cout has no effect on loop stability and can therefore increase output voltage ripple or improve transient response. The output voltage ripple ∏vout is: Input Capacitor The 10µf ceramic input capacitor should be as close as possible between VIN (vin) and VIN (pgnd) to allow parasitic inductance. If using a long wire to the IC, additional "bulk" capacitors (electrolytic or tantalum) should be placed between CIN and the power line to reduce the inductance of the power leads and CIN. The effective cin capacitance value decreases as vin decreases and increases due to the DC bias effect. This has little effect on regulator performance. Layout Suggestions The layout suggestions below highlight the different TopCopper planes by using different colors. It includes a demonstration of how to add a cout capacitor to reduce ripple as well as short trips. The inductor in this example is a TDK VLC5020T-R47N type. VCC and VIN should be connected together by a thin wire some distance away from the IC, or through a resistor (R3 below), connecting the switching spike on pvin to the IC bias supply on VCC. If the PCB area is high, the connection between pvin and vcc can be on another PCB layer through vias. The via impedance provides some filtering of the high frequency peaks produced on the pvin. pgnd and agnd are connected through the IC's thermal pad. Extending the pgnd and agnd planes can improve ic cooling. The IC analog ground (agnd) is connected to p11 and 12 between pins. Large AC ground currents should return to pins 3 and 4 (pgnd) via copper pins 6 and 7 below p1 or through the direct trace of pins 3 and 4 (as shown as COUT1-COUT3). en and pgood are connected to the system control logic through vias. CHI1 is an optional device used to provide lower equipment. Impedance path for high frequency switching edges/spikes, which helps reduce software node and VIN ringing. CIN should be as close as possible to pgnd and vin as shown below. The PGND connection to the return inner plane should be done as a series of vias distributed in COUT to complete the return trace between pins 6 and 7 and the CIN return plane.