Features
CCD Signal Processing: Correlated Double Sampling (CDS) Programmable Black Level Clamp Programmable Gain Amplifier (PGA): -6dB to +42dB Gain Range 12-bit Digital Data Output: Up to 20MHz Conversion Rate No Missing Codes 79dB Signal-to-Noise Ratio Portable Operation : Low Voltage: 2.7V to 3.6V Low Power: 83MW at 3.0V (Typical) Standby Mode: 6MW
Description of ccd signal processor for VSP2262 digital camera
The VSP2262 is a complete mixed-signal processing IC for digital cameras that provides signal conditioning and analog-to-digital (A/D) conversion for the output of a CCD array. The main CCD channel provides correlated double sampling (CD) to extract video information from pixels, digital controls for gain range under different lighting conditions, and black level clamping for accurate black level reference. Also performs input signal clamping and offset correction of the input cds. Stable gain control is linear in decibels. Also, after a gain change, the black level recovers quickly. The VSP2262Y is packaged in LQFP-48 and powered by a +3V/+3.3V power supply.

Electrostatic Discharge Sensitivity This integrated circuit may be damaged by electrostatic discharge. Burr Brown recommends taking proper precautions when handling all integrated circuits. Failure to follow proper operation and installation procedures may result in damage.
ESD damage can range from minor performance degradation to complete device failure. Precision integrated circuits can be more susceptible to damage because very small parameter changes can cause the device to not meet its published specifications.

CDS Timing Specifications

Serial Interface Timing Specification

300-4ce7-4b40-8eb9-4c1223a6f3d4.png" />

Introduction to Theory of Operation
The VSP2262 is a complete mixed-signal IC that includes all key features related to the processing of CCD imager output signals in video cameras, digital still cameras, security cameras, or similar applications (see simplified block diagram on page 1 for details). VSP2262 includes correlated double sampler (CDS), programmable gain amplifier (PGA), analog-to-digital converter (ADC), input clamp circuit, optical black level (OB) level clamp loop, serial interface, timing control , reference voltage generator and general-purpose 8 digital-to-analog converter (DAC). We recommend using an off-chip transmitter follower buffer between the ccd output and the vsp2262 ccdin input. The PGA gain control, clock polarity setting, and operating mode are selectable through the serial interface. When the reset pin goes low asynchronously to the clock, all parameters are reset to their default values.
Correlated Double Sampler (CDS)
The output signal of the CCD imager is sampled twice within a pixel period: once in the reference interval and once in the data interval. Subtract these two samples from each other to extract pixel video information, and remove any common or correlated noise that separates the two. Therefore, CDS is very important in reducing reset noise and low frequency noise on the CCD output signal. Figure 1 shows a simplified block diagram of the CDS and input clamp.

Simplified block diagram of CDS and input clamp.
The cds are driven through an off-chip coupling capacitor (cin). AC coupling is highly recommended, since the DC level of the CCD output signal is usually a few volts, so the CD will not work properly. Depending on the application environment, a 0.1μF capacitor is recommended for CIN. Also, we recommend an off-chip emitter follower buffer that can drive over 10pf because of the 10pf capacitance and a small amount of pf stray capacitance visible at the input. The analog input signal range for the ccdin pin is 1vp-p, and the appropriate common mode voltage for the cds is about 0.5v to 1.5v.
The reference level is sampled during the active period of the small hydropower, and the voltage level is maintained on the sampling capacitor C1 on the trailing edge of the small hydropower. The data level is sampled during SHD-active, and the voltage level on sampling capacitor C2 is held on the trailing edge of SHD. The switched capacitor amplifier then performs the subtraction of these two levels.
The user can select the active polarity (active high or active low) of the SHP/SHD via the serial interface (see the "Serial Interface" section for details). The default value for SHP/SHD is Active Low. However, immediately after powering on, this value is unknown. Therefore, the appropriate value must be set using the serial interface, or reset to default by hitting the reset pin. The descriptions and timing diagrams in this datasheet are based on active low (default) polarity.
The input clamp or pseudo pixel clamp buffer CCD output capacitor is coupled to the vsp2262. The purpose of the input clamp is to restore the DC component of the input signal lost due to AC coupling and to establish the desired DC bias point for cds. Figure 1 shows a simplified block diagram of the input clamp. During the dummy pixel interval, the input level is clamped to the internal reference voltage cm (1.5v). More specifically, the virtual clamping function becomes active when both CLPDM and SHP are active. If there are no dummy pixels and/or clpdm pulses in the system, clpob pulses can be used instead of clpdm whenever clamping occurs during black pixels. In this case, during the optical black pixel interval, the CPLDM pin (at the same timing as CPLOB) and SHP become active, and then the virtual clamp function becomes active.
The active polarity (active high or active low) of the CLPDM and SHP can be selected via the serial interface (see the Serial Interface section for details). The default value for CLPDM and SHP is "active low". However, immediately after powering on, this value is unknown. Therefore, the appropriate value must be set using the serial interface, or reset to default by hitting the reset pin. The descriptions and timing diagrams in this datasheet are based on active low (default) polarity.
High-performance analog-to-digital converter ADCs are fully differential and pipelined. This ADC is ideal for low voltage operation, low power requirements and high speed applications. It guarantees 12-bit resolution with no missing codes. The vsp2262 includes a reference generator for the ADC.

(Negative Reference, Pin 39) and cm (Common Mode Voltage, Pin 37) should be bypassed to ground with 0.1µf ceramic capacitors and should not be used elsewhere in the system as they will affect the stability of these reference levels , resulting in a decrease in ADC performance. Note that these are analog output pins, therefore, no external voltage is applied.
Programmable Gain Amplifier (PGA)
Characteristics of PGA gain. The pga provides a gain range of -6db to +42db, which is linear in db. Gain is controlled by a digital code with 10-bit resolution and can be set via the serial interface (see the "Serial Interface" section for details). The default value of the gain control code is 128 (pga gain=0db). However, immediately after powering on, this value is unknown. Therefore, the appropriate value must be set using the serial interface, or reset to default by hitting the reset pin.
Optical black (ob) level clamp ring In order to extract video information correctly, the ccd signal must be referenced to a good ob level. The vsp2262 has an auto-calibration loop to establish the ob level using the optical black pixels output from the CCD imager. The input signal level of the ob pixel is recognized as the actual "ob level" and the loop should be closed when the clpob is activated.
During the valid pixel interval, the reference level of the ccd output signal is clamped to the ob level by the ob level clamp loop. To determine the loop time constant, an off-chip capacitor is required and should be connected to COB (pin 28). The time constant t is given in the following equation: t=c/(16384imin) where c is the value of the capacitance connected to c ob and imin is the minimum current that controls the digital-to-analog converter (dac) in the ob level clamp loop (0.15 microamps), 0.15 microamps is equivalent to 1LSB of DAC output current. When c is 0.1 μf, the time constant t is 40.7 μs.
In addition, the slew rate sr is given by: sr=imax/c where c is the value of the capacitance connected to c ob, imax is the maximum current (153 microamps) of the control dac in the ob level clamp loop, 153 microamps Equivalent to 1023lsb of dac output current.
In general, ob-level clamping at high speeds results in "clamping noise" (or "white stripe noise"), however, the noise decreases as c increases. On the other hand, an increase in c takes longer to resume from standby mode or immediately after power up. Therefore, we consider 0.1µf to 0.22µf to be a reasonable value for C. However, this depends on the application environment; we recommend careful tuning using trial and error.
The "OB clamp level" (base level) can be programmed via the serial interface (see the "Serial Interface" section for more details). Table 1 shows the relationship between the input code and the ob clamp level.
The active polarity of the CLPOB (active high or active low) is selectable via the serial interface (see the "Serial Interface" section for details). The default value of clpob is "active low". However, immediately after powering on, this value is unknown. Therefore, the appropriate value must be set using the serial interface, or reset to default by hitting the reset pin. The descriptions and timing diagrams in this datasheet are based on active low (default) polarity.
Pre-Blanking and Data Delay
The vsp2262 features input blanking or pre-blanking. When PBLK goes low, all digital outputs will go to zero on the 11th rising edge of ADCCK. In this mode, digital output data is output on the rising edge of adcck with a delay of 11 clock cycles (data delay of 11).

Unlike the pre-blanking mode where the digital output data is output on the rising edge of adcck with a delay of 9 clock cycles (data delay of 9). If the input voltage is 0.3V above the supply rail or 0.3V below the ground rail, the protection diodes will turn on to prevent the input voltage from rising further. Such high swing signals may cause equipment damage to the vsp2262 and should be avoided.
Standby Mode In order to save power, when the vsp2262 is not in use, the vsp2262 can be set to standby mode (or power-down mode) through the serial interface. See the "Serial Interface" section for more information. In this mode, all function blocks are disabled and the digital outputs will be zeroed, causing the current consumption to drop to 1 mA. Since all bypass capacitors will be discharged in this mode, powering up from standby mode takes a considerable amount of time (typically 200 to 300 ms).
voltage reference
All reference voltages and bias currents required by the VSP2262 are generated by its internal bandgap circuitry. There are three main reference voltages used by cds and adc: refp (positive reference, pin 38), refn (negative reference, pin 39) and cm (common mode voltage, pin 37). refp, refn and cm should be heavily decoupled with appropriate capacitors (eg 0.1µf ceramic capacitors). Do not use these voltages elsewhere in the system as they will affect the stability of the reference level and cause degradation in ADC performance. Note that these are analog output pins and no external voltage is applied.
BYPP2 (Pin 29), BYP (Pin 31), and BYPM (Pin 32) are also reference voltages used in analog circuits. BYP should use a 0.1µF ceramic capacitor to ground. Since the capacitance values of bypp2 and bypm affect the step response, we consider 400pf to 9000pf to be a reasonable value. However, since this depends on the application environment, we recommend careful tuning using a trial and error method.
BYPP2, BYP and BYPM should all be heavily decoupled with appropriate capacitors and not used elsewhere in the system. They affect the stability of the reference level and cause performance degradation. Note that these are analog output pins and no external voltage is applied.
Serial Interface The serial interface has a 2-byte shift register and various parallel registers to control all digital programmable features of the vsp2262. Writing to these registers is controlled by four signals (sload, sclk, sdata, and reset). To enable the shift register, sload must be pulled low. sdata is the serial data input and sclk is the shift clock. The data of sdata is brought into the shift register on the rising edge of sclk; the data length should be two bytes. After a 2-byte shift operation, the data in the shift register is transferred to the parallel latch on the rising edge of sload. In addition to the parallel latches, there are several registers dedicated to device-specific functions, which are synchronized to ADCCK. The data in the parallel latches takes five to six clock cycles to write to these registers. Therefore, to complete the data update, 5 to 6 clock cycles need to be latched in parallel by the rising edge of sload.
The serial interface data format is shown in Table 2. test is the test mode flag (only for Texas Instruments), a0 to a2 are the addresses of various registers, and d0 to d11 are the data (or operand) fields.

Schedule
The CDS and ADC are operated by the SHP/SHD and a derived timing clock generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. See VSP2262 "CDS Timing Specification" for the timing relationship between CCD signals, SHP/SHD, ADCK and output data. CPLPOB is used to activate the black level clamp loop during OB pixel intervals, and CPLDM is used to activate the input clamp during dummy pixel intervals. If CLPDM pulses are not available in your system, CLPOB pulses can be used instead of CLPDM whenever clamping occurs during black pixels (see the Input Clamping and Dummy Pixel Clamping section for more details). The clock polarity of SHP/SHD, CLPOB and CLPDM can be set independently through the serial interface (see the "Serial Interface" section for details). The descriptions and timing diagrams in this datasheet are based on active low (default) polarity. To maintain stable and accurate OB clamping levels, we recommend that CPLOB should not be activated during PBLK activation. See the Pre-Blanking and Data Delay section for details. In standby mode, ADCCK, SHP, SHD, CLPOB and CLPDM are internally masked and pulled high.
Power, Ground, and Device Decoupling It is recommended that the VSP2262 contains analog circuitry and very high-precision high-speed ADCs that are susceptible to any extraneous noise from the rails or elsewhere. Therefore, it should be considered an analog component, and all supply pins except DRVDD should be powered by the system's only analog supply. This will ensure the most consistent results, as digital power lines often carry high levels of broadband noise that would otherwise be coupled into the device and degrade achievable performance. Proper grounding, short lead lengths, and use of ground planes are also very important for high-frequency designs. Multilayer PC boards are recommended for optimal performance because they offer distinct advantages such as minimizing ground impedance, separating signal layers through ground planes, and more. It is strongly recommended that the analog and digital ground pins of the VSP2262 be connected together on the IC, and only to the analog ground of the system. The driver stage (B[11:0]) for the digital outputs is provided through a dedicated power supply pin (DRVDD), which should be completely separated from the other supply pins, or at least the ferrite bead.
It is also recommended to minimize capacitive loading on the output data lines (typically less than 15pF). Large capacitive loads require higher charging current surges that can feed back into the analog portion of the vsp2262 and affect performance. If possible, external buffers or latches should be used, providing the added benefit of isolating the VSP2262 from any digital noise activity on the data lines. Additionally, a resistor in series with each data line helps reduce inrush current. Values in the range of 100 to 200 μm will limit the instantaneous current of the output stage to provide charging of parasitic capacitances when the output level goes from low to high or high to low. Due to the high speed of operation, the converter also generates high frequency current transients and noise, which are fed back to the power and reference lines. This requires adequate bypassing of the supply and reference pins. In most cases, a 0.1µf ceramic chip capacitor is sufficient to separate the reference pins. The power pins should be decoupled to the ground plane with a parallel combination of tantalum (1µF to 22µF) and ceramic (0.1µF) capacitors. The effectiveness of decoupling depends heavily on the proximity to a single pin. DRVDD should be close to DRVGND. Special care must be taken to bypass COB, BYPP2, and BYPM, as these capacitance values determine the important analog performance of the device.

(1) The marketing status value is defined as follows: Active: Product equipment recommended for the new design. TimeBuy: TI has announced that the device will be discontinued, with a lifetime purchase period in effect. NRND: Not recommended for new designs. Devices are in production to support existing customers, but TI does not recommend using this part in new designs. Preview: The device has been released, but not yet in production. The sample may or may not have it. Obsolete: TI has discontinued production of this device.
(2) Eco-Planning - Eco-friendly classification of plans: Pb Free (RoHS) or Green (RoHS and NOS/BR) - Please check /Office Content for the latest availability information and additional product content details. Pending: No lead-free/green transition plan defined. Pb Free (ROHS): TI's term "lead-free" or "lead-free" refers to semiconductor products that are compliant with current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in a homogeneous material . When designed for high temperature soldering, Ti-Pb-free products are suitable for specific lead-free processes. Green (ROHS and NO): Titanium is defined as "green" and means Pb Free (RoHS Compliant), Bromine (Bromine) and Antimony (SB) flame retardants (bromine or antimony not more than 0.1% in homogeneous material weight).
(3) MSL, peak temperature. -- Moisture sensitivity rating according to jedec industry standard classification and peak solder temperature.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and beliefs as of the date it is provided. TI makes no representations or warranties as to the accuracy of information provided by third parties based on its knowledge and beliefs about such information. Efforts are being made to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information, but may not perform destructive testing or chemical analysis of incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary and therefore cas numbers and other limited information may not be released.