Benefits: Advantages Ultra compact size - 6mm x 6mm MLP, 44% space saving compared to traditional 8mm x 8mm drmos package. Fully optimize system efficiency. Clear voltage waveform reduces ringing. high frequency operation. Features The ultra-compact thermally enhanced 6mm x 6mm MLP package is 84% smaller than traditional discrete solutions. Synchronous driver plus FET multi-chip module. High current handling 35 A. Over 93% peak efficiency. Logic level pulse width modulation input. Fairchild's PowerTrench 174 ;5 technology MOSFET for cleaning voltage waveforms and reducing ringing. Optimized for switching frequencies up to 1 MHz. Skip mode SMOD [low side door closed] input. The application of fairchild-syncfettm [integrated Schottky diode] technology in low-side mosfet. Integrated bootstrap Schottky diode. Adaptive gate drive timing for penetration protection. Driver output disable function [release pin]. Undervoltage Lockout (UVLO). Fairchild green packaging and RoHS compliant. Low profile SMD package. General Description The XSTM DRMOS family is Fairchild's next generation fully optimized, ultra-compact, integrated MOSFET plus drive power stage solution for high current, high frequency synchronous step-down DC-DC applications. The fdmf6704a xstm drmos integrates a driver chip, two power mosfets and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6mm x 6mm MLP package. Using an integrated approach, the entire switching power stage is optimized in terms of driver and MOSFET dynamic performance, system inductance and RDS(ON). This greatly reduces package parasitics and layout challenges associated with traditional discrete solutions. The xstm drmos utilizes fairchild's high performance powertrenchtm 5 mosfet technology, which greatly reduces ringing in synchronous buck converter applications. The powertrenchtm 5 can eliminate the need for snubber circuits in buck converter applications. The driver IC incorporates advanced features such as SMOD to improve light-load efficiency. 5 V gate drivers and improved PCB interface optimize maximum low-side FET exposed pad area to ensure higher performance. This product is compatible with the new Intel 6mm x 6mm drmos specification. Application of compact blade server V-core, non-V-core and VTT DC-DC converters. Desktop computer V-Core, non-V-Core and VTT DC-DC converters. Workstation V-core, non-V-core and VTT type DC-DC converters. Gaming motherboard V-core, non-V-core and VTT DC-DC converters. game console. High current DC-DC point-of-load (POL) converters. Microprocessor voltage regulators for networking and telecommunications. Small voltage regulator module.

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Operating Circuit Description The FDMF6704A is a driver plus FET module optimized for synchronous buck converter topology. Only a pwm input signal is required to properly drive the high-side and low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz. The purpose of the low side driver (GL) of the low side driver is to drive a ground referenced low RDS(on) N-channel MOSFET. The bias of gl is intrinsically linked between vdrv and cgnd. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. GL remains low when the drive is disabled (disb=0v). The high-side driver (GH) of the high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is generated by a bootstrap power supply circuit consisting of an internal diode and an external bootstrap capacitor (cboot). During boot, vswh remains at pgnd, allowing cboot to charge vdrv through an internal diode. When the PWM input goes high, GH will start charging the gate (Q1) of the high-side mosfet. During this transition, charge is removed from cboot and transferred to the gate of Q1. When Q1 is on, VSWH rises to VIN, forcing the pilot pin into VIN +VC (boot), which provides sufficient VGS boost for Q1. To complete the switching cycle, Q1 is turned off by pulling gh to vswh. When vswh drops to pgnd, cboot recharges to vdrv. The gh output is in phase with the pwm input. When the driver is disabled, the high side doors remain low. SMOD The SMOD (Skip Mode) function allows increased converter efficiency at light load conditions. During SMOD, the LS FET is disabled and prevents the output cap from discharging. When the SMOD pin is pulled high, the synchronous buck converter will operate in synchronous mode. When the SMOD pin is pulled low, the LS FET is turned off.

The SMOD function has no internal current sensing. The SMOD pin is connected to a PWM controller that can automatically or disable the SMOD when the controller detects a light load condition. Normally, this pin is active low. The driver IC for the adaptive gate drive circuit embodies an advanced design that ensures minimal MOSFET dead time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adaptively adjusts the gate drivers to make sure they don't go at the same time. See Figure 4 for timing waveforms. To prevent overlap during low-to-high switching transitions (Q2 off to Q1 on), the adaptive circuit monitors the voltage at the GL pin. When the PWM signal goes high, Q2 will start to turn off after some propagation delay (tpdll). Once the GL pin discharges below 1 V, the adaptive delay TDHH after Q1 begins to turn on. To prevent overlap during high-to-low transitions (on Q1 to Q2), the adaptive circuit monitors the voltage at the VSWH pin. When the PWM signal goes low, Q1 will start to turn off after some propagation delay (TPDHL). Once the VSWH pin is below 1 V, the adaptive delay TDLH after Q2 starts to turn on. In addition, the VGS for the first quarter was also monitored. When VGS(Q1) is discharged low, a second adaptive delay is initiated, which causes Q2 to be driven after 250 ns, regardless of VSWH state. This function is implemented to ensure that CBOOT is recharged every switching cycle, especially for the case where the power converter is sinking current and the VSWH voltage does not fall below the 1 V adaptive threshold. The secondary delay of 250 ns is longer than TDTLH.

Application Information: Power Supply Capacitor Selection For the power supply input (vcin) of the fdmf6704a, a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1F, X7R or X5R capacitors. Place this capacitor close to the FDMF6704A VCIN and PGND pins. Boot Circuit The boot circuit uses a charge storage capacitor (CBOOT) as shown in Figure 23. Bootstrap capacitance of 100nF, X7R or X5R capacitor is sufficient. To improve switching noise immunity, a series bootstrap resistor is required. VCIN Filter The VDRV pin provides power to the high-side and low-side power FET gate drivers. In most cases, it can be connected directly to VCIN, which provides power to the logic portion of the driver. For extra noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values are 10 ohms and 1F. The printed circuit board layout guidelines diagram shows an example of the correct layout of the FDMF6704A and key components. All high current paths like vin, vswh, vout and gnd copper should be short and wide for better and stable current flow, heat radiation and system performance. The following is a guideline that pcb designers should consider: 1. The input ceramic bypass capacitors must be close to the vin and pgnd pins of the fdmf6704a to help reduce the input current ripple component caused by switching operations. 2.vswh copper track has two uses. In addition to being a high frequency current path from the drmos package to the output inductor, it also acts as a heat sink for the lower fet in the drmos package. The tracks should be short and wide enough to present a low impedance path for high frequency, high current flow between the drmos and the inductor to minimize losses and temperature rise. Note that the vswh node is a high voltage high frequency switching node with a high noise potential. Care should be taken to minimize coupling to adjacent tracks. In addition, since this copper trace also acts as a heat sink for the lower FET, a trade-off must be made to use the maximum area to improve DRMOS cooling while maintaining acceptable noise emissions. 3. The position of the output inductor should be as close as possible to the FDMF6704A to reduce the power loss due to copper traces. Care should be taken so that the inductive dissipation does not heat the drmos. 4. The PowerTrench® 5 mosfet used in the output stage is very effective in minimizing ringing. In most cases, shock absorbers are not required. If a buffer is used, it should be placed near the FDMF6704A. Resistors and capacitors should be sized for power dissipation. 5. Place ceramic bypass capacitors and bootstrap capacitors as close as possible to the VCIN and bootstrap pins of the FDMF6704A to ensure a clean and stable power supply. Trace width and length should also be considered. 6. Include tracking from phase to VSWH to improve noise margin. Keep traces as short as possible.

7. The layout should include the option to insert a small value series start resistor between the start cap and the start pin. Boot ring sizes, including RBOOT and Cboot, should be as small as possible. Start-up resistors are generally not necessary, but are effective in improving noise operating margins in multiphase designs that may have noise issues due to ground bounce and high negative VSWH ringing. The vin and pgnd pins handle high current transients with frequencies above 100MHz. If possible, these package pins should be connected directly to the VIN and board ground plane. The use of thermal traces in series with these pins is discouraged as this increases the inductance of the power path. This additional inductance in series with the pgnd pin will reduce the noise immunity of the system by increasing the negative vswh ringing. 8. The cgnd pad and the pgnd pin should be connected with multi-hole plane ground copper to ensure stable grounding. Poor grounding can create noisy transient offset voltage levels between cgnd and pgnd. This can lead to faulty operation of the gate driver and mosfet. 9. The ringing of the start pin is most effectively controlled by the close placement of the start capacitor. Do not add extra protective sleeves to the PGND capacitors. This can cause excessive current to flow through the boot diode. 10. The SMOD, DISB and PWM pins have no internal pull-up or pull-down resistors. They should not float. These pins should not have any noise filter caps. number 11. Use multiple vias on each copper area to connect the top, inner, and bottom layers to help smooth electrical current and heat conduction. Vias should be relatively large with reasonable inductance. Critical high frequency components such as Rboot, Cboot, RC snubber and bypass cap should be located close to the DRMOS module and on the same side of the PCB as the module. If this is not feasible, it should be connected from the back side via a low inductance via network