feature

Non-volatile memory holds wiper settings; 256-bit; LFCSP-10 (3 mm x 3 mm x 0.8 mm) thin package; compact MSOP-10 (3 mm x 4.9 mm x 1.1 mm) package; I2C® compatible Interface; provides higher interface flexibility; end-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ; resistance tolerance stored in EEPROM (0.1% accuracy); power-on EEPROM refresh time <1ms; software write Protection Command; Address Decode Pin AD0 and Pin AD1 Enable; 4 Packets Per Car; 100 Years Typical Data Retention at 55°C; Wide Operating Temperature -40°C to +125°C; 3 V to 5 V Single Supply .

application

LCD panel VCOM adjustment; LCD panel brightness and contrast control; replacement of mechanical potentiometers in new designs; programmable power supplies; RF amplifier biasing; automotive electronics adjustment; gain control and offset adjustment; fiber-to-the-home systems; electronic level setting .

General Instructions

The AD5259 provides a compact, nonvolatile LFCSP-10. (3 mm x 3 mm) or MSOP-10 (3 mm x 4.9 mm) packs 256 solutions for position adjustment applications. These devices perform the same electronic regulation functions. As a mechanical potentiometer 1 or a variable resistor, but with higher resolution and solid state reliability. The wiper settings can be controlled via an I2C compatible digital interface for reading the wiper registers. and EEPROM contents. Resistance tolerances are also stored in EEPROM, providing an end-to-end tolerance accuracy of 0.1%. A separate VLogic pin provides increased interface flexibility. For users who need multiple components on one bus, address bits ad0 and AD1 allow up to four devices on the same bus.

theory of operation

The AD5259 is a 256-bit digitally controlled variable resistor (VR) device. The EEPROM is preloaded to mid-scale from the factory, so initial power-up is at mid-scale.

Variable Resistor Programming

Rheostat operation

The nominal resistance (R) of the RDAC between Terminal A and Terminal B is 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance of the VR has 256 contacts accessible through the wiper terminals. Decode the 8-bit data in the rdac latch to select one of 256 possible settings.

The general formula for determining the digitally programmed output resistance between wiper W and terminal B is:

Where:

D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register.

The R antibody is the end-to-end resistance.

RW is the wiper resistance resulting from the on-resistance of each internal switch.

Under zero-scale conditions, there is a relatively low finite wiper resistance value. In this state, care should be taken to limit the current between wiper W and terminal B to a maximum pulse current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to a mechanical potentiometer, the RDAC resistance between wiper W and terminal A produces a digitally controlled complementary resistance R. The resistance value setting for R starts from the maximum value of the resistance and decreases as the data value loaded in the latch increases. The general equation for this operation is:

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Therefore, the resistance tolerance is stored in the EEPROM, enabling the user to know that the actual R is within 0.1%.

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily creates a voltage divider proportional to the input voltage from terminal A to terminal B at wiper W to terminal B and wiper W to terminal A. Unlike the polarity of V to GND, which must be positive, the voltage across terminal A to terminal B, wiper W to terminal A, and wiper W to terminal B can be in either polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground will produce an output voltage at the wiper W to B terminals, starting at 0 V until 1 LSB is less than 5 V. The general equation that defines the V output voltage of any effective input voltage applied to terminal A relative to ground at terminal B is:

A more precise calculation includes the effect of wiper resistance v:

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the rheostat mode, the output voltage is mainly determined by the ratio of the internal resistances r and r, not the absolute value.

IC Compatible Interface 2

The master initiates a data transfer by establishing a start condition, a high-to-low transition on the SDA line while SCL is high (see Figure 4). The next byte is the slave address byte, which consists of the slave address (first 7 bits) and an R/W bit. When the r/w bit is high, the master device reads data from the slave device. When the r/w bit is low, the master writes to the slave.

The slave address of the part is determined by two configurable address pins, pin AD0 and pin AD1. The state of these two pins is registered and decoded into the corresponding IC7 bit address at power-up. The slave address corresponding to the transmit address bit responds by pulling the sda line low during the ninth clock pulse (this is called the slave acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers.

writing

In write mode, the last bit (r/w) of the slave address byte is logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the instruction bits. The user must choose whether to write to the RDAC register,

EEPROM registers, or activate software write protection, the last five bits are all zeros. The slave pulls the sda line low again during the ninth clock pulse. The last byte is the data byte msb first. In write-protected mode, no data is stored; instead, a logic high in lsb enables write protection. Likewise, logic low disables write protection. The slave pulls the sda line low again during the ninth clock pulse.

save/restore

In this mode, only the address and instruction bytes are required. The last bit (r/w) of the address byte is the logic low bit. The first three bits of the instruction byte are the instruction bits. The two options are to transfer data from RDAC to EEPROM (storage), or from EEPROM to RDAC (restore). The last five digits are all zeros. Additionally, the user should issue a nop command immediately after reverting the EEMEM setting to RDAC to minimize supply current consumption.

read

Assuming the register of interest is not directly writeable, it is necessary to write a virtual address and instruction byte. The instruction byte will vary depending on whether the desired data is an RDAC register, an EEPROM register, or a tolerance register.

After sending the virtual address and instruction bytes, a repeated start is required. After the repeated start, another address byte is required, but this time the r/w bit is logic high. This address byte is followed by a readback byte containing the information requested in the instruction byte. The read bit occurs on the negative edge of the clock. Tolerance registers can be read individually.

After all data bits have been read or written, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the sda line when scl is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 46). In read mode, the master responds with a no to the ninth clock pulse (ie the sda line is held high). Then, before the tenth clock pulse, the master pulls the SDA line low and then SDA high to establish a stop condition (see Figure 47).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after only addressing and indicating the part once. For example, after the rdac acknowledges its slave address and instruction byte in write mode, the rdac output is updated on each successive byte until a stop condition is received. If a different instruction is required, the write/read mode must start over with a new slave address, instruction and data bytes. Likewise, the repeated read function of rdac is also allowed.

The AD5259 features patented R-tolerance memory in nonvolatile memory. Tolerances are stored in memory during factory production and can be read by the user at any time. Knowledge of the stored tolerance allows the user to calculate R precisely. This feature is useful for accuracy, rheostat mode, and open loop applications where knowledge of absolute resistance is critical.

The stored tolerance is in read-only memory and is expressed as a percentage. Tolerances are stored in two memory location bytes in symbol-sized binary (see Figure 41).

The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal). These two bytes can be accessed independently by two separate commands (see Table 15). Alternatively, the first byte can be read followed by the second byte in one command (see Table 16). In the latter case, the memory pointer will be automatically incremented from the first eeprom position to the second eeprom position (from 11110 to 11111) if consecutive reads.

In the first memory location, specify the msb as the sign (0=+ and 1=-) and the seven lsb as the integer part of the tolerance. In the second memory location, all eight data bits are designated as the fractional part of the tolerance. Note that the fractional part has a limited precision of 0.1%. For example, if the rated R=10 kΩ, and the data read from address 11110 shows 0001 1100 and address 11111 shows 0000 1111, the tolerance can be calculated as:

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

8 LSBs: 0000 1111 = 15 × 2–8 = 0.06

Tolerance = +28.06%

Rounded Tolerance = +28.1% and therefore, RAB_ACTUAL = 12.810 kΩ

esd protection for digital pins and resistor terminals

The AD5259 V, V, and GND supplies define the boundary conditions for proper 3-terminal and digital input operation. Supply signals that appear on Terminal A, Terminal B, and Terminal W in excess of V or GND are clamped by internal forward-biased ESD protection diodes (see Figure 42). Digital input SCL and digital input SDA are clamped with respect to V and GND by ESD protection diodes, as shown in Figure 43.

power-on sequence

Since the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 42), it is very important to energize GND/V/V before applying any voltage to Terminal A, Terminal B, and Terminal W. Important; otherwise, the diode is forward biased, so V and V are unintentionally energized, potentially affecting the user circuit. The ideal power-up sequence is as follows: GND, V, V, digital input, then V, V, V. The relative order of V, V and digital inputs does not matter as long as power is applied after GND/V/V.

Layout and Power Bypass

It is a good practice to use a layout design with compact, minimum lead lengths. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µf to 0.1µf chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µf to 10µf tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency fluctuations (see Figure 44). The digital ground should also be remotely connected to a point on the analog ground to minimize ground bounce.

Multiple devices on a bus

The AD5259 has two configurable address pins, pin AD0 and pin AD1. The state of these two pins is registered at power-up and decoded into the corresponding IC-compatible 7-bit address (see Table 5). This allows up to four devices on the bus to write or read independently.

show application

circuit

A feature of the AD5259 is its unique separation of the V and V supply pins. Separation provides more flexibility in applications where the required supply voltage is not always available.

In particular, liquid crystal panels typically require a voltage range of 3V to 5V. A rare exception is the circuit in Figure 46, where the 5V supply powers the digital potentiometer.

In the more common case shown in Figure 47, only the analog 14.4V and digital logic 3.3V supplies are available. By placing discrete resistors above and below the digital potentiometer, it is now possible to tap V from the resistor string itself. Depending on the resistor value chosen, in this case, the voltage at V equals 4.8 V, allowing the wipers to operate safely all the way up to 4.8 V. The current consumption of V does not affect the bias of this node as it is only on the order of microamps. v is connected to the 3.3v digital power supply of the mcu because v will draw to the 35ma needed when the eeprom. Trying to power 35mA through a 70kΩ resistor is impractical, so V is not connected to the same node as V. Therefore, V and V are provided as two separate power pins that can be tied together or handled separately; V powers the logic/EEPROM, and V biases the A, B, and W terminals for added flexibility.