The VSP2212 is a complete mixed-signal IC that contains all the key features associated with processing CCD imager output signals in video cameras, digital still cameras, security cameras, or similar applications. The front page of this data sheet shows a simplified block diagram. VSP2212 includes correlated double sampler (CDS), programmable gain amplifier (PGA), analog-to-digital converter (ADC), input clamp, optical black (OB) level clamp loop, serial interface, timing control, voltage reference generator and general purpose 8-bit digital Toanalog converter (DAC). We recommend using an off-chip transmitter follower buffer between the ccd output and the vsp2212 ccdin input. PGA gain control, clock polarity setting, and operating mode selection are available through the serial interface. When the reset pin goes low asynchronously from the clock, all parameters are reset to their default values.
Correlated Double Sampler (CDS)
The output signal of the CCD imager is sampled twice within a pixel period: once in the reference interval and once in the data interval. Subtracting these two samples extracts the pixel's video information and removes any noise common or related to the two intervals. Therefore, cds are very important to reduce reset noise and low frequency noise in ccd output signal. Figure 1 shows a simplified block diagram of the CDS and input clamp.
Depending on the application environment, a 0.1μF capacitor is recommended for CIN. In addition, we recommend an off-chip emitter follower buffer that can drive over 10pf, as 10pf of sampling capacitance and a few pf of stray capacitance can be seen at the input pins. The analog input signal range for the ccdin pin is 1vp-p, and the appropriate common mode voltage for the cds is about 0.5v to 1.5v.
The reference level is sampled during the active period of shp, and the voltage level is held on the sampling capacitor c1 on the trailing edge of shp. The data level is sampled during shd activation, and the voltage level is held on the sampling capacitor c2 on the trailing edge of shd. The switched capacitor amplifier then performs the subtraction of these two levels.
The active polarity of the SHP/SHD (active high or active low) is selectable via the serial interface (see the "Serial Interface" section for details). The default value for SHP/SHD is Active Low. However, as soon as the power is turned on, the value is "unknown". Therefore, the appropriate value must be set using the serial interface, or reset to default using the reset pin. The descriptions and timing diagrams in this data sheet are based on active low polarity (default).
The input clamp or pseudo pixel clamp buffer CCD output capacitor is coupled to the vsp2212. The purpose of the input clamp is to restore the DC component of the input signal lost due to AC coupling and to establish the desired DC bias point for cds.

Simplified block diagram of CDS and input clamp.
The cds are driven through an off-chip coupling capacitor (cin). AC coupling is strongly recommended, as the DC level of the CCD output signal is often up to several volts and the CDs won't work properly.
Enter the clamp. During the dummy pixel interval, the input level is clamped to the internal reference voltage cm (1.5v). More specifically, the virtual clamping function becomes active when both CLPDM and SHP are active. If there are no dummy pixels and/or clpdm pulses in the system, clpob pulses can be used instead of clpdm whenever clamping occurs during black pixels. In this case, both the cpldm pin (activated in synchronization with clpob) and shp become active during the optical black pixel interval, and then the virtual clamp function becomes active.
The active polarity (active high or active low) of the CLPDM and SHP can be selected via the serial interface (see the Serial Interface section for details). The default value for CLPDM and SHP is "active low". However, as soon as the power is turned on, the value is "unknown". Therefore, the appropriate value must be set using the serial interface, or reset to default using the reset pin. The descriptions and timing diagrams in this data sheet are based on active low polarity (default).
High-performance analog-to-digital converters (ADCs)
The analog-to-digital converter (adc) uses a fully differential and pipelined structure. This ADC is ideal for low voltage operation, low power requirements and high speed applications. It guarantees 12-bit resolution of output data with no missing codes. The vsp2212 includes a reference generator for the ADC. refp (positive reference, pin 38), refn (negative reference, pin 39) and cm (common mode voltage, pin 37) should be bypassed to ground with 0.1µf ceramic capacitors and should not be used elsewhere in the system ; they affect the stability of these reference levels and cause a degradation in ADC performance. Note that these are analog output pins.
Programmable Gain Amplifier (PGA)
Figure 2 shows the characteristics of the PGA gain. The pga provides a gain range of -6db to +42db, which is linear in db. Gain is controlled by a digital code with 10-bit resolution and can be set via the serial interface (see the "Serial Interface" section for details). The default value of the gain control code is 128 (pga gain=0db). However, as soon as the power is turned on, the value is "unknown". Therefore, the appropriate value must be set using the serial interface, or reset to default using the reset pin.
Optical black (ob) level clamp loop During the valid pixel interval, the reference level of the CCD output signal is clamped to the ob level by the ob level clamp loop. To determine the loop time constant, an off-chip capacitor is required and should be connected to COB (pin 28). The time constant t is given in the following equation:
T=C/(16384•Imine)
where c is the capacitance value connected to c ob, imin is the minimum current (0.15 microamps) to control the dac in the ob level clamp loop, 0.15 microamps is equivalent to 1lsb of the dac output current. When c is 0.1 μf, the time constant t is 40.7 μs.
Furthermore, the slew rate sr is given by the following equation:
SR= IMAX/C
where c is the capacitance value connected to c ob, imax is the maximum current (153 microamps) that controls the dac in the ob level clamp loop, 153 microamps is equivalent to 1023lsb of the dac output current.
In general, high-speed ob-level clamping results in "clamping noise" (or "white stripe noise"), however, the noise decreases as c increases. On the other hand, an increase in c takes longer to resume from standby mode or immediately after power up. Therefore, we consider 0.1µf to 0.22µf to be a reasonable value for C. However, this depends on the application environment; we recommend careful tuning using trial and error.

pga gain characteristics.
In order to correctly extract video information, the CCD signal must be referenced to a recognized optical black (ob) level. The vsp2212 has an auto-calibration loop to establish the ob level using the optical black pixels output from the CCD imager. The input signal level of the ob pixel is recognized as the actual "ob level" and the loop should be closed during this time while the clpob is active.
The "OB clamp level" (base level) can be programmed via the serial interface (see the "Serial Interface" section for more details). Table 1 shows the relationship between the input code and the ob clamp level.

The active polarity of the CLPOB (active high or active low) is selectable via the serial interface (see the "Serial Interface" section for details). The default value of clpob is "active low". However, as soon as the power is turned on, the value is "unknown". Therefore, the appropriate value must be set using the serial interface, or reset to the default value by resetting the pins. The descriptions and timing diagrams in this data sheet are based on active low polarity (default).
Pre-Blanking and Data Delay Some CCDs have large transient output signals during the blanking interval. Such a signal can exceed the 1vp-p input signal range of the vsp2212 and will supersaturate the vsp2212. Recovery time from saturation can be long. To avoid this, the vsp2212 has an input blanking (or pre-blanking) function (pblk). When pblk goes low, the ccdin input is disconnected from the internal cds stage, preventing large transients from passing through. To accommodate the clock delay of the vsp2212, the digital output of the vsp2212 will go to zero after the 11th rising edge of adcck from pblk to low. In this mode, digital output data is output on the rising edge of adcck with a delay of 11 clock cycles (data delay of 11). Note that in normal operation, the digital output data appears on the rising edge of adcck with a delay of 9 clock cycles (data delay of 9).
It is recommended not to activate CLPOB during PBLK activation to maintain stable and accurate OB clamping. Since the CCDIN input is disconnected from the internal circuitry, the OB clamp level is not the same as the "actual" OB level established by the CCD imager output, even though the autocalibration loop is closed while the CLPOB is active. Missing ob clamps can affect image quality.
If the input voltage is 0.3V above the supply rail, or 0.3V below the ground rail, the protection diodes are turned on to prevent the input voltage from rising further. Such high swing signals may cause equipment damage to the vsp2212 and should be avoided.
Standby Mode In order to save power, when the vsp2212 is not in use, the vsp2212 can be set to standby mode (or power-down mode) through the serial interface. See the "Serial Interface" section for more information. In this mode, all function blocks are disabled and the digital outputs will return to zero. The current consumption will drop to 1mA. Since all bypass capacitors will be discharged in this mode, powering up from standby mode takes a considerable amount of time (typically 200 to 300 ms).
voltage reference
All reference voltages and bias currents required by the VSP2212 are generated by its internal bandgap circuitry. There are three main reference voltages used by cds and adc: refp (positive reference, pin 38), refn (negative reference, pin 39) and cm (common mode voltage, pin 37). refp, refn, and cm should be heavily decoupled with appropriate capacitors (e.g. 0.1µf ceramic capacitors) and should not be used elsewhere in the system; they affect the stability of the reference level and result in degraded ADC performance. Note that these are analog output pins.
BYPP2 (Pin 29), BYP (Pin 31), BYPM (Pin 32) are also reference voltages used in analog circuits. BYP should use a 0.1µF ceramic capacitor to ground. The capacitance values of BYPP2 and BYPM affect the step response. Therefore, we consider 1000pf to be a reasonable value. However, this depends on the application environment; we recommend careful tuning using trial and error.
All BYPP2, BYP and BYPM should be heavily decoupled with appropriate capacitors and not used elsewhere in the system. They can affect the stability of these reference levels and cause performance degradation. Note that these are analog output pins.
Serial Interface The serial interface has a 2-byte shift register and various parallel registers to control all digital programmable features of the vsp2212. Writing to these registers is controlled by four signals (sload, sclk, sdata, reset). To enable the shift register, sload must be pulled low. sdata is the serial data input and sclk is the shift clock. The data of sdata is brought into the shift register on the rising edge of sclk. The data length should be 2 bytes. After a 2-byte shift operation, the data in the shift register is transferred to the parallel latch on the rising edge of sload. In addition to the parallel latches, there are several registers dedicated to device-specific functions, which are synchronized to ADCCK. The data in the parallel latches takes 5 or 6 clock cycles to write to these registers. Therefore, to complete the data update, it takes 5 or 6 clock cycles after parallel latching on the rising edge of sload.
The serial interface data format is shown in Table 2. test is the test mode flag (only for burr brown), a0 to a2 are the addresses of various registers, and d0 to d11 are the data or operand fields.

Power, Ground, and Equipment Decoupling Recommendations
The VSP2212 integrates a very high precision and high speed analog-to-digital converter and analog circuitry that is susceptible to any extraneous noise from the track or elsewhere. Therefore, it should be considered an analog component, and all supply pins except DRVDD should be powered by the system's only analog supply. This will ensure the most consistent results, as digital power lines often carry high levels of broadband noise that would otherwise couple into the device and degrade achievable performance. Proper grounding, short lead lengths, and use of ground planes are also important for high-frequency designs. Multilayer PC boards are recommended for best performance as they offer significant benefits such as minimizing ground impedance, separating signal layers by ground plane, etc. It is strongly recommended to connect the analog and digital ground pins of the VSP2212 to the IC and only to the analog ground of the system. The driver stage for the digital outputs (b[11:0]) is powered through a dedicated power supply pin (drvdd) and should be completely separated from the other supply pins, or at least use ferrite beads. It is also recommended to minimize capacitive loading on the output data lines (typically less than 15pF). Larger capacitive loads require higher charging current surges that can feed back into the analog portion of the vsp2212 and affect performance. If possible, external buffers or latches should be used, providing the added benefit of isolating the vsp2212 from any digital noise activity on the data lines. Additionally, resistors in series with each data line help minimize inrush current. Values in the range of 100Ω to 200Ω will limit the instantaneous current provided by the output stage to charge parasitic capacitances when the output level changes from low to high or from high to low. Due to the high speed of operation, the converter also generates high frequency current transients and noise, which are fed back to the power and reference lines.
Requires that the supply and reference pins be adequately bypassed. In most cases, a 0.1µf ceramic chip capacitor is sufficient to separate the reference pins. The power pins should be separated from the ground plane using a parallel combination of tantalum (1µf to 22µf) and ceramic (0.1µf) capacitors. The effectiveness of decoupling depends largely on the proximity to individual pins. drvdd should be separated from the proximity of drvgnd. Special attention must be paid to bypassing cob, bypp2, and bypm because these capacitor values determine the important analog performance of the device.