Features: 12/16-bit resolution and monotonicity; current output range: 4mA to 20mA, 0mA to 20mA, or 0mA to 24mA; Typical Total Unadjusted Error (TUE) of ±0.01% FSR; ±3ppm/°C typical output drift; flexible serial digital interface; on-chip output fault detection; on-chip reference (10 ppm/°C max); feedback/monitoring of output current asynchronous clear function; supply (AVDD) range 10.8 V to 40 V; AD5410arez/AD5420arez; 10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ; output loop compliant with AVDD-2.5 V; temperature range: -40°C to +85°C; .

Applications: Process Control; Actuator Control; PLC; Hart Network Connections.

General Instructions

The AD5410/AD5420 are low cost, high precision, fully integrated 12/16-bit converters with programmable current source outputs designed to meet the requirements of industrial process control applications. The output current range is programmable with an overrange function of 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA. Output open circuit protection. The device operates on a power supply (AVDD) range of 10.8 V to 60 V. Output loop compliance is 0 V to 2.5 V. The flexible serial interface is compatible with spi, microwire™, qspi™ and dsp and can operate in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on reset feature that ensures the device powers up in a known state, as well as an asynchronous clear pin that sets the output to the low end of the selected current range. The unadjusted total error is typically ±0.01%fsr.

Package product

Hart Modems: AD5700, AD5700-1

the term

Relative Accuracy or Integral Nonlinearity (INL) For DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation (in %fsr) from a straight line passing through the endpoints of the DAC transfer function. A typical inl and code diagram is shown in Figure 7.

Differential Nonlinearity (DNL)

Differential nonlinearity (dnl) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. A differential nonlinearity of ±1 lsb maximum specified ensures monotonicity. The monotonicity of the DAC is guaranteed by design. A typical DNL and code diagram is shown in Figure 8.

Unadjusted Total Error (Tuesday)

Total unadjusted error (tue) is a measure of output error that takes into account various errors, namely input error, offset error, gain error, output drift, power supply, and temperature. TUE is expressed in %fsr. A typical TUE and code diagram is shown in Figure 9.

Monotonicity

A dac is monotonic if the output increases or stays the same to increase the digital input code. The AD5410/AD5420 are monotonic over their entire operating temperature range.

full scale error

Full-scale error is a measure of the output error when the full-scale code is loaded into the data register. Ideally, the output should be full scale -1 LSB. Full-scale error is expressed as a percentage of full-scale range (fsr).

Full-Scale Error Temperature Coefficient (tc) This is a measure of full-scale error as a function of temperature. The full-scale error tc is expressed in ppm fsr/°C.

gain error

This is a measure of the span error of the DAC. It is the deviation of the slope of the dac transfer characteristic from the ideal, expressed in %fsr. A plot of gain error versus temperature is shown in Figure 15.

Gain Error Temperature Coefficient (tc) This is a measure of gain error as a function of temperature. Gain error tc is expressed in ppm fsr/°C.

Current loop compliance voltage

This is the maximum voltage at the I pin whose output current is equal to the programmed value. The output power supply rejection ratio psrr indicates how the output of the DAC is affected by changes in the power supply voltage.

Voltage Reference Temperature Coefficient (tc) A voltage reference, tc, is a method of measuring the variation of the reference output voltage with temperature. The voltage reference tc is calculated using the box method, which defines tc as the maximum change in the reference output over a given temperature range, expressed in ppm/°C, as follows:

VRefMax is the maximum reference output measured over temperature.

V recombinant protein is the minimum reference output measured over the entire temperature range.

V Supplement is the nominal reference output voltage, 5 V.

Temperature variation is the specified temperature range, -40°C to +85°C.

Reference load regulation

Load regulation refers to the change in the reference output voltage due to a specific change in load current. Expressed in ppm/ma.

theory of operation

The AD5410/AD5420 are precision digital-to-current loop output converters designed to meet the requirements of industrial process control applications. They provide a high precision, fully integrated, low cost microcontroller solution for generating current loop outputs. Available current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The user can select the desired output configuration through the control register.

architecture

The DAC core architecture of the AD5410/AD5420 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 37. The four msbs of a 12-bit or 16-bit data word are decoded to drive the 15 switches, e1 to e15. Each switch connects one of 15 matched resistors to ground or to the reference buffer output. The remaining 8/12 bits of the data word driving switch s0 to switch s7 or switch s0 to switch s11 are an 8/12-bit voltage mode r-2r ladder network.

The voltage output from the DAC core is converted to current (see Figure 38) and then mirrored to the supply rails so the application can see the output of the current source relative to ground.

serial interface

The AD5410/AD5420 are controlled by a versatile 3-wire serial interface that operates at clock frequencies up to 30 MHz. They are compatible with spi, qspi, microwire and dsp standards.

input shift register

The input shift register is 24 bits wide. Data is first loaded into the device msb as a 24-bit word under the control of the serial clock input sclk. Data is recorded on the rising edge of SCLK. The input shift register consists of 8 address bits and 16 data bits, as shown in Table 6. The 24-bit word is unconditionally latched on the rising edge of the latch. Data will continue to be clocked regardless of the state of the latches. On the rising edge of latching, the data present in the input shift register is latched; that is, the last 24 bits to be latched before the rising edge of latching are the latched data. The timing diagram for this operation is shown in Figure 2.

Independent operation

The serial interface works with sequential and non-sequential sclks. The continuous SCLK source can only be used when the latch is high after the correct number of data bits have been clocked. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and the latch must be taken high after the last clock to latch the data. The first rising edge of sclk clocked in the msb of the data word marks the start of a write cycle. 24 rising clock edges must be applied to SCLK before the latch is brought high. If the latch is high before the rising SCLK edge at 24, the written data is invalid. The incoming data is also invalid if more than 24 rising SCLK edges are applied before the latch goes high.

Daisy Chain Operation

For systems with multiple devices, the SDO pins can be used to chain multiple devices together, as shown in Figure 39. This daisy-chain mode can be used for system diagnostics and to reduce the number of serial interface lines. Daisy-chain mode is enabled by setting the dcen bit in the control register. The first rising edge of sclk clocked in the msb of the data word marks the start of a write cycle. SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data will fluctuate out of the input shift register and appear on the SDO line. This data has been clocked on the last falling edge of SCLK and is valid on the rising edge of SCLK. A multi-device interface is constructed by connecting the sdo of the first device to the sdin input of the next device in the chain. Each device in the system requires 24 clock pulses.

Therefore, the total number of clock cycles must be equal to 24 × n, where n is the total number of AD5410/AD5420 devices in the chain. The latch is high when the serial transfer to all devices is complete. This will lock the incoming data in each device in the daisy chain. The serial clock can be a continuous clock or a gated clock.

The continuous SCLK source can only be used when the latch is high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and the latch must be taken high after the last clock to latch the data. The timing diagram is shown in Figure 4.

readback operation

When writing to the input shift register, the readback mode is invoked by setting the address byte and reading the address, as shown in Table 9 and Table 8. The next write to the AD5410/AD5420 should be a NOP command that clocks out data from the previously addressed register, as shown in Figure 3. By default, the SDO pin is disabled. After the AD5410/AD5420 is addressed for a read operation, a rising edge on the latch enables the SDO pin to expect data to be clocked. After the data is clocked on the sdo, a rising edge on the latch again disables (tri-states) the sdo pin. For example, to read back a data register, the following sequence should be performed:

1. Write 0x020001 to the AD5410/AD5420 input shift register. This configures the part for read mode with the data register selected.

2. Next is the second write, a nop condition, 0x000000. During the write process, the data from the data register is clocked on the SDO line.

power-on state

A power-on reset circuit ensures that all registers are loaded with zero code when the AD5410/AD5420 are powered up. Therefore, the output is disabled (tri-stated). Additionally, after power-up, the internal calibration registers are read and the data is applied to the internal calibration circuit. For reliable read operation, there must be sufficient voltage on the AV supply when the DVCC supply powers up to trigger a read event. Turning on the dvcc power after the avdd power has reached at least 5v ensures this. If the dvcc and avdd are energized at the same time, the energization rate of the power supply should be greater than, typically 5000 volts/sec. If the internal DVCC is enabled, the power supply should be powered up at a rate higher than the typical 2000 V/sec. If this is not possible, simply issue a reset command to the AD5410/AD5420 after power up. This will perform a power-on reset event, read the calibration registers and ensure the specified operation of the AD5410/AD5420. To ensure proper calibration and allow the internal reference to settle to its correct trim value, 40 µs should be allowed after a successful power-on reset.

Transfer Function

For the current output ranges of 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA, the output current is expressed as:

data register

The data register is addressed by setting the address byte of the input shift register to 0x01. The data to be written to the data register is entered into position DB15 to DB4 of the AD5410 and DB15 to DB0 of the AD5420, respectively.

control register

The control register is addressed by setting the address byte of the input shift register to 0x55. Data written to the control register is input to location DB15 to location DB0.

reset register

The reset register is addressed by setting the address byte of the input shift register to 0x56. The reset register contains a reset bit at location db0. Writing logic high performs a reset operation that restores the part to its powered state.

status register

The status register is a read-only register. Status register bit function.

AD5410/AD5420 Features

error alarm

The AD5410/AD5420 feature a fault pin, which is an open-drain output that allows multiple AD5410/AD5420 devices to be connected to a single pull-up resistor for global fault detection. The fault pin is forcibly activated by any of the following fault conditions:

(1) Due to the open-loop circuit or insufficient power supply voltage, the IOUT voltage tries to rise above the compliance range. The output current is controlled by a PMOS transistor and an internal amplifier, as shown in Figure 38. The internal circuitry that develops the fault output avoids the use of comparators with window limits, as this requires an actual output error before the fault output becomes active. Conversely, a signal is generated when the remaining drive capability of the output stage's internal amplifier is less than about 1v (when the gate of the output pmos transistor is close to ground). Therefore, the fault output activates slightly before the compliance limit is reached. Since the comparison takes place in the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output error occurs until the faulty output becomes active.

(2) If the core temperature of AD5410/AD5420 exceeds about 150°C. The iout fault and overtemp bits of the status register are used with the fault pin to notify the user of a fault condition that caused the fault pin to be asserted.

Asynchronous clear (clear)

Clear is an active high clear that clears the current output to the bottom of its programmed range. It must be kept clear for the minimum amount of time to complete the operation. When the clear signal returns low, the output remains at the clear value. The pre-cleared value can be restored by pulsing the latch signal low without timing any data. New values cannot be programmed until the pin is cleared back low.

internal reference

The AD5410/AD5420 contain an integrated +5 V voltage reference with a maximum initial accuracy of ±5 mV and a maximum temperature drift coefficient of 10 ppm/°C. The reference voltage is buffered and available externally for use elsewhere in the system.

External current setting resistor

In Figure 38, rset is an internal sense resistor that is part of the voltage-to-current conversion circuit. The stability of the output current over temperature depends on the stability of the rset value. An external low-drift resistor with a precision of 15 kΩ can be connected from the RSET pin of the AD5410/AD5420 to ground; this improves the overall performance of the AD5410/AD5420. External resistors are selected via control registers.

digital power

By default, the DVCC pin accepts a 2.7 V to 5.5 V supply. Alternatively, via the DVCC select pin, the internal 4.5 V supply can be output on the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. The advantage of this device is that the digital power supply does not have to be carried across the isolation barrier. Enable the internal power supply by leaving the DV select pin unconnected. To disable the internal power supply, the DVCC selection should be tied to 0 V. DVCC is capable of supplying up to 5mA of current.

External boost function

As shown in Figure 41, adding an external boost transistor reduces the power dissipated in the AD5410/AD5420 by reducing the current in the on-chip output transistor (divided by the current gain of the external circuit). Discrete npn transistors with breakdown voltage bvceo greater than 40v can be used.

The external boost capability allows the AD5410/AD5420 to be used at extremes of supply voltage, load current, and temperature range. Boost transistors can also be used to reduce the amount of temperature-induced drift in parts. This minimizes the temperature-induced drift of the on-chip voltage reference, which improves drift and linearity.

Hart Communications

The AD5410/AD5420 include a CAP2 pin into which a Hart signal can be coupled. If the output is enabled, the Hart signal appears on the current output. To obtain a peak-to-peak current of 1 mA, the signal amplitude at the CAP2 pin must be 48 mV peak-to-peak. Assuming a modem output amplitude of 500 mV peak-to-peak, its output must be attenuated by 500/48 = 10.42. If this voltage is used, the current output should meet the Hart amplitude specification. Figure 42 shows the recommended circuit for Hart signal attenuation and coupling.

When determining the absolute value of the capacitor, make sure the fsk output from the modem is not distorted. Therefore, the bandwidth presented to the modem output signal must pass the 1200 Hz and 2200 Hz frequencies. Recommended values are C1=2.2nF and C2=22nF. To meet hart's analog rate-of-change requirements, the output's slew rate must be digitally controlled.

Digital Slew Rate Control

The slew rate control feature of the AD5410/AD5420 allows the user to control the rate at which the output current changes. With the slew rate control feature disabled, the output current changes at a rate of approximately 16 mA over 10 microseconds. This varies with load conditions. To reduce slew rate, enable slew rate control. This feature is enabled through the sren bit of the control register, the output is not converted directly between two values, but digitally stepped at a rate defined by two parameters accessible through the control register. The parameters are sr clock and sr step. The sr clock defines the update rate of the digital conversion, and the sr step defines the amount of change in the output value with each update. These two parameters together define the rate of change of the output current. Table 18 and Table 19 summarize the value ranges for the sr clock and sr step parameters. Figure 43 shows the output current change for ramp times of 10 ms, 50 ms, and 100 ms.

When the slew rate control function is enabled, all output changes are made at the programmed slew rate. If the clear pin is asserted, the output transitions to the zero-scale value at the programmed transition rate. The output can be stopped at its current value by writing to the control register. To avoid stalling output conversions, before writing to any AD5410/AD5420 registers, the conversion active bit can be read to check if the conversion is complete. The update clock frequency for any given value is the same for all output ranges. However, for a given step size value, the step size varies across different output ranges because the lsb size is different for each output range. Programmable slew time range for any output range full-scale change. obtained by Equation 1. The digital slew rate control feature causes the current output to be stepped, as shown in Figure 47. Figure 47 also shows how to remove the ladder by connecting capacitors to the CAP1 and CAP2 pins, as described in the I Filter Capacitors section.

filter capacitor out

Capacitors can be placed between CAP1 and AVDD, and CAP2 and AVDD, as shown in Figure 44.

As shown in Figure 45, the capacitor forms a filter on the current output circuit, reducing the bandwidth and slew rate of the output current. Figure 46 shows the effect of capacitors on the output current slew rate. To significantly reduce the rate of change, very large capacitance values are required, which may not be suitable for some applications. In this case, the digital slew rate control feature should be used. As shown in Figure 47, capacitors can be used in conjunction with the digital slew rate control function as a method of eliminating the steps caused by digital code increments.

Output current feedback/monitoring

For feedback or monitoring of the output current value, a sense resistor can be placed in series with the output pin and the voltage drop across it is measured. In addition to being an add-on, the resistor adds the required compliance voltage. Another way is to use resistors that are already in place. One such resistor is R3, which is internal to the AD5410/AD5420, as shown in Figure 48. By measuring the voltage between the R3Sense and Boost pins, the value of the output current can be calculated as follows:

I out = 3 - (2) where: VR R3 I Bias VR3 is the voltage drop across R3 measured between R3's sense and boost pins. I Bias is the constant bias current flowing through R3, typically 444µA. The resistance value of R3 resistor R3, the typical value is 40Ω.

Both R3 and IBIAS have a tolerance of ±10% and a temperature coefficient of 30 ppm/°C. Connecting to R3Sense instead of AVDD avoids merging together R3's internal metal connections with large temperature coefficients and causing large errors. Figure 49 shows the relationship between R3 and ambient temperature, and Figure 50 shows the relationship between R3 and output current.

To eliminate errors caused by R3 and IBIAS tolerances, two measurement calibrations can be performed, as shown in the following example:

1. Program code 0x1000, measure IOUT and VR3. In this example, the measurements are: IOUT=1.47965mA; VR3=79.55446mV;

2. Program code 0xF000, measure IOUT and VR3 again. The measured values this time are: IOUT=22.46754 milliamps; VR3=946.39628 millivolts;

Using this information and Equation 2, two simultaneous equations can be generated from which the values of R3 and Ibias can be calculated as follows:

Simultaneous equation 1:

Simultaneous equation 2:

From these two equations:

Equation 2 turns into VR 3:

application information

Driving Inductive Loads

When driving inductive or poorly defined loads, connect a 0.01µF capacitor between I and GND. This ensures stability when the load exceeds 50mh. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling.

Alternatively, capacitors can be connected from cap1 and/or cap2 to av to reduce the slew rate of the current. The digital slew rate control feature may also prove useful in this case.

Transient Voltage Protection

The AD5410/AD5420 contain ESD protection diodes to prevent damage from normal operation. However, industrial control environments can subject I/O circuits to higher transients. To protect the AD5410/AD5420 from excessive voltage transients, external power supply diodes and inrush current limiting resistors may be required, as shown in Figure 51. The resistor value is limited by the fact that during normal operation the output level at I must remain within its AV-2.5 V compliance limit and the two protection diodes and resistors must have appropriate power ratings. Further protection can be provided with transient voltage suppressors (tvs) or transorbs. They function as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against positive and negative high voltage transients) and are available in a variety of isolation and breakdown voltage ratings. It is recommended to protect all field-connected nodes.

Layout Guidelines

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board (PCB) on which the AD5410/AD5420 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5410/AD5420 are in a system where multiple devices require an AGND to DGND connection, they should only be connected at one point. The star ground point should be as close as possible to the device.

The D5410/AD5420 should have ample supply bypassing of 10µF, in parallel with 0.1µF on each supply, as close to the package as possible, ideally close to the device. The 10µf capacitors are of the tantalum bead type. The 0.1µf capacitors should have low efficiency series resistance (esr) and low efficiency series inductance (esi), like common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents generated by internal logic switches.

The power supply lines to the AD5410/AD5420 should use the largest possible traces to provide a low impedance path and reduce the effect of faults on the power supply lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the sdin and sclk lines helps reduce crosstalk between them (not needed on multi-layer boards with separate ground planes, but separating the lines helps reduce crosstalk). Because noise can couple to the DAC output, it is imperative to minimize noise on the Refin line.

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects on the board. Microstrip technology is by far the best approach, but it's not always possible on double-sided panels. In this technique, the component side of the board is dedicated to the ground plane, and the signal traces are placed on the solder side.

Electrically isolated interface

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the control circuit from any dangerous common-mode voltages that may occur. The Icoupler® family of products from Analog Devices, Inc. provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5410/AD5420 is ideal for an isolated interface because the number of interface lines is kept to a minimum. Figure 52 shows a 4-channel isolated interface using the ADUM1400 with the AD5410/AD5420. For more information, please visit.

Microprocessor Interface 2.5

The microprocessor interfaces with the AD5410/AD5420 through a serial bus that uses a protocol compatible with the microcontroller and DSP processors. The communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a latch signal. The AD5410/AD5420 require a 24-bit data word whose data is valid on the rising edge of SCLK.

For all interfaces, DAC output updates are initiated on the rising edge of the latch. The contents of the registers can be read using the readback function.

Thermal and Supply Considerations

AD5410/AD5420 Design Maximum Operating Speed

The connection temperature is 125°C. It is important that the device does not operate under conditions that cause the connection temperature to exceed this value. If the AD5410/AD5420 are operated at maximum AV while driving the maximum current (24 mA) directly to ground, an excessive junction temperature will occur. In this case, the ambient temperature should be controlled or AVDD should be reduced.

At the highest ambient temperature of 85°C, the 24-lead tssop can dissipate 1.14w, and the 40-lead lfcsp can dissipate 1.21w.

To ensure that the junction temperature does not exceed 125°C when the maximum current of 24mA is drawn directly into ground (while adding 4mA of on-chip current), AV should be derated from the maximum rating to ensure that the DD package does not need to consume more than before. Multiple energy descriptions (Figure 53 and Figure 54)

Industrial, Hart Compatible Analog Output Applications

Many industrial control applications require a precisely controlled current output signal, and the AD5410/AD5420 are ideal for such applications. Figure 55 shows the AD5410/AD5420 circuit design for an output module designed specifically for industrial control applications. The design provides a hart-capable current output with the hart functionality provided by the ad5700/ad5700-1hart modem, the industry's lowest power and smallest footprint hart compatible IC modem. To save even more space, the AD5700-1 provides a 0.5% accurate internal oscillator. The hart_-out signal from the AD5700 is attenuated and AC coupled to the cap2 pin of the AD5420. For more information on this configuration, see Application Note AN-1065. An alternative method of coupling the Hart signal to the rset pin is provided in circuit note CN-0270 (for external rset only). Using either configuration will cause the AD5700 Hart modem output to modulate an analog current from 4 mA to 20 mA without affecting the DC level of the current. This circuit follows the HART physical layer specification as defined by the HART Communication Foundation.

The module is powered by a 24 volt field power supply that powers the AV directly. For transient overvoltage protection, a transient voltage suppressor (TV) is placed on the IOUT and field power connections. A 24V TV is placed on the input and a 36V TV is placed on the field power input. For added protection, clamp diodes are connected from the IOUT pin to the AVDD and GND supply pins. The recommended external bandpass filter for the AD5700 Hart modem includes a 150 kΩ resistor, which limits the current to a level low enough to be intrinsically safe. In this case, the input has higher transient voltage protection, so no additional protection circuitry is required even in the harshest industrial environments.

Isolation between the AD5410/AD5420 and backplane circuitry features ADUM1400 and ADUM1200 i-coupler digital isolators; for more information on i-coupler products, visit. The internally generated digital power supply of the AD5410/AD5420 powers the field side of the digital isolator, eliminating the need to generate digital power on the field side of the isolation barrier. The AD5410/AD5420 digital power outputs provide up to 5 mA, which is sufficient to meet the 2.8 mA requirement of the ADum1400 and ADum1200 operating at logic signal frequencies up to 1 MHz. To reduce the number of isolators required, non-critical signals like clear can be connected to gnd and fault, while sdo can be left unconnected, reducing the isolator requirement to only 3 signals. However, doing so will disable the part's failure alert function.