Characteristics: V/F conversion to 1 MHz; robust overall construction; very low nonlinearity; 0.002% typ at 10 kHz; 0.005% typ at 100 kHz; 0.07% typ at 1 MHz; input offset Adjustable to zero; CMOS or TTL compatible; unipolar, bipolar or differential V/F; V/F or F/V conversion; surface mount; MIL-STD-883 compliant versions available.

Product Description

The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. The inherent monotonicity of the v/f transfer function makes the ad650 a high-resolution analog-to-digital converter. Flexible input configurations allow the use of multiple input voltage and current formats, and open collector outputs with separate digital grounds allow simple connection to standard logic families or optocouplers.

The linearity error of the AD650 is typically 20ppm (0.002% of full scale), with a maximum of 50ppm (0.005%) at 10kHz full scale. This corresponds to about 14 bits of linearity in the analog-to-digital converter circuit. Higher full-scale frequencies or longer count intervals can be used for higher resolution conversions. The AD650 has an effective dynamic range of 60 years, allowing extremely high resolution measurements. The linearity of the AD650KN, BD, and SD grades is guaranteed to be less than 1000 ppm (0.1%) even at 1 MHz full scale.

In addition to analog-to-digital conversion, the AD650 can be used in isolated analog signal transmission applications, phase locked loop circuits, and precision stepper motor speed controllers. In F/V mode, the AD650 can be used in precision tachometer and FM demodulation circuits. The input signal range and full-scale output frequency are user programmable through two external capacitors and a resistor. The input bias voltage can be zeroed with an external potentiometer.

The AD650JN and AD650KN are packaged in plastic 14 lead dipping. The AD650JP is available in a 20-lead plastic lead chip carrier (PLCC). Both plastic packaged versions of the AD650 are specified over the commercial (0°C to +70°C) temperature range. For industrial temperature range (–25°C to +85°C) applications, the AD650AD and AD650BD are available in ceramic packages. The AD650SD is available over the extended temperature range of -55°C to +125°C.

Product Highlights

1. In addition to very high linearity, the AD650 can operate at full-scale output frequencies up to 1MHz. The combination of these two features makes the AD650 an inexpensive solution for applications requiring high-resolution monotonic A/D conversion.

2. The AD650 has a very general architecture and can be configured to accommodate bipolar, unipolar or differential input voltages or unipolar input currents.

3. ttl or cmos compatibility is achieved by using opencollector frequency output. For traditional cmos or ttl logic levels, pull-up resistors can be connected to voltages as high as +30v or +15v or +5v.

4. The same components used for v/f conversion can also be used for f/v conversion by adding a simple logic bias network and reconfiguring the AD650.

5. AD650 provides independent analog and digital grounding. This feature allows preventing ground loops in practical applications.

6. AD650 is available in MILSTD-883 version. For detailed specifications, see the analog device military data sheet or the current AD650/883B data sheet.

circuit operation

Unipolar configuration

The AD650 is a charge-balanced voltage-to-frequency converter. In the wiring diagram shown in Figure 1 or the block diagram of Figure 2a, the input signal is converted into an equivalent current by the input resistor rin. This current is precisely balanced by an internal feedback current delivered in short, timed pulses from a 1 mA internal current source from the switch. These current pulses can be thought of as precisely defined charge packets. The number of charge packets required, each to generate a pulse for an output transistor, depends on the amplitude of the input signal. Since the number of charge packets transferred per unit time depends on the amplitude of the input signal, a linear voltage-to-frequency conversion will be done. The frequency output is provided through an open collector transistor.

A more rigorous analysis shows how the charge-balancing voltage-frequency conversion occurs.

As shown in Figure 2a, the device is arranged as a v-to-f converter. The device consists of input integrator, current source and steering switch, comparator and one-shot trigger. When the output of one trigger is low, the current steering switch S1 diverts all the current to the output of the op amp, this is called the integration period. When a trigger is fired once and its output is high, switch s1 diverts all current to the op amp's summing junction; this is called the reset cycle. Two different states and different branch currents are shown in Figure 2. It should be noted that the output current from the op amp is the same for either state, thus minimizing transients.

A positive input voltage produces a current (iin=vin/rin) that charges the integrator capacitor cint. As charge builds up on CINT, the integrator's output voltage ramps toward ground. When the integrator output voltage (pin 1) exceeds the comparator threshold (–0.6 volts), the comparator triggers a trigger with a time period tos determined by the trigger capacitor cos. Specifically, the one-time period is:

Once the integrator output voltage exceeds the comparator threshold and the integrator ramps up by a certain amount, the reset cycle begins:

After the reset period is over, the device begins another integration period, as shown in Figure 2, and starts ramping down again. The amount of time required to reach the comparator threshold is as follows:

Now the output frequency is:

Note that the integrating capacitor cint has no effect on the transfer relationship, but only determines the amplitude of the integrator output sawtooth signal.

one-time timing

A key part of the preceding analysis is the one-time period given in Equation (1). This time period can be decomposed into a propagation delay of approximately 300 ns, and a second time period linearly related to the timing capacitance cos. When a trigger is triggered, the voltage switch holding pin 6 to analog ground opens, allowing this voltage to vary. An internal 0.5mA current source is connected to pin 6, which then draws its current from cos, causing the voltage at pin 6 to drop linearly. At approximately –3.4 V, the single-shot resets itself, ending the timing cycle and restarting the V/F conversion cycle. The total one-time period can be expressed mathematically as:

Substitute the actual value quoted above:

This simplifies to the time period equation given above.

Component selection

The user can only select four component values. These are the input resistor rin, the timing capacitor cos, the logic resistor r2 and the integration capacitor cint. The first two determine the input voltage and full-scale frequency, while the last two are determined by other circuit factors.

Of the four components to be selected, R2 is the easiest to define. As a pull-up resistor, you should choose to limit the current through the output transistor to 8ma if you want a TTL of 0.4v max. For example, if using a 5V logic supply, R2 should be no less than 5V/8mA or 625 ohms. Larger values can be used if desired.

RIN and COS are the only two parameters that set the full-scale frequency to fit a given signal range. The swing variables affected by the choice of rin and cos are nonlinear. The selection guide in Figure 3 illustrates this very vividly. In general, larger cos values and lower full-scale input currents (higher rin values) provide better linearity. In Figure 3, the meaning of the four different options for RIN is shown. Although the selection guide is set for a unipolar configuration with an input signal range of 0 to 10 V, the results can be extended to other configurations and input signal ranges. For a full-scale frequency of 100 kHz (corresponding to a 10 V input), you can see that Rin = 20 K and Cos = 620 pF give the lowest nonlinearity of the available choices, 0.0038%. Also, if you want to use the highest frequency, this will yield a minimum nonlinearity of 20ppm, which is about 33kHz (40.2kΩ and 1000pf).

For input signal spans other than 10 V, the input resistance must be scaled. For example, if 100 kΩ is called for a 0 V–10 V span, then 10 K would be used for a 0 V–1 V span, or 200 kΩ for a ±10 V bipolar connection.

The final component to choose is the integration capacitor CINT. In almost all cases, the optimal value of CINT can be calculated using the following formula:

When the proper cint value is used, the charge-balanced structure of the AD650 provides continuous integration of the input signal, thus generating a large amount of noise and interference.

If the output frequency is measured by counting pulses within a constant gate period, the integration provides infinite normal mode rejection for frequencies corresponding to the gate period and its harmonics. However, if the integrator stage is saturated with excessive noise pulses, the continuous integration of the signal will be interrupted, causing noise to appear at the output. If the approximate amount of noise that will appear on cint is known (vnoise), the value of cint can be checked using the following inequality:

For example, consider an application that requires a maximum frequency of 75 kHz, a signal range of 0 V–1 V, and a supply voltage of only ±9 V. The component selection guidelines in Figure 3 were used to select 2.0 kΩ for RIN and 1000 pF for COS. This results in a one-shot time period of about 7 microseconds. Substituting 75 kHz into Equation 7 yields a value of 1300 pF for CINT. As the input signal approaches zero, during the reset phase, 1 mA flows through the integrated capacitor to the switched current sink, causing the voltage on CINT to increase by about 5.5 volts. Since the integrator output stage requires about 3 volts of head space to function properly, there is only a 0.5 volt margin left for integrating extraneous noise on the signal lines. Negative noise pulses at this time can saturate the integrator, causing signal integration errors. Raising cint to 1500 pf or 2000 pf will provide more noise margin, eliminating this potential point of failure.

Bipolar V/F

Figure 4 shows how an internal bipolar current receiver can be used to provide half-scale offset for a ±5 V signal range while providing a maximum output frequency of 100 kHz. When a 1.24 kΩ resistor is connected between pins 4 and 5, the nominal 0.5 mA (±10%) bias current sink is enabled. So, with a nominal 10 kΩ resistance to ground shown, there is a -5 V offset at pin 2.

Since pin 3 must also be -5V, the current through RIN is: 10V/40kOhms = +0.25mA (at VIN=+5V), 0mA (at VIN=+5V) –5 volts).

The guidelines used when selecting components are the same as those outlined in the unipolar configuration, with only one change. The voltage over the entire signal range must be equal to the maximum value

Input voltage in unipolar configuration. In other words, the value of the input resistance rin is determined by the input voltage span rather than the maximum input voltage. A diode from pin 1 to ground is also recommended. This is discussed further in the "Other Circuit Conditions" section.

In a unipolar circuit, rin and cos must have low temperature coefficients to minimize the overall gain drift. The 1.24 kΩ resistor used to activate the 0.5 mA bias current should also have a low temperature coefficient. The temperature coefficient of bipolar bias current is about –200 ppm/°C.

Unipolar V/F, Negative Input Voltage

Figure 5 shows the connection diagram for negative input voltage V/F conversion. In this configuration, the full-scale output frequency occurs at the negative full-scale input, and zero output frequency corresponds to zero input voltage.

A very high impedance signal source can be used since it only drives the non-vertical integrator input. The typical input impedance of this terminal is 1 GΩ or higher. For v/f conversion of a positive input signal using the connection diagram of Figure 1, the signal generator must be able to supply the integrated current to drive the AD650. For the negative V/F conversion circuit in Figure 5, the integral current is drawn from ground through R1 and R3, and the active input is high impedance. The circuit operation for negative input voltages is very similar to the positive input unipolar conversion described in the previous section. For best run results, use the component equations listed in this section.

F/V conversion

The AD650 also makes a very linear frequency-to-voltage converter. Figure 6 shows the connection diagram for F/V conversion with TTL input logic levels. Each time the input signal crosses the comparator threshold and goes negative, a trigger is activated and switches 1 mA to the integrator input for the measured time period (determined by cos). As the frequency increases, the amount of charge injected into the integrated capacitor increases proportionally. The voltage across the integrator stabilizes when the leakage current through r1 and r3 is equal to the average current being switched to the integrator. The net result of these two effects is that the average output voltage is proportional to the input frequency. Optimum performance is achieved by selecting components using the same guidelines and equations listed in the v/f conversion section.

high frequency operation

Proper RF techniques must be followed when the AD650 is at or near its maximum frequency of 1 MHz. Lead lengths must be kept as short as possible, especially on one-shot and integrated capacitors, and at integration and junctions. Additionally, at maximum output frequencies above 500 kHz, a 3.6 kΩ pull-down resistor is required from pin 1 to –vs (see Figure 7). The additional current through the pull-down resistor reduces the op amp's output impedance, improving its transient response.

Decoupling and Grounding

It is good engineering practice to use bypass capacitors on the supply voltage pins and insert small value resistors (10Ω to 100Ω) in the supply lines to provide a measure of decoupling between circuits in the system. A 0.1µf to 1.0µf ceramic capacitor should be used between the supply voltage pin and the analog signal ground for proper bypassing on the AD650.

Also, larger board-level decoupling capacitors of 1µF to 10µF should be placed relatively close to the AD650 on each supply line. This precaution is essential in high-resolution data acquisition applications, where one expects to take advantage of the full linearity and dynamic range of the AD650. While some types of circuits work satisfactorily with only one location of power supply decoupling per board, this practice is strongly discouraged in high-precision analog designs.

Separate digital and analog grounds are provided on the AD650. The emitter of the open collector frequency output transistor is the only node that returns to digital ground. All other signals refer to analog ground. The purpose of the two separate grounds is to allow isolation between the high-precision analog signal and the digital portion of the circuit. On digital ground, noise up to a few hundred millivolts can be tolerated without compromising VFC accuracy. This ground noise is unavoidable when switching large currents associated with frequency output signals.

At 1 MHz full scale, it is necessary to use a pull-up resistor of about 500 ohms to get a fast enough rise time to provide a well-defined output pulse. This means, for example, from a 5V logic supply, the open collector output will draw 10mA.

Due to the self-inductance of the wire, such a high current switch will definitely cause ringing when running long distances to ground. For example, a 20-gauge wire has an inductance of about 20 mA per inch; switching 10 mA at 50 mA at the end of a 12-inch 20-gauge wire will produce a 50-mV voltage spike. The separate digital ground of the AD650 will easily handle these types of switching transients.

Interference due to the radiation of electromagnetic energy from these fast transients will remain a problem. Typically, voltage spikes are produced by inductive switching transients; these spikes can capacitively couple to other parts of the circuit. Another problem is the ringing of the ground and power lines due to the distributed capacitance and inductance of the wires. This ringing can also couple disturbances into sensitive analog circuits. The best way to solve these problems is to properly bypass the logic power supply in the AD650 package.

A 1 μf to 10 μf tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to digital ground pin 10. The pull-up resistor should be connected directly to the frequency output pin 8. Lead lengths on bypass capacitors and pull-up resistors should be kept as short as possible. The capacitor will source (or sink) the current transient, and the large AC signal will flow in a physically small loop through the capacitor, pull-up resistor, and frequency output transistor. It is important that the physical size of the loop is small for two reasons: first, if the wire is shorted, the self-inductance will be reduced, and second, the loop will not radiate rfi effectively.

Digital ground (pin 10) should be connected separately to power ground. Note that the wires to the digital power supply carry only DC current and cannot radiate RFI. There may also be a DC ground drop due to different currents returned on the analog and digital grounds. This will not cause any problems. In fact, the AD650 can withstand DC potential differences of up to 0.25 volts between analog and digital grounds. These features greatly simplify power distribution and ground management for large systems. Proper grounding techniques require that the digital and analog grounds be returned to the power supply separately. Additionally, the signal ground must be directly referenced to the analog ground (pin 11) on the component. All signal grounds should be connected directly to pin 11, especially the one-shot capacitors.

Temperature Coefficient

The drift specification for the AD650 does not include any supporting resistor or capacitor temperature effects. The drift of the input resistors r1 and r3 and the timing capacitor cos directly affects the overall temperature stability. In the application of Figure 2, a 10 ppm/°C input resistor used with a 100 ppm/°C capacitor could result in a maximum overall circuit gain drift: 150 ppm/°C (AD650A) + 100 ppm/°C (COS) + 10 ppm /°C (RIN) 260 ppm/°C

In a bipolar configuration, the drift of the 1.24 kΩ resistor used to activate the internal bipolar bias current source will directly affect the value of this current. This resistor should match the resistor connected to the op amp's non-converting input (pin 2), see Figure 4. That is, the temperature coefficients of the two resistors should be equal. If this is the case, the effects of the temperature coefficients of the resistors cancel each other out and the resulting drift in the offset voltage at the op amp's non-converting input will be determined by the ad650 only. Under these conditions, the tc of the bipolar bias voltage is typically –200 ppm/°C, with a maximum of –300 ppm/°C. The bias voltage always decreases with increasing temperature.

The other circuit components do not directly affect the accuracy of the VFC over-temperature variation, as long as their actual value is not too far from the nominal value, preventing operation. This includes the integrated capacitor, CINT. A change in the value of the CINT capacitance will only result in a different rate of change of the voltage across the capacitor. During the integration phase (see Figure 2), the rate of change of the voltage on CINT is reversed from the reset phase.

1. "Noise Reduction Technology in Electronic Systems", by HWOtt,

Tolerance via drift or CINT. The net effect of the change in the integrator capacitor is simply to change the peak-to-peak amplitude of the sawtooth wave at the integrator output.

The gain temperature coefficient of the AD650 is not a constant value. Instead, the gain, tc, is a function of full-scale frequency and ambient temperature. At low full-scale frequencies, the gain tc is primarily determined by the stability of the internal reference (buried Zener reference). This low-speed gain tc can be quite good; at 10 kHz full scale, the gain tc near 25°C is typically 0±50 ppm/°C. Although the gain tc varies with ambient temperature (trending positive at higher temperatures), the drift remains within a ±75 ppm/°C window over the entire military temperature range. At full-scale frequencies above 10kHz, the dynamic error is more important than the static drift of the DC reference. At full-scale frequencies of 100 kHz and above, these timing errors control the gain, tc. For example, at a full-scale frequency of 100 kHz (Rin = 40 K and Cos = 330 pF), the gain Tc near room temperature is typically -80 ± 50 ppm/°C, but at an ambient temperature near +125°C, the gain Tc It tends to be more positive, usually +15±50 ppm/°C. This information is shown graphically in Figure 8. At higher temperatures, the gain tc always tends to be positive. Therefore, the gain tc of the ad650 can be adjusted by using a one-shot capacitor with an appropriate tc to cancel the drift of the circuit. For example, consider a full-scale frequency of 100 kHz. The average drift of -100ppm/°C means that as the temperature increases, the circuit will produce a lower frequency response to a given input voltage. This means that as temperature increases, the value of the one-shot capacitor must decrease to compensate for the AD650's gain Tc; that is, the capacitor's Tc must be -100 ppm/°C. Now consider a 1 MHz full-scale frequency.

Unless the expected ambient temperature range is known, it is not possible to achieve much improvement in performance. For example, in a constant low temperature application, such as collecting data in an arctic climate (approximately -20°C), a cos drift of -310 ppm/°C is required to compensate for the AD650's gain drift. However, if the ambient temperature of this circuit should be +75°C, the cos cap changes the gain tc from about 0 ppm to +310 ppm/°C.

The temperature effects of the above components are the same when the AD650 is configured for negative or bipolar input voltage and f/v conversion.

Nonlinear specification

The linearity error of the AD650 is specified by the endpoint method. That is, the error is expressed as the deviation from the ideal voltage-to-frequency conversion relationship after calibrating the converter at full scale and "zero". Nonlinearity will vary with the choice of one-shot capacitor and input resistance (see Figure 3). Verification of the linearity specification requires the availability of a switchable voltage source (or DAC) with a linearity error of less than 20ppm, and the use of very long measurement intervals to minimize counting uncertainty. Each ad650 is automatically tested for linearity, and this verification is usually not required, which is tedious and time-consuming. If non-linear testing is required, either as part of incoming quality screening or as part of final product evaluation, an automated "benchtop" tester will prove useful. Such a system based on the lts-2010 of an analog device is described in reference 2.

Figure 9 shows the voltage-to-frequency conversion relationship, with the nonlinearity exaggerated for clarity. The first step in determining the nonlinearity is to connect Figure 9b. Amplify the nonlinearity with a straight line over the 1 MHz full-scale operating range (typically 10 mV and 10 V). This straight line is the ideal relationship required by the circuit. The second step is to find the difference between this line and the actual response of the circuit at a few points between the endpoints, usually ten intermediate points are enough. The difference between the actual response and the ideal response is the frequency error measured in Hertz. Finally, these frequency errors are normalized to full-scale frequency and expressed as parts per million of full scale (ppm) or hundredths of full scale (%). For example, at full 100 kHz

2. "V–F Converters Need Accurate Linearity Tests," by L. Devito (Electronic Design, March 4, 1982).

Scale, if the maximum frequency error is 5 Hz, the nonlinearity will be specified as 50 ppm or 0.005%. Typically on the 100 kHz scale, the nonlinearity is positive, with a maximum appearing at about mid-scale (Fig. 9a). At higher full-scale frequencies (500 kHz to 1 MHz), the nonlinearity becomes "S" shaped and the maximum value can be positive or negative. Typically, on the 1 MHz scale (rin = 16.9k, cos = 51 pf), the nonlinearity is positive below about 2/3 of the scale and negative above that point. As shown in Figure 9b.

PSRR

The power supply rejection ratio is a specification of the gain of the ad650 as the power supply voltage changes. psrr is expressed in parts per million, ppm/% per percent gain change of the power supply. For example, consider a VFC with an input voltage of 10 volts and an output frequency of 100 kHz when the supply voltage is ±15 volts. Changing the supply voltage to ±12.5V is a 5V change between 30V or 16.7%. If the output frequency changes to 99.9khz, the gain change is 0.1% or 1000ppm. psrr is 1000 ppm divided by 16.7%, which equals 60 ppm/%.

The PSRR of the AD650 is a function of the full-scale operating frequency. At low full-scale frequencies, psrr is determined by the stability of the reference circuit in the device and can be very good. At higher frequencies, the dynamic error is more important than the static reference signal, so the psrr is not as good. At 10 kHz full-scale frequency (RIN = 40 K, COS = 3300 pF), the PSRR value is typically 0 ± 20 ppm/%. At 100 kHz (RIN=40K, COS=330 pF), PSRR is typically +80±40 ppm/%; at 1 MHz (RIN=16.9 kΩ, COS=51 pF), PSRR is +350±50 ppm/% %. Figure 10 summarizes this information graphically.

Additional Circuit Considerations

The input amplifiers connected to pins 1, 2 and 3 are not standard op amps. Instead, the design has been optimized for simplicity and high speed. The biggest difference between this amplifier and a normal op amp is the lack of an integrator (or level-shifting) stage. So the voltage on the output (pin 1) must always be higher than 2 volts on the input (pins 2 and 3). For example, in F-to-V conversion mode, see Figure 6, the non-vertical input (pin 2) of the op amp is grounded, which means that the output (pin 1) in the figure will not be able to demand a negative voltage at the output, But it is conceivable to require a bipolar output voltage (say ±10 volts) by connecting an extra R. Resistor from pin 3 to positive voltage. this will not work.

Caution should be exercised in the presence of high positive input voltages at or before power-up. These conditions can cause the integrator output (pin 1) to lock up. This is a lossless latch, so normal operation can be resumed by cycling the power. As shown in Figure 4, latching can be prevented by connecting two diodes (eg 1N914 or 1N4148), preventing pin 1 from swinging under pin 2.

The second major difference is that the output will only drop 1mA from the negative supply. Apart from a 1mA current source for v-to-f conversion, there is no pull-down stage at the output. The op amp will draw a lot of current from the positive supply, and it is internally protected by current limiting. When the op amp is not supplying external current, its output can be driven to within 3 volts of the positive supply. When the supply is 10mA, the output voltage can be driven to within 6V of the positive supply.

The third difference between this op amp and the normal device is that the inverting input pin 3 is bias current compensated, while the non-bias input is not bias current compensated. The bias current at the inverting input is nominally zero, but can be as high as 20mA in either direction. Non-vertical inputs typically have a 40mA bias current that always flows into the node (npn input transistor). Therefore, it is not possible to match the input voltage drop caused by the bias current by matching the input resistance.

Operational amplifiers have means to adjust the input bias voltage. The 20 kΩ potentiometer is connected to pins 13 and 14, and the wiper is connected to the positive power supply through a 250 kΩ resistor. A potential of about 0.6 volts is established through a 250 kΩ resistor and 3 μA of current is injected into the zero pin. It is also possible to make the op amp offset voltage zero by using only one zero pin and using a bipolar current input or output zero pin. The amount of current required will be very small, typically less than 3 microamps. This technique is shown in the Applications section of this datasheet: Auto-zero circuits use this technique.

Bipolar bias current is activated by connecting a 1.24 kΩ resistor between pin 4 and the negative supply. The combined current output to the non-vertical input of the op amp is nominally 0.5 mA with a tolerance of ±10%. This current is then used to provide the offset voltage when pin 2 is connected to ground through a resistor. The 0.5 mA appearing on pin 2 also flows through the 1.24 kΩ resistor, this current can be obtained by looking at the voltage across the 1.24 kΩ resistor. External resistors are used to activate the bipolar bias current source to provide the lowest tolerance and temperature drift of the resulting bias voltage. Other resistor values between pin 4 and –vs can be used to obtain bipolar bias currents other than 0.5mA. FIG. 11 is a graph of the relationship between bipolar bias current and resistor value used to activate the power supply.

Applications of Differential Voltage-Frequency Conversion

The circuit of Figure 12 accepts a true floating differential input signal. The common mode input VCM may be in the range of +15 to -5 volts with respect to analog ground. The signal input (VIN) may be ±5 volts relative to the common mode input. Both inputs are low impedance: the source driving the common-mode input must provide 0.5 mA from the bipolar bias current source, and the source driving the signal input must provide the integration current.

If a lower common mode voltage range is required, a zener can be used for lower voltages. For example, if a 5 volt zener is used, the VCM input may be in the +10 to -5 volt range. If the zener is not used at all, the common mode range is ±5 volts relative to analog ground. If the zener is not used, the 10k pull-down resistor is not needed and the integrator output (pin 1) is connected directly to the comparator input (pin 9).

Auto-zero circuit

To fully utilize the dynamic range of the AD650 VFC, very small input voltages need to be converted. For example, a 60-year dynamic range based on 10-volt full-scale requires accurate measurement of signals down to 10 microvolts. In these constant bias voltages, dynamic range is not affected, but all frequency readings are just shifted by a few Hz. However, if the offset should change, then it is impossible to distinguish small changes in the input voltage from drifts in the offset voltage. Therefore, the available dynamic range is smaller. The circuit shown in Figure 13 provides automatic adjustment of the op amp bias voltage. The circuit uses an AD582 sample-and-hold amplifier to control the offset, and the input voltage to the VFC is switched between ground and the signal under test via an AD7512DI analog switch. The offset of the AD650 is adjusted by injecting current into or out of pin 13. Note that only one offset null is used. In "VFC norm" mode, the SHA is in hold mode with a very large hold capacitor, 0.1µF, to keep the AD650 offset constant for a long time.

When the circuit is in "auto-zero" mode, the SHA is in sampling mode and behaves as an op amp. This circuit is a variation of the classic two-amp servo loop, where the output of the device under test (DUT) - here the DUT is the AD650 op-amp is forced to ground through the feedback action of the control amplifier SHA. Since the input of the VFC circuit is grounded in auto-zero mode, the input current that can flow is determined by the bias voltage of the AD650 op amp. Since the output of the integrator stage is forced to ground, the voltage is known to be unchanged (equal to ground potential). Therefore, if the output of the integrator is constant, its input current must be zero, so the offset voltage is forced to zero. Note that the output of the DUT may be forced to any convenient voltage other than ground. All it takes is to know that the output voltage is constant. Also note that in this circuit the effect of the bias current at the inverting input of the ad650 op amp is also zero. The 1000 pf capacitor shunting the 200 kΩ resistor is the compensation for the two amplifier servo loops. Two integrators in a loop need a zero for compensation. Note that the 3.6 kΩ resistor from pin 1 of the AD650 to the negative supply is not part of the autozero circuit, but rather the resistor required for VFC operation at 1 MHz.

PLL f/v conversion

Although the f/v conversion technique shown in Figure 6 is very accurate, using only a few additional components, it is very limited in terms of signal frequency response and carrier feedthrough. If the carrier (or input) frequency changes instantaneously, the output cannot change quickly due to the integrator time constant formed by cint and rin. While the integrator time constant can be reduced to provide faster f-to-v settling of the output voltage, the carrier feedthrough will be larger. For signal frequency response over 2kHz, the phase-locked f/v conversion technique shown in Figure 14 is recommended.

In a phase locked loop circuit, the oscillator is driven to the same frequency and phase as the input reference signal. In applications such as synthesizers, the oscillator output frequency is first processed by a programmable "divide by n" and then applied as feedback to the phase detector. Here, the oscillator frequency is forced to be "n times" the reference frequency, and this frequency output is the desired output signal, not a voltage. In this case, the AD650 offers compact size and wide dynamic range.

In a signal recovery application of pll, the desired output signal is the voltage applied to the oscillator. In these cases a linear relationship between input frequency and output voltage is required; the AD650 makes an excellent oscillator for fm demodulation. The wide dynamic range and excellent linearity of the AD650 VFC allow simple implementation of high performance analog signal isolation or telemetry systems. The circuit shown in Figure 14 uses a digital phase detector to provide proper feedback even if the frequencies are not equal. This phase frequency detector (pfd) is available in integrated form.

Analysis of this circuit must begin with the 7474 dual D flip-flop. When the input carrier matches the output carrier in both phase and frequency, the q output of the flip-flop will rise simultaneously. Using two zeros and then two ones at the input of the exclusive-or (xor) gate will keep the output low while keeping the dmos off. Additionally, the nand gate resets the flip-flop to zero. During the entire cycle just described, the dmos integrator gate remains closed so that the voltage at the integrator output remains unchanged from the previous cycle. However, if the input carrier and the output carrier differ by a few degrees, the xor gate will be opened for a small time span when the two signals do not match. Since q2 will be low during the mismatch period, a negative current will be fed into the integrator causing its output voltage to rise. This in turn will slightly increase the frequency of the ad650, thus driving the system towards sync. In a similar fashion, if the input carrier lags the output carrier, the integrator will be forced down slightly to synchronize the two signals. Using mathematical methods, the ±25 μA pulses from the phase detector are incorporated into the phase detector gain kd.

Also, the v/f converter is configured to produce 1 MHz in response to a 10 volt input, so its gain ko is:

The dynamics of the phase relationship between the input and output signals can be described as a second-order system with a natural frequency ω:

and damping coefficient:

For the values shown in Figure 14, these relationships simplify to a natural frequency of 35 kHz with a damping factor of 0.8.

For those who want an easy way to determine the component values of other pll frequencies and vfc full scale voltage, the following recipe steps can be used:

1. Determine ko (in radians/volt-seconds) from the maximum input carrier frequency fmax (Hertz) and the maximum output voltage vmax.

2. Calculate the value of c according to the required loop bandwidth fn. Note that this is the desired frequency range of the output signal. The loop bandwidth (fn) is not the maximum carrier frequency (fmax): it can be very narrow even if the signal is transmitted on a 1 MHz carrier.

3. Calculate R using the following formula, resulting in a damping coefficient of approximately 0.8:

If, in practice, pll overshoots or overshoots before reaching its final value, the damping factor can be increased by increasing the value of r. Conversely, if pll exceeds -damping, a smaller R value should be used.