Features: 35MW max power consumption; 50µW power down mode; 25µs conversion max acquisition; ±1/2LSB max entry and DNL; 72dB min SINAD, 1kHz input; ±10V, 0V to +5V and 0V to +4V enter.

Range: Single-supply +5V operation; parallel and serial data outputs; 16-bit ADS7807 compatible pinout; use internal or external.

References: 28 pin 0.3" plastic dipping and SOIC.

describe

The ADS7806 is a low-power 12-bit sampling similar to digital sampling using state-of-the-art CMOS structures. It contains a complete 12-bit, capacitive-based, SAR a/d with S/H, clock, reference and microprocessor interfaces with parallel and serial output drivers. The ADS7806 can acquire and convert to full 12-bit accuracy up to 25 microseconds with only 35 mW maximum laser trimmed scaling resistors provide standard industrial input ranges of ±10V and 0V to +5V.in addition, 0V to +4V The range allows for complete single supply systems. The 28-pin ADS7806 is dipped in SOIC in 0.3-inch plastic, and both are fully specified for the industrial –40°C to +85°C temperature range.

Basic operation

Parallel output

Figure 1a) shows the basic circuit to operate the ADS7806 with a ±10V input range and parallel outputs. Driving R/C (pin 22) low for 40 ns (12 µs max) will start the converter - Zion. BUSY (pin 24) will go low and remain low until the conversion is complete and the output registers are updated. If byte (pin 21) is low, the 8 most significant bits will be valid when busy is rising; if byte is high, the 4 least significant bits will be valid when busy is rising. Data will be output in binary 2's complement format. Busy high can be used to lock data. After the first byte is read, the bytes can be toggled to allow the remaining bytes to be read. When busy is low.

The ADS7806 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals. Offset and gain are adjusted internally to allow external single-supply trimming. External resistors compensate for this adjustment, if offset gain will be corrected in software (see Calibration section).

Serial output

Figure 1b) shows the basic circuit to operate the ADS7806 with a ±10V input range and serial output. Setting R/C (pin 22) low for 40ns (12 microseconds max) will initiate a conversion and output valid data from the previous conversion on SData (pin 19), synchronized to 12 clock pulses of the data clock (pin 19). foot 18). BUSY (pin 24) will go low and remain low until the conversion is complete and serial data has been transferred. Data will be output in binary 2's complement format, msb first, and on the rising and falling edges of the data clock. Busy high can be used to lock data. All conversion commands will be ignored while busy.

The ADS7806 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

Offset and gain are adjusted internally to allow external trimming using a single supply. External resistors compensate for this adjustment, and can be ignored if offset and gain are corrected in software.

Begin converting the combination of CS (Pin 23) and R/C (Pin 22) for a minimum of 40ns, immediately putting the ADS7806 in hold and begin converting "n". busy (pin 24) will go low and remain low until conversion "n" is complete and the internal output registers have been updated. All new conversion commands during busy low period will be ignored. cs and/or r/c must go high before busy goes high, otherwise a new conversion will be started without enough time to acquire a new signal.

The ADS7806 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

CS and R/C are triggered internally or horizontally. When initiating a conversion, there is no requirement for the input to go low first. However, if CS or R/C initiates transition "n", make sure the lower critical input is at least 10ns before initiating the input. If EXT/INT table 3. Control function when using parallel output (dataclk low-order binding, ext/int high-order binding).

(pin 8) is low when conversion "n" is initiated, serial data for conversion "n-1" will be output to SData (pin 19) after conversion "n" begins. See Internal Data Clock in the Read Data section. To reduce the number of control pins, r/c can be used to control read and transition modes by placing the CS system in a lower position. This will not work when using the internal data clock in serial output mode. However, the parallel output and serial output (only when using an external data clock) will

Affected when R/C rises.

read data

The ADS7806 outputs serial or parallel data in straight binary or binary 2's complement data output format. If SB/BTC (pin 7) is high, the output is in SB format, if low, the output is in BTC format. The parallel outputs can be read without affecting the internal output registers; however, a serial read of the data port will cause the internal output registers to shift one bit per data clock pulse. Therefore, data can be read on the parallel port until the same data on the serial port is read, but data cannot be read through the serial port until the same data on the parallel port is read.

Parallel Output To use the parallel output, connect Ext/Int (pin 8) to High and DataClk (pin 18) to Low. SData (pin 19) should be left unconnected. The parallel output will activate when R/C (Pin 22) is high and CS (Pin 23) is low. Any other combination of CS and R/C will tri-state the parallel outputs. Valid conversion data can be read as two 8-bit bytes on D7D0 (pins 9-13 and 15-17). When the byte (pin 21) is low, the 8 most significant bits are valid for the msb on D7. When byte is high, the 4 least significant bits are valid for lsb on d4. Bytes can be switched to read two bytes in one conversion cycle.

On initial power-up, the parallel outputs will contain indeterminate data.

Parallel output (after conversion)

Busy (pin 24) will go high after conversion "n" is complete and the output register has been updated. Valid data for transition 'n' will be available on D7-d0 (pins 9-13 and 15-17). Busy high can be used to lock data.

Parallel output (during conversion)

After starting conversion "n", valid data in conversion "n-1" can be read and valid for 12 microseconds after conversion "n" starts. Do not attempt to read data more than 12 microseconds after transition "n" begins until busy (pin 24) goes high; this may result in invalid data being read. See Table VI and Figures 2 and 3 for timing constraints.

Serial output

Data can pass through the internal data clock or an external data clock. When using serial outputs, be careful with parallel outputs D7-d0 (pins 9-13 and 15-17) as when CS (pin 23) these pins will come out of HI-Z state.

Internal data clock (during conversion)

To use the internal data clock, drive Ext/Int (pin 8) low. A combination of R/C (Pin 22) and CS (Pin 23) low will initiate conversion 'N' and activate the internal data clock (typically 900kHz clock frequency). The ADS7806 will output 12 valid data bits from the transition 'n-1' on SData (pin 19) to the 12 clock pulses clocked out on dataclk (pin 18), msb first. Data is valid on both the rising and falling edges of the internal data clock. The rising busy edge (pin 24) can be used to lock data. After the 12th clock pulse, dataclk will remain low until the next conversion starts, and sdata will go to whatever logic level was input on the tag (pin 20) during the first clock pulse.

External data clock

To use an external data clock, connect Ext/Int (pin 8) high. The external data clock is not a conversion clock and can only be used as a data clock. output mode enabled

ADS7806, CS (pin 23) must be low and R/C (pin 22) must be high. dataclk must be up to 20% to 70% of the total data clock period; the clock frequency can be between dc and 10mhz. Serial data from transition 'n' can be output on sdata (pin 19) after transition 'n' is complete or during transition 'n+1'.

An obvious way to simplify converter control is to cs low and use r/c to start the conversion. While this is perfectly acceptable, problems can arise when using an external data clock. at the 12 microsecond uncertainty point. After conversion 'n' starts until busy rises, the internal logic converts the result of conversion 'n' to the output register. If CS is low and R/C is high, if the external clock is high at this time, data will be lost. Therefore, with cs low, r/c and/or dataclk must be low during this period to avoid loss of valid data.

External data clock (after conversion)

After conversion "n" is complete, the output register has been updated and busy (pin 24) will go high. With CS low and R/C high, valid data from transition 'N' will be output on SData (pin 19), synchronized to the external data clock input on DataCLK (pin 18). msb is valid on the first falling edge and second rising edge of the external data clock. The LSB is valid on the 12th falling edge and the 13th rising edge of the data clock. The tag (pin 20) will input one bit of data per external clock pulse. The first bit input on the label will be valid on SData on the 13th falling edge and 14th rising edge of data CLK; the second bit input will be valid on the 14th falling edge and 15th rising edge of data CLK, etc. Under continuous data clock, the tag data will be output on SData until the internal output register is updated according to the result of the next conv.

External data clock (during conversion)

After starting conversion "n", valid data in conversion "n-1" can be read and valid for 12 microseconds after conversion "n" starts. Data rising from 12 microseconds after the start of conversion "n" to busy (pin 24); this will result in a loss of data. Note: For best performance when using an external data clock, data should not be clocked during conversion. Switching noise from asynchronous data clocks can cause digital feedthrough and degrade converter performance.

Label Features

Tag (pin 20) input serial data synchronized to external or internal data clock. When using an external data clock, the serial bitstream input on the tag will follow the lsb output on sdata until the internal output register is updated with the new conversion result. After all 12-bit valid data are output, the logic level input on the label of the first rising edge of the internal data clock is valid on SData.

input range

The ADS7806 offers three input ranges: standard ±10V and 0-5V, and a 0-4V range for complete single-supply systems. Figures 7a and 7b show the circuit connections required to implement each input range and optional offset and gain adjustment circuits. Offset and full-scale error (1) specifications are tested and guaranteed with the fixed resistors shown in Figure 7b. Adjustments for offset and gain are described in the calibration section of this datasheet.

Offset and gain are adjusted internally to allow external trimming using a single supply. An external resistor compensates for this adjustment, which is negligible if the offset and gain are corrected in software (see the Calibration section). The input impedance is summarized in Table 2, which is a combination of the internal resistor network and external resistors shown on the first page of the product data sheet

Note: (1), Full-scale error includes offset and gain errors measured at +fs and -fs. for each input range (see Figure 8). The input resistor divider network provides inherent overvoltage protection, guaranteed to be at least ±25V. An analog input above or below the expected range will produce a positive full-scale or negative full-scale digital output, respectively. For analog inputs beyond the nominal range, no wrapping or folding will occur.

calibration

hardware calibration

To calibrate the offset and gain of the ADS7806 in hardware, install the resistors shown in Figure 7A. Table VII lists the hardware trim ranges for each input range relative to the input.

The resistors shown in Figure 7b are necessary for compensation and gain. See the No Calibration section for more details on external resistors. Refer to Table 8 for offset and gain error ranges with and without external resistors.

Note that the actual voltage drop across the external resistor is at least two orders of magnitude lower than the voltage across the internal resistor divider network. This should be taken into consideration - when choosing the accuracy and drift specifications of the external resistors. In most applications, a 1% metal film resistor is sufficient.

In some applications, the external resistor shown in Figure 7b may not be necessary. These resistors provide compensated internally trimmed offset and gain, allowing calibration with a single power supply. Not using external resistors will result in offset and gain errors, as well as those listed in the Electrical Specifications section. Offset is the equivalent voltage of the digital output when the input is grounded. Positive gain error occurs when the equivalent output voltage of the digital output is greater than the analog input. Refer to Table 8 for the nominal ranges of gain and offset errors with or without external resistors. See Figure 8 for a typical change in transfer function when the external resistor is removed.

To further analyze the effect of removing any combination of external resistors, consider Figure 9. The combination of external and internal resistors form a voltage divider that reduces the input signal at the cdac to an input range of 0.3125v to 2.8125v. Internal resistors are laser trimmed to high relative accuracy to meet full specifications. However, due to process variations, the actual input impedance of the internal resistor network (look at pin 1 or pin 3) is only accurate to ±20%. This should be taken into account when determining the effect of removing external resistors.

references

The ADS7806 can operate with its internal 2.5V reference or an external reference. The internal reference can be bypassed by applying an external reference to pin 5; connecting REFD (pin 26) high will turn off the internal reference, reducing the total power dissipation of the ADS7806 by about 5 mW.

The internal reference has a drift of about 8 ppm/°C (typical), which accounts for about 20% of the full-scale error (fse=?0.5% for low-scale, fse=?0.25% for high-scale).

The ADS7806 also has an internal reference voltage buffer. See Figure 10 for the characteristic impedance of the buffer input and output under all power-down and reference voltage reduction conditions.

referee

REF (Pin 5) is the input for the external reference or the output for the internal 2.5V reference. The 2.2µf tantalum capacitor should be placed as close to the reference pin from ground as possible. This capacitor and ref's output resistance create a low-pass filter on the reference to limit noise. Using a smaller capacitor value will introduce more noise to the reference signal, reducing the SNR and SNR. The REF pin should not be used to drive external AC or DC loads. See Figure 10.

The external reference is in the range of 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage can increase the full-scale and lsb size of the converter, thereby improving the signal-to-noise ratio.

CAP

CAP (pin 4) is the output of the internal reference buffer. The 2.2µf tantalum capacitor should be placed as close as possible to the grounded cap pin to provide the best switching current for the cdac throughout the conversion cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor smaller than 1µF can cause the output buffer to oscillate and there may not be enough charge available for the cdac. Capacitance values greater than 2.2µf have little effect on improving performance. See Figures 10 and 11.

The output of the buffer is capable of driving up to 1 mA into a DC load. Using an external buffer will allow the internal reference to be used for larger DC and AC loads. Do not attempt to directly drive an AC load whose output voltage is capped. This will result in reduced converter performance.

Reference and power outages

The ADS7806 has analog power-down and reference power-down functions via PWRD (pin 25) and REFD (pin 26), respectively. pwrd and refd high will shut down all analog circuits holding previously converted data in internal registers, provided the data has not been shifted out through the serial port. Typical power consumption in this mode is 50 microwatts. With a 2.2 microF capacitor connected to the capacitor, power recovery is typically 1 ms. See Figure 11 for power-up recovery times for capacitor values. When +5V is applied to VDIG, the digital circuitry of the ADS7806 remains active regardless of PWRD and REFD states.

pressurized water reactor

PWRD high will turn off all analog circuits except the reference. The previously converted data will be kept in the internal registers and can still be read. For pwrd high, the convert command produces meaningless data.

Reid

REFD high will turn off the internal 2.5V reference voltage. All other analog circuits, including the reference buffer, will be activated. When using an external reference, refd should be high to minimize power consumption and loading effects on the external reference. The characteristic impedance (high and low) of the reference buffer input is shown in Figure 10. The internal reference consumes about 5 MW.

layout

power

For best performance, connect the analog and digital power pins to the same +5V supply, and connect the analog and digital grounds together. As stated in the electrical specifications, the ADS7806 uses 90% of its power for analog circuits. The ADS7806 should be considered an analog component.

The +5V supply for the A/D should be separate from the +5V supply used for the system's digital logic. Connecting vdig (pin 28) directly to the digital supply can degrade converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be generated from any analog supply used for analog signal conditioning. A simple +5V regulator can be used if a +12V or +15V supply is present. While it is not recommended to use a digital power supply to power the converter, make sure the power supply is properly filtered. Whether using a filtered digital supply or a regulated analog supply, VDIG and VANA should be connected to the same +5V supply.

ground

There are three ground pins on the ADS7806. DGND is the digital power ground. agnd2 is the analog power ground. agnd1 is the ground to which all a/d's internal analog signals are referenced. agnd1 is more susceptible to current induced voltage drops and must have a minimal resistive path back to the power supply.

All ground pins of the A/D should be tied to the analog ground plane and separated from the system's digital logic ground for best performance. Both analog and digital ground planes should be connected to the "system" ground as close to the power supply as possible. This helps prevent dynamic digital ground currents from modulating analog ground to power ground through the common impedance.

signal conditioning

In many cmos a/d converters, the fet switch used for sample and hold releases a large amount of charge injection, which causes the drive op amp to oscillate. The charge injection due to sampling FET switching on the ADS7806 is approximately 5-10% of the charge injection on a similar ADC with a charge redistribution DAC (CDAC) structure. There is also a resistive front end that attenuates any charge released. The end result is a minimum requirement for the drive capability of the signal conditioning prior to A/D. In the application, any op amp large enough to drive the signal is sufficient to drive the ADS7806.

The resistive front end of the ADS7806 also provides guaranteed ±25V overvoltage protection. In most cases, this eliminates the need for an external overvoltage protection circuit.

middle latch

The ADS7806 has tri-stated outputs for the parallel port, but if the bus is active during conversion, an intermediate latch should be used. The tri-state output can be used to isolate the A/D from other peripherals on the same bus if the bus is not active during the conversion process.

The intermediate latch is good for any monolithic a/d converter. The ADS7806 has an internal LSB size of 610µV. Transients resulting from fast switching signals on the parallel port, even when the A/D is tri-stated, can couple through the substrate to the analog circuitry, resulting in degraded converter performance. The effect of this phenomenon will be more pronounced when using the pin-compatible ADS7807 or any other 16-bit converter in the ADS family. This is because the internal LSB size is small at 38µV.

application information

qspi interface

Figure 12 shows a simple interface between the ADS7806 and any Qspi-equipped microcontroller. This interface assumes that the conversion pulses do not come from the microcontroller and that the ADS7806 is the only serial peripheral.

Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. When a low-to-high transition of the slave select (SS) occurs, starting from busy (indicating the end of the current transition), the port can be enabled. If this is not done, the microcontroller sum and A/D may be "out of sync".

Figure 13 shows another interface between the ADS7806 and a Qspi-equipped microcontroller. This interface allows the microcontroller to provide transition pulses, while also allowing multiple peripherals to be connected to the serial bus. This interface and the following discussion assume that the master clock of the QSPI interface is 16.78MHz. Note that the serial data input of the microcontroller is connected to the msb (d7) of the ADS7806, not the serial output (sdata). Using D7 in place of the serial port provides tri-state functionality, allowing other peripherals to be connected to the MISO pin. When communication with these peripherals is required, pcs0 and pcs1 should be held high; this will keep the d7 tri state and prevent transitions from occurring.

In this configuration, the QSPI interface is actually set up to perform two different serial transfers. The first, an 8-bit transfer, makes pcs0(r/c) and pcs1(cs) go low at the start of conversion. The second, a 12-bit transfer, just causes PCS1 (CS) to be turned down. Valid data will be transmitted at this time.

For both transfers, the dt register (post-transfer delay) is used to cause a delay of 19 microseconds. The interface is also set to wrap to the beginning of the queue. In this way, QSPI is a state machine that generates proper timing for the ads7806. Therefore, the timing is locked to the crystal-based timing of the microcontroller, rather than the interrupt drive. Therefore, the interface is suitable for both AC and DC measurements.

For fastest conversion rate, baud rate should be set to 2 (4.19MHz SCK), dt to 10, first serial transfer to 8 bits, second to 12 bits, dsck disabled (in command control bytes). This will allow a maximum conversion rate of 23 kHz. For slower rates, dt should be increased. Do not slow down SCK, as this may increase the chance of affecting the conversion result or inadvertently starting a second conversion during the first 8-bit transfer.

Also, cpol and cpha should be set to zero (sck is usually low and data is captured on the rising edge). The command-control byte for 8-bit transfers should be set to 20 hours, and the command-control byte for 12-bit transfers should be set to 61 hours.

SPI interface

The spi interface is usually only capable of 8-bit data transfer. For some microcontrollers with a spi interface, data may be received in a similar way, as shown in Figure 12 for the qspi interface. The microcontroller needs to fetch the 8 most significant bits before the content is overwritten by the least significant bits.

A modified version of the QSPI interface shown in Figure 13 may be possible. For most microcontrollers with a spi interface, automatic generation of transition pulses is not possible and must be done in software. This will limit the interface for "DC" applications due to insufficient jitter performance of the switching pulse itself.

DSP56000 interface

The DSP56000 serial interface has an SPI compatible mode and some enhancements. Figure 14 shows the interface between the ADS7806 and the DSP56000, which is very similar to the Qspi interface in Figure 12. As mentioned in the QSPI section, the dsp56000 must be programmed to observe a transition on SC1 from low to high (busy high at the end of the transition).

As shown in Figure 15, the DSP56000 can also provide switching pulses by including a monostable multivibrator. The receive and transmit parts of the interface are separated (asynchronous mode), and the transmit part is set to generate word-length frame sync every other transmit frame (frame rate allocator set to 2). The prescaler modulus should be set to 5.

The monostable multivibrator in this circuit will provide different pulse widths for the conversion pulses. The pulse width will be determined by the external R and C values used by the multivibrator. The 74HCT123N datasheet says the pulse width is (0.7)rc. Choosing a pulse width close to the minimum specified in this data sheet will provide the best performance. The maximum conversion rate of the 20.48MHz DSP56000 is 35.6kHz. If a slower oscillator can be tolerated on the dsp56000, a slew rate of 40khz can be achieved by using a 19.2mhz clock and a prescaled modulo of 4.