Features Zilog Z80 CPU Compatible Code Expansion Description Two Chained DMA Channels Low Power Modes On-Chip Interrupt Controller Three On-Chip Wait State Generators On-Chip Oscillator/Generator Extended MMU Addressing (up to 1 MB)
Clock Serial I/O Ports General Description The enhanced Z80180/Z8S180/Z8L180 significantly improves upon previous Z80180 models while being fully backward compatible with existing Zilog Z80 devices. Z80180/Z8S180/Z8L180 now offer faster execution speed, power saving mode and EMI noise reduction. Footprint This enhanced Z180 design also includes additional feature enhancements for ASCIS, DMA and iStandby mode power consumption. With the addition of an "escc-like" baud rate generator (brg), the two asci now have the flexibility and ability to transmit data asynchronously at rates up to 512kbps. Additionally, the asci receiver adds a 4-byte first-in, first-out (fifo) that can be used to buffer incoming data to reduce the incidence of overflow errors. DMA has been modified to allow "chaining" of two DMA channels when set up to receive their DMA requests from the same peripheral device. This feature allows uninterrupted DMA operations between two DMA channels, reducing the amount of CPU intervention.

Z80180/Z8S180/Z8L180 SL1919 Enhanced Z180 Microprocessor Two 16-bit Counter/Timers Two Enhanced UARTs (up to 512 Kbps)
Clock Speeds: 6, 8, 10, 20, 33 MHz
Operating range: 5V (3.3V@20MHz)
Operating temperature range: 0C to + 70C °°
Extended Temperature Range - 40C to +85C°°
Three package styles – 68-pin PLCC
– 64-pin dipping – 80-pin QFP
The Z80180/Z8S180/Z8L180 not only consumes less power than the previous model during normal operation, but also has three modes designed to further reduce power consumption. Zilog reduces I power consumption in standby mode to a minimum of 10 microamps by stopping the external oscillator and internal clock. Sleep mode reduces power consumption by putting the CPU in a "stopped" state, which consumes less current while the on-chip I/O devices are still working. System Stop Mode puts both the CPU and OnChip peripherals into "stop" mode, further reducing power consumption. The duplicated copy implements a new clock multiplication feature in the z80180/z8s180/z8l180 devices, which allows the programmer to double the clock of the internal clock with that of the external clock. This saves system cost by allowing the use of lower cost, lower frequency crystals instead of higher cost and higher speed oscillators.
The enhanced Z180 is packaged in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages.

Pin Description
A0A19 address bus (output, high, tri-state). a0a19 constitutes a 20-bit address bus. The address bus provides addresses for memory data bus exchanges up to 1 MB, and I/O data bus exchanges up to 64 K. The address bus enters a high impedance state during reset and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (T, selected as address output at reset), address line A19 is not available in the DIP version of the Z80180. Out Busack bus acknowledgment (output, active low). /busack indicates that the requesting device, the mpu address and data bus, and some control signals have entered a high impedance state.
BueReq bus request (input, active low). External devices such as DMA controllers use this input to request access to the system bus. This request has higher priority than /nmi and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and places the address and data buses and other control signals in a high impedance state.
CKA0, CKA1. Asynchronous clocks 0 and 1 (bidirectional, active high). When in output mode, these pins are the transmit and receive clock outputs from the ASCI baud rate generator. In input mode, these pins are used as external clock inputs for the ASCI baud rate generator. cka0 is multiplexed with /dreq0, and cka1 is multiplexed with /tend0.
cks. Serial clock (bidirectional, high). This line is the clock for the CSIO channel.
PHI clock. System clock (output, high). The output is used as a reference clock for microprocessors and external systems. The frequency of this output is equal to half the frequency of the crystal or input clock.
/cts0-/cts1. Clear to send 0 and 1 (input, active low). These lines are the modem control signals for the ASCI channel. /CTS1 is multiplexed with RX.
D0-D7. databus = (bidirectional, high, tristate). d0-d7 form an 8-bit bidirectional data bus for transferring information between input/output and storage devices. The data bus enters a high impedance state during reset and external bus acknowledge cycles.
DCD0. Data carrier detect 0 (input, active low). This is the programmable modem control signal for ASCI channel 0.
/Drake, Drake 1. DMA requests 0 and 1 (input, low). /dreq is used to request dma transfers from an on-chip dma channel. The dma channel monitors these inputs to determine when the external device is ready.
for read or write operations. These inputs can be programmed for level or edge sensing. /dreq0 is multiplexed with cka0.
e. Enable clock (output, active high). Synchronizer cycle clock output during bus transactions.
Exstar external clock crystal (input, active high). Crystal oscillator connection. When not using a crystal, an external clock can be input to the Z80180/Z8S180/Z8L180 on this pin. This input is Schmitt triggered.
stop. stop/sleep(output, low). This output is asserted after the CPU executes a HALT or SLP instruction and waits for a non-maskable or maskable interrupt before operation resumes. It is also used in conjunction with the /m1 and st signals to decode the state of the CPU machine cycle.
/in 0. Mask interrupt request 0 (input, low). This signal is generated by an external I/O device. As long as the /nmi and /busreq signals are inactive, the CPU will execute these requests at the end of the current instruction cycle. The CPU acknowledges the interrupt request through an interrupt acknowledgement cycle. During this cycle, both the /m1 and /iorq signals will activate.
/int1, /int2. Masks interrupt requests 1 and 2 (input, low). This signal is generated by an external I/O device. As long as the /nmi, /busreq, and /int0 signals are inactive, the CPU will honor these requests at the end of the current instruction cycle. The CPU will acknowledge these requests with an interrupt acknowledgement cycle. Unlike the acknowledgement of /int0, neither the /m1 nor the /iorq signal will become active during this cycle.
IORQ. I/O request (output, active low, tri-state). /IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. /iorq and /m1 are also generated during the acknowledgement of the /int0 input signal to indicate that the interrupt response vector can be placed on the data bus. This signal is similar to the /IOE signal of the Z64180.
/M1. Machine cycle 1 (output, active low). Along with /mreq, /m1 represents the opcode fetch cycle and instruction execution the current cycle is. Along with /iorq, /m1 indicates that the current cycle is used for interrupt acknowledgement. It is also used in conjunction with the /halt and st signals to decode the state of the CPU machine cycle. This signal is similar to the /LIR signal of the Z64180.
/MREQ. Memory request (output, active low, tristate). /mreq indicates that the address bus reserves valid addresses for memory read or memory write operations. This signal is similar to the /me signal of the z64180.
/NMI. Non-maskable interrupt (input, negative edge triggered). /nmi has higher priority than /int and is always recognized at the end of the instruction, regardless of the state of the interrupt enable trigger. This signal forces the CPU to continue execution at location 0066H.
RD. Recode (output, active low, tristate). /rd indicates that the cpu wants to read data from memory or an i/o device. Addressing I/O or memory devices should use this signal to transfer data onto the CPU data bus.
/rFSH. refresh(output, activity low). Along with /mreq, /rfsh indicates that the current cpu machine cycle and the contents of the address bus should be used to flush dynamic memory. The lower 8 bits of the address bus (A7-A10) contain the refresh address. This signal is similar to the /REF signal of the Z64180.
/RTS0. Request to send 0 (output, activity low). This is the programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive data 0 and 1 (input, high). These signals are the received data to the asci channel.
RXS. Clock serial receive data (input, active high). This line is the receiver data for the CSIO channel. rxs is multiplexed with /cts1 signal of asci channel 1.
Holy state (output, active high). This signal is used with the /m1 and /halt outputs to decode the state of the CPU machine cycle.

architecture
The z180 combines a high-performance CPU core with various system and I/O resources, making it useful in a wide range of applications. The CPU core consists of five functional modules: clock generator, bus state controller, interrupt controller, memory management unit (MMU) and central processing unit (CPU). Integrated I/O resources form the remaining four functional blocks: direct memory access (DMA) control (2 channels), asynchronous serial communication interface (ASCI, 2 channels), programmable reload timer (PRT, 2 channels) and clock Serial I/O (CSIO) channel.

clock generator. Generate system clock from external crystal or clock input. The external clocks are divided by two or one and are provided to internal and external devices.
bus state controller. This logic performs all state and bus control activities related to the CPU and some on-chip peripherals. This includes wait state timing, reset cycles, DRAM refreshes, and DMA bus swaps.
interrupt controller. This logic monitors and prioritizes various internal and external interrupts and traps to provide proper responses from the CPU. To maintain compatibility with Z80 CPUs, three different interrupt modes are supported.
memory management unit. mmu allows the user to map the memory used by the cpu (logically only 64kb) to the 1mb addressing range supported by the z80180/z8s180/z8l180. The organization of mmu object code maintains compatibility with z80 CPUs while providing access to extended memory spaces. This is achieved through the use of an effective "Public Area Banking Area" scheme.
central processing unit. The CPU is microcoded to provide object code cores compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiplication. The core has been modified to allow many instructions to execute in fewer clock cycles.
DMA controller. The dma controller provides high-speed transfers between memory and i/o devices. Supported transfer operations are memory to memory, memory to/from I/O, and I/O to I/O. The supported transfer modes are Request, Burst, and Loop Steal. DMA transfers can access the full 1 MB address range, block lengths up to 64 KB, and can span 64 K boundaries.
Asynchronous Serial Communication Interface (asci). asci logic provides two independent full duplex uarts. Each channel includes a programmable baud rate generator and modem control signals. asci channels can also support multiprocessor communication formats and interrupt detection and generation.
Programmable Reload Timer (PRT). This logic consists of two independent channels, each containing a 16-bit counter (timer) and count reload register. The time base of the counter is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides optional output to allow waveform generation.

Clock Serial I/O (CSI/O). The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for a simple high-speed data connection to another microprocessor or microcomputer. trdr is used for csi/o transmission and reception. Therefore, the system design must ensure that the constraints of half-duplex operation are met (transmit and receive operations cannot occur simultaneously). For example, if a csi/o transfer is attempted while the csi/o is receiving data, the csi/o will not work. Also note that trdr is not buffered. Therefore, attempting to perform a csi/o transmit while the previous transmit data is still shifted out causes the shifted data to be updated immediately, disrupting the ongoing transmit operation. Likewise, reading trdr during send or receive should be avoided.
operating mode
Compatibility of Z80 with 64180. The Z80180/Z8S180/Z8L180 is powered by two different "ancestors" processors, Zilog's original Z80 and Hitachi 64180. The Operational Mode Control Register (OMCR), shown in Figure 8, is programmable to select between certain Z80s and 64180s.

Operation Control Register (OMCR: I/O Address=3eh) M1E (M1 Enable). This bit controls the M1 output and is set to 1 during reset.
When m1e=1, the m1 output is asserted low during the opcode fetch cycle, the int0 acknowledgement cycle, and the first machine cycle of the nmi acknowledgement.
On the z80180/z8s180/z8l180, this option causes the processor to fetch a reti instruction once, and when fetching reti from zero wait state memory, three clock machine cycles are used, which are not fully timing compatible with the z80 , but compatible with on-chip ctc. When m1e=0, the processor does not drive the low bits of m1 during an instruction fetch cycle, and after fetching a reti instruction with normal timing, it returns and refetches the instruction using a fully z80-compatible cycle (including driving the low bits of m1). Some external Z80 peripherals may require this feature to properly decode RETI instructions.

Standby mode (with or without fast recovery). Software can put the z80180/z8s180/z8l180 into this mode by setting the iostop bit (icr5) to 1, ccr6 to 1, and executing the slp instruction. This mode stops the on-chip oscillator, resulting in the minimum power in any mode, less than 10µA.
Like idle mode, the Z80180/Z8S180/Z8L180 will leave standby mode in response to a low open reset or open
NMI, or LOW on Int0-2, is enabled by a 1 of the corresponding bit in the Int/Trap Control Register, and if the brext bit in the CPU Control Register (CCR5) is 1, the bus is granted to an external host. However, the time required for all of these operations is greatly increased due to the need to restart the on-chip oscillator and ensure it is stable to square wave operation.
When the external clock is connected to the external pin instead of the crystal to the external pin and the external pin, and the external clock is running continuously, there is no need to use the standby mode because it does not need time to restart the oscillator, other modes restart faster . However, if the external logic stops the clock in standby mode (for example, by decoding halt low and m1 high for a few clock cycles), then standby mode can be used to allow the external clock source to stabilize after re-enabling.
When the external logical drive is reset to
The Z80180/Z8S180/Z8L180 comes out of standby mode, the use of the crystal or external clock source has stopped, and the external logic must be held low in reset until the on-chip oscillator or external clock source restarts and stabilizes.
Clock Stability Requirements
The Z80180/Z8S180/Z8L180 are much smaller in the divide-by-2 mode selected by the reset sequence - controlled by the clock divide bit in the CPU control post register (CCR7). Therefore, software should:
a. Before the slp instruction to enter standby mode, program ccr7 to 0, select divide by 2 mode, and then.
b. After SLP 01 instruction reset, interrupt, or online restart, delay CCR7 programming to 1 to set a divide-by-one pattern to maximize clock stabilization time.
If software sets ccr6 to 1 before the slp instruction puts the mpu in standby mode, the value in the ccr3 bit determines how long the z80180/z8s180/z8l180 waits for the oscillator to restart and stabilize when it leaves standby mode due to an external interrupt request. If ccr3 is 0, z80180/z8s180/z8l180 wait 217
(131072) clock cycles, whereas if ccr3 is 1, it only waits 64 clock cycles. The latter is called Express Recovery Mode. The same delay applies to granting the bus to an external master in standby mode when the brext bit in the CPU Control Register (CCR5) is 1.
As mentioned before, when the Z80180/Z8S180/Z8L180 leaves standby mode due to NMI low, or when it leaves standby mode due to ENABLED INTO-2 of IEF being low, the flag is 1 due to the IE instruction and it starts by executing an interrupt , the return address is the address of the instruction following the SLP instruction. If the Z80180/Z8S180/Z8L180 leaves standby mode due to enabling external interrupt request in the int/trap control register, but the ief bit is 0 due to the di instruction, the processor restarts by executing the instruction following the slp instruction. If INT0 or INT1 or 2 goes inactive before the clock stabilization delay expires, the Z80180/Z8S180/Z8L180 remains in standby mode.
Time to leave standby mode due to an interrupt request. Note that the Z80180/Z8S180/Z8L180 requires 64 or 217 (131072) clocks to restart, depending on the CCR3 bit.

When the z80180/z8s180/z8l180 is in standby mode, the latter (non-fast-recovery) condition may inhibit it from granting the bus to an external master if many "demand drives" the external master's brext bits. If yes, then quick(ccr5) is 1. Recovery or idle mode can be used. Note that depending on the ccr3 bits, the part needs 64 or 21 (131072) clock cycles to grant the bus.

ASIC transfer register 0. When the asci transmit register receives data from the asci transmit data register (tdr), the data is shifted out to the txa pin. After the transfer is complete, the next byte (if available) is automatically loaded from the TDR to the TSR and the next transfer begins. If there is no data available for transmission, tsr idles by outputting a continuous high level. This register is not programmable access
ASIC transfers data registers 0, 1 (TDR0, 1: I/O address = 06h, 07h). Once the tsr is empty, the data written to the asci transfer data register is transferred to the tsr. Data can be written when tsr shifts out the previous byte of data. Therefore, the asci transmitter is double buffered.
Data can be written to and read from the ASCI transmit data registers. If data is read from the ASIC transfer data register, this read operation does not affect the ASIC data transfer operation
ASIC receives shift register 0,1 (rsr0,1). This register receives the data shifted on the rxa pin. When the data is full, if it is empty, it will automatically transfer the data to the ASCI Receive Data Register (RDR). An overflow error occurs if rsr is not empty when the next incoming data byte is shifted in. This register is not programmable access.
asci receives data fifo 0,1 (rdr0, 1: i/o address=08h, 09h). The asci receive data register is a read-only register. When a complete byte of input data is assembled into rsr, it is automatically transferred into 4-character first-in, first-out (fifo) memory. The earliest character in the fifo (if any) can be read from the receive data register (rdr). In the case of fifo full, the next input data byte can be converted to rsr. So the asci sink is well buffered.

MPE: Multiprocessor Mode Enable (bit 7). ASCI has a multiprocessor communication mode that utilizes extra bits of data for selective communication when multiple processors share a common serial bus. Selects the multiprocessor data format when the MP bit in CNTLB is set to
1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE will enable or disable the "wakeup" function as follows. If MBE is set to 1, only received bytes with MPB (multiprocessor bit) = 1 can affect RDRF and error flags. In fact, other bytes (mpb=0) are "ignored" by asci. If mpe is reset to 0, all bytes (regardless of the state of the mpb data bits) affect redr and error flags. During reset, MPE is cleared to 0.
Reply: Receiver enabled (bit 6). When re is set to 1, the asci transmitter is enabled. When te is reset to 0, the transmitter is disabled and any ongoing transmission operations are interrupted. However, the tdre flag is not reset and the previous contents of tdre are maintained. During reset, in iostop mode, te is cleared to 0.
te: Transmitter enable (bit 5). When te is set to 1, the asci receiver is enabled. When te is reset to 0, the transmitter is disabled and any ongoing transmission operations are interrupted. However, the tdre flag is not reset and the previous contents of tdre are maintained. During reset, in iostop mode, te is cleared to 0.
rts0: Request to send channel 0 (bit 4 in cntla0 only). If bit 4 of the system configuration register is 0, the rts0/txs pin has the rts0 function. rts0 allows asci to control (start/stop) another communication device transmission (e.g. by connecting to the de-
Vice's CTS input). rts0 is essentially a 1-bit output port with no side effects on other asci registers or flags.
Use bit 4 in CNTLA1.
cka1d=1, cka1/trendpin=tendcka1d=0, cka1/trendpin=cka100 Cleared to 0 on reset.
MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3). When multiprocessor mode is enabled (mp in cntlb=1), mpbr when read contains the value of the mpb bits of the last receive operation. When 0 is written, the select EFR function resets all error flags (ovrn, fe, pe, and brk in the ASEXT register) to 0. MPBR/EFR is not defined during reset.