feature

±2.5% Gain Matching ±0.5 LSB Linearity Error Internal Bandgap Voltage Reference Low Fault Energy Single 3.3V Supply

application

PC Graphics Video Signal Conversion - RGBYCbCr – Composite, Y, C

describe

The FMS3818 is a low-cost triple D/A converter designed for speed-critical graphics and video applications. The CMOS level input is converted to an analog current output to drive a 25–37.5Ω load, corresponding to a double-byte terminated 50–75Ω load. Synchronized synchronous current input timing is added to the IOG output. Blank will override the RGB input, setting the IOG, IOB and IOR currents to zero when blank = L. Although suitable for many applications the internal 1.25V reference voltage can be overridden by the VREF input. Few external components are required, just a current reference resistor, current output load resistor, bypass capacitors, and decoupling capacitors. The package is a 48 lead LQFP. The manufacturing technology is CMOS. Performance is guaranteed between 0 and 70°C.

Function description

There are three identical 8-bit D/A converters in the FMS3818, each with a current source output. External loads need to convert these currents into voltage outputs. Data input RGB7 0 is overwritten by blank input. sync=h activates the sync current from ios to sync the green video signal.

Digital input incoming GBR data is registered on the clock input, CLK. The analog output follows the delay, TDO. Sync and Blank The Sync and Blank inputs control the d/a converter interval in the output level (Figure and Table 1). Blank forces D/A output to blank level when sync=l closes current source ios to green D/A converter. sync=h adds 1/ 112 /256th of the full-scale current of the green output. sync=l turns off the sync current during sync prompts. Empty gate D/A input. If blank=H, D/input controls the output current blank level to add to the output. If blank=L, data entry and base are disabled. D/A Outputs Each D/A output is a current source from the VDDA supply. Expressed in current units, follow from current data: G=G7-0&blank+sync*112B=B7-0blank R=R7-0&blank The typical LSB current step is 73.2 microamps. To get a voltage output, a resistor must be connected to ground. The output voltage depends on this external resistor, the reference voltage, and the value of the gain setting resistor connected between rref and gnd. To achieve a double-terminated 75Ω transmission line, a parallel 75Ω resistor should be placed near the analog circuit output pins. Connect the 75Ω termination wire to the analog output with a load of 37.5°C on the FMS3818 current source. The FMS3818 can also operate with 75 ohm termination resistors. To reduce the output voltage swing to the desired range, the nominal value of the RREF resistor should be doubled. The voltage reference full-scale current is through an external resistor, RSET connected between the RREF pin and GND. The voltage on RSET is the reference voltage, Vref, which can be connected to VREF from the 1.25V internal bandgap reference or an external voltage reference. To reduce noise, a 0.1µf capacitor should be connected between VREF and ground. ISET is mirrored to each GBR output current source. To reduce noise, a 0.1µF capacitor should be connected between the comp pin and the analog supply voltage vdda. The power required for power and ground is a single supply +3.3 volts. To minimize power supply induced noise, analog +3.3V is connected to the VDDD and VDDA pins with 0.1 and 0.01µF decoupling capacitors or pin pairs placed near each VDD pin. High conversion rate digital data makes capacitive coupling to the output of any D/A converter potentially problematic. Since the digital signal contains the CLK signal as well as the video output signal data feedthrough often looks like harmonic distortion or degrades the SNR performance. All ground pins should preferably be connected to a common solid ground plane for performance.

The application infographic shows a typical FMS3818 interface circuit. In this example, the optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source. The grounded FMS3818 power supply must be well regulated and free of high frequency noise. Careful decoupling of the power supply will ensure the highest quality video signal at the output of the circuit. The FMS3818 has separate analog and digital circuits. To keep digitizing system noise away from the D/A converter, it is recommended that the supply voltage come from the system analog power supply and all ground connections (GND) are made to analog ground. The power pins should be separated individually on the pins. Printed Circuit Board Layout The design of high-performance mixed-signal circuits requires printed circuits with ground planes. The layout of the overall system board of directors has a great impact on performance. Capacitive coupling from digital to analog circuits can lead to poor D/A conversion. Consider these suggestions for layout: 1. Keep key analog traces (VREF, IREF, COMP, ios, ior, iog) as short as possible. All digital signals are possible. The FMS3818 should be close to the edge of the board, near the analog output connectors. 2. The power plane of the FMS3818 should be separate from the one that provides the digital circuit. All VDD should use one power board pin. If the power supply of the FMS3818 is the same as part of the system digital circuit, the FMS3818 should be separated with 0.1µF and 0.01µF capacitors isolated with ferrite beads. 3. The ground plane should be solid, not cross hatched. The connection to the ground plane should be very short lead. 4. If there is a dedicated power board layer for the digital power supply, it should not be placed under the FMS3818, voltage reference or analog output. Capacitive coupling of digital power supply noise to the FMS3818 and its associated analog circuitry can have a detrimental effect on performance. 5. CLK should be handled with care. Jitter and Noise Turning this clock on can degrade performance. Terminate the clock lines carefully to eliminate overshoot and ringing. Improved Transition Time Output The parallel capacitor controls the output to slow down the transition time, while the series inductance causes the amount of ringing that affects overshoot and settling times. For a double-terminated 75Ω load, the transition time can be improved by matching the output capacitor impedance of the FMS3818. The output capacitor can be connected in series with a 220 NH inductor to a 75Ω power supply terminal.