feature:

Serial Peripheral Interface (SPI) compatible supports SPI modes 0 (0,0) and 3 (1,1);

- Datasheet describes Mode 0 operation; low and standard voltage operation;

-VCC = 1.8V to 5.5V; 20MHz clock frequency (5V); 8-byte page mode; block write protection;

- Protect 1/4, 1/2 or the entire array; write protect (wp) pin and write disable command for hardware and software data protection

; Automatic timing write cycle (max. 5 ms); High reliability;

- Endurance: 1 million write cycles;

- Data retention: 100 years; Green (PB/Halogen free/RoHS compliant) packaging options;

-Mold sales: wafer shape, waffle packaging, bump waffle.

describe

The AT25010B /020B/040B provides 1024/ 2048 / 4096 -bit serial Electrically Erasable Programmable Read-Only Memory (EEPROM), 128/256/512 words per 8-bit. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation is essential. AT25010B/020B/040B are available for space saving, jedec soic, udfn, tssop, xdfn and vfbga packages.

The AT25010B/020B/040B is enabled through the chip select pin (CS) and accessed through a three-wire interface consisting of serial data input (SI), serial data output (SO), and serial clock (SCK). All programming cycles are fully automatically timed and no separate erase cycle is required before writing.

Block write protection is enabled by programming the Status Register with one of the four write-protected blocks. Separate program enable and program disable instructions provide additional data protection. Hardware data protection passed

WP pin used to prevent accidental write attempts. The hold pin can be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings: Operating Temperature………-40°C to +125°C; Storage Temperature -65°C to +150°C.

Voltage on any pin: With respect to ground …………-1.0V to +7.0V; Maximum operating voltage 625V: DC output current 5mA.

CAUTION: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and does not imply that the functional operation of the device under these or any other conditions is beyond that specified in the operating section of this specification. Long-term exposure to absolute maximum rating conditions may affect device reliability.

2. Serial Interface Description

MASTER: The device that generates the serial clock.

SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a slave.

Transmitter/Receiver: The AT25010B/020B/040B has separate pins for data transmission (SO) and reception (SI).

MSB: The most significant bit (msb) is the first bit transmitted and received.

Serial opcodes: After the device is selected, CS will go low and the first byte will be received. This byte contains the operation code that defines the operation to be performed. The opcode also contains address bit A8 in read and write instructions.

Invalid opcode: If an invalid opcode is received, no data will be transferred into the AT25010B/020B/040B and the serial output pin (SO) will remain in a high impedance state until a fall in CS is detected again along. This will reinitialize serial communication.

Chip Select: When CS pin is low, select AT25010B/020B/040B. When no device is selected, data will not be accepted through the si pin and the so pin will remain in a high impedance state.

Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When a device is selected and a serial sequence is in progress, HOLD can be used to pause and not reset the master device of the serial sequence. To suspend, the hold pin must be pulled low while the SCK pin is low. To resume serial communication, hold the pin high while the SCK pin is low (SCK may still toggle during the hold). When the SO pin is in a high impedance state, the input to the SI pin is ignored.

Write Protect: When held high, the write protect pin (wp) will allow normal read/write operations. When the wp pin goes low, all writes are disabled.

Low operating pressure will interrupt writing to the AT25010B/020B/040B while CS is still low. Low operating pressure will not affect any write operations if the internal write cycle has been initiated.

three. Function description

The AT25010B/020B/040B is designed to interface directly with the Synchronous Serial Peripheral Interface (SPI) of the 6805 and 68HC11 series microcontrollers.

AT25010B/020B/040B use 8-bit instruction register. The list of instructions and their operation codes are shown in Figure 3-1. All instructions, addresses and data are transferred in msb first and transitioned in cs from high to low.

Write Enable (wren): When VCC is applied, the device will power up in the write disabled state. All programs - therefore, the ming directive must be preceded by a write enable directive. The wp pin must be held high during the wren instruction.

Write Disable (WRDI): To prevent accidental writes to the device, the write disable instruction disables all programming modes. The wrdi instruction has nothing to do with the state of the wp pin.

Read Status Register (RDSR): The Read Status Register instruction provides access to the Status Register. The read/busy and write enable status of the device can be determined by the rdsr instruction. Similarly, the block write protection bits indicate the extent of the protection employed. These bits are set using the wrsr instruction.

Write Status Register (WRSR): The wrsr instruction allows the user to select one of four protection levels. The AT25010B/020B/040B is divided into four array segments. A quarter, half or all memory segments can be protected. Therefore, any data within any selected segment will be read-only. Block write protection level and corresponding status register control bits.

Bits bp1 and bp0 are non-volatile units with the same characteristics and functions as conventional memory units (eg wren, twc, rdsr).

Reading Sequence (Read): The following sequence is required to read the AT25010B/020B/040B through the SO pin. After the cs line is pulled low to select the device, the read opcode (including a8) is sent over the si line, followed by the byte address to read (a7-a0). When done, any data on the si line is ignored. The data (d7-d0) is at the specified address, then moved onto the so line. If only one byte is read, the cs line should be driven high after the data is output. Since the byte address is auto-incremented, data will continue to be shifted out, so the read sequence can continue. When the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle.

Write Sequence (Write): In order to program the AT25010B/020B/040B, the Write Protect pin (WP) must be held high and two separate instructions executed. First, the device must be enabled for writing via the wren command. The write (write) instruction can then be executed. Additionally, the address of the memory location to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands except the rdsr instruction are ignored.

Write commands require the following sequence. After the cs line is pulled low to select the device, the write opcode (including a8) is sent over the si line, followed by the byte address (a7-a0) and data (d7-d0) to be programmed. The program will start after the CS pin is brought high. After the d0 (lsb) data bit is clocked, the cs pin must transition from low to high immediately within the sck low time.

The ready/busy status of the device can be determined by initiating the Read Status Register (RDSR) instruction. If bit 0 = "1", the write cycle is still in progress. If bit 0 = "0", the write cycle has ended. During a write programming cycle, only the RDSR instruction is enabled.

The AT25010B/020B/040B is capable of performing 8-byte page write operations. After each byte of data is received, the three low-order address bits are internally incremented by one; the six high-order bits of the address remain unchanged. If more than 8 bytes of data are transferred, the address counter will roll over and the previously written data will be overwritten. The AT25010B/020B/040B automatically returns to the write disable state at the end of the write cycle.

Note: If the wp pin is too low or the device is not write enabled (wren), the device will ignore the write command and will return to standby when CS is raised. A new CS falling edge is required to reinitialize serial communication.

4. Timing diagram