Features Industry Standard Pins High Current Drive Capability of ±4 A in Miller Plateau Regions
Efficiently obtain constant current even at low supply voltages
TTL/CMOS Compatible Inputs, Independent of Supply Voltage 20 ns typical rise time and 15 ns typical fall time under 1.8 nF load Typical propagation delay time of 25 ns on input fall, 35 ns typical propagation delay time on input rise
4.5-V to 15-V supply voltage
0.3 mA supply current Dual outputs in parallel for higher drive current Thermally enhanced MSOPPOWERPAD™ software package rated for -40°C to +125°C
TrueDrive™ output architecture using bipolar and CMOS transistors in parallel
2 apps switch power
DC-DC Converter Motor Controller Line Driver
Class D Switching Amplifier Description
The ucc2732x and ucc3732x families of high-speed dual mosfet drivers deliver large peak currents to capacitive loads. Three standard logic options are available - double inversion, double non-inversion, one inversion and one non-inversion driver. The thermally enhanced 8-pin PowerPad MSOP package (DGN) significantly reduces thermal resistance and improves long-term reliability. The ucc2732x and ucc3732x are also available in standard soic-8(d) or pdip-8(p) packages.
These drivers employ an inherent minimum breakdown current design that delivers the most needed 4A current in the miller plateau region during MOSFET switching transitions. A unique bipolar and mosfet hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.

Overview
The ucc2732x and ucc3732x families of high-speed dual MOSFET drivers can deliver large peak currents to capacitive loads. Three standard logic options are available: double inverting, double non-inverting and one inverting and one non-inverting driver. These drivers employ an inherently minimal penetration current design, delivering 4A in the miller plateau region during MOSFET switching transitions where it is most needed. A unique bipolar and mosfet hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.
Functional block diagram

Characterization Input Stage The input threshold has a logic sensitivity of 3.3v over the entire vdd voltage range; however it is equally compatible with 0v to vdd signals.
The inputs of the ucc2732x and ucc3732x family of drivers are designed to withstand 500 mA of reverse current without any damage to the IC. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is met in typical power supply applications where the input signal is provided by a pwm controller or logic gate with fast transition times (<200ns). The input stage of the driver functions as a digital gate and is not used in applications that use a slowly varying input voltage to generate a switching output when the logic threshold of the input section is reached. While this may not be detrimental to the driver, the driver's output may switch repeatedly at high frequencies.
The user should not attempt to alter the input signal to the driver in order to slow down (or delay) the speed of the output signal. If a limited rise or fall time of the power device is required, an external resistor can be added between the output of the driver and the load device (usually the gate of the power mosfet). External resistors also help remove power dissipation from the device package as described in (see Thermal Considerations)
It is important that the two channels of the input signal, ina and inb, have logic compatible thresholds and hysteresis. If not used, INA and INB must be tied to VDD or GND; it cannot be left floating.
output stage
The inverted output of the UCCx7323 and the output of the UCCx7325 are designed to drive external P-channel mosfets. The non-converted outputs of the UCCx7324 and the outputs of the UCCx7325 are designed to drive external channel mosfets.
Characterization (continued)
Each output stage is capable of delivering ±4-A peak current pulses and oscillations to Vdd and Gnd. The pull-up and pull-down circuits of the driver are composed of bipolar transistors and mosfet transistors in parallel. The peak output current rating is the combined current from the bipolar transistor and the mosfet transistor. When the voltage on the driver output is less than the saturation voltage of the bipolar transistor, the output resistance is the rds(on) of the mosfet transistor. Each output stage also provides very low overshoot and overshoot impedance due to the body diode of the external mosfet.
This means that in many cases, external Schottky clamp diodes are not required. The uccx732x family provides 4A gate drive, which is most needed during MOSFET switching transitions in the miller plateau region to improve efficiency. A unique bipolar and mosfet hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
Device functional mode

When the vdd supply is between 4.5v and 15v, the output stage depends on the state of the hi and li pins

Application Information High-speed power supplies usually require high-speed, high-current drivers, such as the uccx732x series. A high power buffer stage is required between the pwm output of the control ic and the gate of the main power mosfet or igbt switching device. In other cases, driver ICs are used to drive power device gates through drive transformers. Synchronous rectified power supplies also need to drive multiple devices at the same time, and these devices place a huge load on the control circuit.
The driver IC is used when the main pwm regulator IC cannot directly drive the switching device for one or more reasons. pwmics do not have the strong drive capability required for expected switching mosfets, limiting switching performance in applications. In other cases, it may be desirable to minimize the effects of high-frequency switching noise by placing high-current drivers physically close to the load. Additionally, newer ICs targeting the highest operating frequencies do not contain onboard gate drivers at all. Their pwm outputs are only used to drive high impedance inputs into drivers such as the uccx732x. Finally, the control IC is thermally stressed due to power dissipation, and external drivers help by transferring heat from the controller to the external package.
typical application

uccx732x drives two separate mosfets
Design Requirements In order to select the proper device from the uccx732x family, ti recommends first checking the proper logic of the outputs. The UCCx7323 has dual inverting outputs; the UCCx7324 has dual non-inverting outputs; the UCCx7325 has inverting channel A and non-inverting channel B. Additionally, some design considerations must first be evaluated in order to make the most appropriate choice. These include vdd, drive current and power dissipation.
The source/sink capability of the detailed design procedure during the Miller plateau The high power mosfet places a heavy load on the control circuit. Efficient, reliable operation requires proper drive. The uccx732x drivers have been optimized to provide maximum drive for power mosfets in the miller platform region of switching transitions. This interval occurs when the drain voltage swings between the voltage levels dictated by the power topology, requiring the drain-gate capacitance to be charged/discharged with current supplied or removed by the driver [1].
Two circuits are used to test the current performance of the uccx732x driver. In each case, external circuitry was added to clamp the output near 5 volts, while the IC was sinking or sourcing current. An input pulse of 250 ns was applied at a frequency of 1 kHz at the appropriate polarity for the corresponding test. In each test, there is a transient where the current peaks and then settles to a steady state value. The current measurements recorded were taken 200 ns after the input pulse was applied, after the initial transient. The first circuit was used to verify the current sink capability when the driver output was clamped around 5V, a typical gate in the Miller plateau region source voltage value. It is found that the UCCX7323 sinks 4.5A when VDD=15V and 4.28A when VDD=12V.

The current sink capability test circuit is used to test the capability of the current source, with the output clamped at around 5V, using a set of Zener diodes. The voltage sources of the UCCx7323 are 4.8A (VDD=15V) and 3.7A (VDD=12V).
Current source capability test

Parallel outputs By connecting the ina/inb inputs as close to the ic as possible, the a and b drivers can be combined into a single driver, and the outa/outb outputs are connected together if no external gate drive resistors are used. In some cases where external gate drive resistors are used, ti recommends that the resistors can be equally divided between outa and outb to reduce the imbalance between the two channels caused by parasitic inductance

Important considerations for UCCx7323/4 paralleling two channels include: 1) INA and INB should be shorted as close as possible to the device in the PCB layout, for OUTA and OUTB, in this case, the PCB layout parasitic mismatches are minimized. 2) INA/B input slope signal should be fast enough to avoid VIN H/VIN L, TD1/TD2 mismatch between channel A and channel B. TI recommends that the input signal slope be greater than 20 V/US.
Video displays, despite low quiescent vdd current, will have higher total supply current depending on the outa and outb currents and the programmed oscillator frequency. The total VDD current is the sum of the quiescent VDD current and the average output current. Knowing the operating frequency and the MOSFET gate charge (qg), the average output current can be calculated using Equation 1.
iout=qg×f
where f is the frequency (1)
For best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. Surface mount components are strongly recommended. A 0.1-micron ceramic capacitor should be located closest to the VDD ground connection. Also, a larger capacitor with a relatively low esr (eg 1µF and above) should be connected in parallel to help pass high current peaks to the load. In driver applications, the parallel combination of capacitors should exhibit low impedance characteristics for the expected current levels. Driver Current and Power Requirements
The uccx732x series drivers are capable of supplying 4A to the MOSFET gate for tens of nanoseconds. High peak current is required to turn on the device quickly. Then, to shut down the device, the driver is required to draw a similar amount of current to ground. This repeats at the operating frequency of the power supply. This discussion uses mosfet because it is the most commonly used switching device in high frequency power conversion equipment.
Current required to drive power mosfets and other capacitive input switching devices. Reference [2] includes information on the previous generation of bipolar ic gate drivers.
When a driver chip is tested under a discrete capacitive load, calculating the power required by the bias supply is a fairly straightforward matter. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2. e=CV2
C is the load capacitor
V is the bias voltage that powers the driver (2)
When the capacitor discharges, an equal amount of energy is transferred to ground. This will result in the power loss given by Equation 3. P=CV2×F
where f is the switching frequency (3)
This energy is dissipated in the resistive elements of the circuit. Therefore, there is no external resistance between the driver and the gate, and this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charging and the other half is dissipated when the capacitor is discharging. A practical example of the conditions using the previous gate drive waveform should help clarify this.
When vdd=12v, cload=10nf, f=300khz, the power loss can be calculated according to formula 4.
P=10nF×(12V)2×(300kHz)=0.432W(4)
For a 12 V supply, this equals the current (see Equation 5):
I=P/V=0.432W/12V=36mA(5)
The actual current measured from the power supply is 0.037a, which is very close to the predicted value. However, the idd current due to internal consumption of the IC should be considered. With no load, the IC's current consumption is 0.0027A. In this case, the output rises and falls faster than the load. This can result in an almost insignificant but measurable current due to cross-conduction in the output stage of the driver. However, these tiny current differences are hidden in high-frequency switching spikes that are beyond the measurement capabilities of a basic lab setup. The current measured at a 10nF load is fairly close to the expected value.
The switching load generated by the power mosfet can be converted into an equivalent capacitance by sensing the gate charge required by the switching device. This gate charge includes the effect of the input capacitance plus the additional charge required to swing the device drain between switching states. Specifications provided by most manufacturers provide typical and maximum gate charge (NC) for switching devices under specified conditions. Using the gate charge qg, the power that must be dissipated by the capacitor to charge can be determined. This is achieved by using the equivalent qg=ceff×v to provide Equation 6 for power:
p=c×v2×f=v×qg×f(6)
Equation 6 allows the power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage and a specific switching frequency.
Apply Curve

Circuit performance achievable with one driver (half of an 8-pin IC) driving a 10nF load. The input pulse width (not shown) was set to 300 ns to show two transitions in the output waveform. Note the linear rising and falling edges of the switching waveform, which is due to the constant output current characteristic of the driver rather than the resistive output impedance of traditional mosfet-based gate drivers.
The source and source current of the driver depends on the vdd value and the output capacitor load. The greater the vdd value, the greater the current capacity; at the same time, the greater the capacitive load, the greater the current sink capacity.
Tracking resistance and inductance, including wire and cable used for testing, slows the rise and fall times of the output; thus reducing the current capability of the driver.
For higher current results, reduce the resistance and inductance on the board as much as possible and increase the capacitive load value to eliminate the effect of the inductance value.

Power Recommendations
The recommended bias supply voltage range for the UCCX732X is 4.5 V to 15 V. The upper end of this range is driven by the 16 V absolute maximum voltage rating of VDD. ti recommends maintaining proper margins to allow for transient voltage spikes.
A local bypass capacitor must be placed between the VDD and GND pins. This capacitor must be as close as possible to the device. Low esr ceramic surface mount capacitors are recommended. TI recommends using two capacitors between VDD and GND: a 100 nF ceramic surface mount capacitor for high frequency filtering, placed very close to the VDD and GND pins, and a 220 nF to 10µF surface mount capacitor Install capacitors for IC bias requirements.

Layout Guidelines Without proper consideration during board layout, optimum performance of high- and low-side gate drivers cannot be achieved. Emphasize the following points:
1) Low ESR/ESL capacitors must be connected near the IC between the VDD and GND pins to support the high peak current drawn from VDD during external MOSFET turn-on.
2) Grounding precautions:
The first task in designing the ground connection is to limit the peak current that will charge and discharge the gate of the mosfet to the smallest physical area. This will reduce loop inductance and minimize noise issues on the gate terminals of the mosfet. The gate driver must be as close as possible to the mosfet.
Star point grounding is a good way to reduce noise coupling between the current loop and the current loop. The grounding of the driver is grounded at one point with other circuit nodes such as the power supply of the power mosfet and the grounding of the pwm controller. Connection paths must be as short as possible to reduce inductance and as wide as possible to reduce resistance.
Provide an acoustic enclosure using the ground plane. Fast rise and fall times at the output can corrupt the input signal during conversion. The ground plane must not be the conduction path for any current loops. Instead, the ground plane must be connected to the star point with a single trace to establish the ground potential. In addition to sound insulation, ground planes also help with heat dissipation.
3) In noisy environments, it may be necessary to use short traces to connect the inputs of unused channels of the UCC2742X device to VDD or GND to ensure that the outputs are enabled and prevent noise from causing output failures.
4) Separate power lines and signal lines, such as output and input signals.
layout example

The range of use of thermal factor drivers is greatly affected by the drive power requirements of the load and the thermal characteristics of the integrated circuit package. In order for a power driver to function within a specific temperature range, the package must be able to efficiently remove the heat generated while maintaining the junction temperature within the specified range. There are three different software packages for the uccx732x driver family to meet a range of application needs.
The msop powerpad-8 (dgn) package greatly alleviates this concern by providing an efficient way to remove heat from the semiconductor junction. As shown in Ref. [3], the powerpad package provides a lead frame die exposed at the bottom of the package. This pad is soldered directly to the copper on the PC board directly below the IC package, reducing θ to 4.7°C/W. The data presented in Ref. [3] shows that the power consumption can be increased by a factor of four in the PowerPad configuration compared to the standard package. As mentioned in reference [4], the PC board must be designed with heat sinks and thermal vias to complete the thermal subsystem. This design results in a significant improvement in thermal performance over d or p packages and shows more than double the power performance of d and p packages.