Feature

2A DC output current

2.9V to 18V input voltage

output voltage can be adjusted from 0.6V

250kHz. Programming

up to 1MHz

Internal soft start and inhibition

Low voltage difference operation: 100%duty cycle

Voltage feedback

Air load current operation

Overcurrent and heat protection

VQFN3X3-8L packaging

set-top box, DVD, DVD burning machine, car audio, LCD, LCD, LCD, LCD电视和监视器

工业：充电器、汽车电池、PLD、PLA、FPGA

联网：XDSL、调制解调器、DC-DC模块

计算机：光存储， Hard disk, printer, sound card/graphics card

Description

L5985 is a lower -voltage switch regulator 2.5A current -limiting embedded power MOSFET, so it can depend on the application conditions to the load. The input voltage range is 2.9V to 18V, and the output voltage can be from 0.6V to Vin. The minimum input voltage is that the startup device is suitable for bus 3.3V bus. The minimum external component is required. The device includes an internal 250kHz switch external frequency oscillator to 1MHz. The QFN package with exposed pads allows to be reduced to about 60 ° C/W

function description

L5985 based on ""voltage mode"" and constant frequency control. The output voltage VOUT is controlled by the feedback pink (FB) to provide an error signal. Compared with the sawtooth wave with a fixed frequency, it controls the power switch. The main internal module is shown in the box diagram in Figure 3. They are: a full -integrated oscillator, providing jagged waves to adjust the duty cycle and synchronization signals. Its switching frequency can be adjusted by external and external. Realize the feedback of voltage and frequency. Z soft start circuit to limit the influx of the starting phase. The pulse width of the voltage mode error amplifier and driving the internal power switch. High -voltage side driver of the embedded Poro -Porter power MOSFET switch. Sensing peak current and extreme current. Z A pressure regulator and internal benchmark. It provides internal circuits and provides fixed internal reference. A voltage monitoring circuit (UVLO), which is used to check input and internal voltage. Z Thermal block to prevent heat out of control

oscillator and synchronization

Figure 4 shows the box diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. The frequency depends on the resistor unnecessary connected to the FSW. If the FSW pin keeps floatingMove, the frequency is 250kHz; it can be increased to as shown in Figure 6 and is grounded by the external resistor. Improve the temporary line performance of the line, and maintain the constant input voltage of the width of the pulse width. The voltage feedback is to change the jagged waves by changing the slope of the voltage (see Figure 5.A) according to the changes in the input voltage. If the oscillator frequency increases the external resistor. In this way, the frequency feed (Figure 5.B) is achieved to keep the PWM gain and the switch frequency constant (see Section 5.4 expression). Synchronous signal is generated by the synchronous pipe foot. The phase shift of this signal is 180 ° with the clock. When the two devices are synchronized, this delay is very useful to connect the synchronous pins together. When connecting the synchronous pipe foot, the high oscillator frequency of the device is used as the main device, so the device is switched from the frequency but delayed for half a cycle. In this way, the average root value of the current can be reduced to the maximum extent.

This device can work simultaneously to feed the external clock signal at a higher frequency. Synchronous changes to the zigzal wave amplitude and change the pulse width adjustment gain (Figure 5.c). When studying the stability of the ring, this change must be considered. In order to minimize the change of the PWM gain, the free running frequency (the resistance on the FSW pin) should be set only slightly lower than the external clock frequency. This changes in the pre -adjustment frequency will change the tap tooth slope to obtain neglected truncated serrated, due to external synchronization.

Soft start

Soft start is the key to ensuring the correct and safe startup of the booster variable. It avoids the impact of excitation surge, making the output voltage rising single. Soft start is an error amplifier performed by a staircase slope on the non -reversing input (VREF). Therefore, the output voltage conversion rate is:

Among them, the conversion rate of SRVREF is non -inverted input, R1, R2 is a resistor separator regulating the output voltage (see Figure 7). Soft start stairs include 9.5mV each step of 64 steps, from 0V to 0.6V. The time base of one step is 32 clock cycles. So the soft start time and output voltage conversion rate depends on the switch frequency

For example, when the switching frequency is 250kHz, the SSTIME is 8ms.

error amplification and compensation

Error amplifier (E/A) provides error signal execution pulse width comparison with jagged waves. Its non -inverter input is connected to the 0.6V voltage benchmark internally, and its inverter input (FB) and output (comp) are external available for feedback and frequency compensation. In this device, the error amplifier is a voltage modulus calculation amplifier with high DC gain and low output impedance. The characteristics of non -checked errors are as follows:

In continuous continuousIn the conductive mode (CCM), the transmission function of the power segment has two poles produced by the LC filter and zero points produced by the ESR of the output capacitor. According to the output ESR value, various compensation network capacitors can be used. If the zero point introduced by the output capacitor will help compensate the LC filter, the bipolar of the LC filter can use type II compensation network. Otherwise, the type must be used to use the compensation network (the relevant compensation network selection). In any case, the method of compensation cycle is to introduce zero to obtain a safe phase.

Over -current protection

L5985 to achieve over -current protection sensing flow over power MOSFET. Due to the noise generated by the power MOSFET switch activity, the current response is disabled in the initial stage of the conduction time. This can avoid failure to detect the failure state. This interval is usually called ""cover time"" or ""blank time"". The cover time is about 200ns. When the current is detected, according to the operating conditions.

1. Output voltage adjustment. When the current is detected, the power MOSFET is closed and the internal reference (VREF), which will set the error amplifier to zero and maintain this state clock cycle within the soft start time (TSS, 2048)). After this period of time, a new soft start -up stage occurred, and internal references began to tilt (see Figure 8.A).

2. Soft start phase. If the current limit is reached, the power MOSFET is closed to achieve pulse over flow protection. In the soft start phase, in the case of overcurrent, the device can skip the pulse to maintain the output current constant equal to the current limit. If the current is higher than the current threshold at the end of the ""cover time"