benefit

Fully optimize system efficiency. Higher levels of efficiency are achievable compared to traditional discrete components. Save up to 50% of PCB space compared to discrete solutions. higher frequency of operation. Simplifies system design and board layout. Reduce time component selection and optimization.

feature

7V to 20V Input Voltage Range Output Current to 32A Supports 1MHz Switching Frequency Internal Adaptive Gate Driver Integrated Schottky Diode Low-Side FET Peak Efficiency >90% Out-of-Phase Shutdown

General Instructions

The FDMF8704 is a fully optimized integrated driver enhanced high current synchronous mosfet power stage solution for buck dc-dc applications. The device integrates a driver chip and space saving two power mosfets, mlp 8x8, 56 pin package. Fairchild's integrated approach optimizes the entire switching power stage to drive FET dynamic performance, system inductance and comprehensively address resistance issues. Packaging parasites and layout solutions to problems associated with traditional discrete are greatly reduced. The result of this comprehensive approach is significant savings in board space, thus maximizing footprint power density. This solution is based on the Intel 8482 ; DRMO specification.

application

Desktop and server VR11.x V-core and non-V-core buck converters. Gaming consoles and high-end CPU/GPU powered desktop systems. High current DC-DC point-of-load (POL) converters. Microprocessor voltage regulators for networking and telecommunications. Small voltage regulator module.

Function description

FDMF8704 is for synchronous buck converter topology. A single PWM input signal is properly driving the high-side and low-side mosfets. Each part is capable of driving speeds up to 1MHz. Low-Side Driver The Low-Side Driver (LDRV) is designed to drive a ground referenced low rds(on) n-channel mosfet. The bias of ldrv is internally connected between vcin and cgnd. When the driver is enabled, the driver output is connected to the PWM input. When the driver is disabled (DISB=0V), LDRV remains low. High Side Driver The high side driver (HDRV) is designed to drive floating n-channel MOSFETs. The bias voltage of the high-side driver is developed by the bootstrap power supply circuit, including external diodes and external bootstrap capacitors (CBOOT). During boot, vswh remains at pgnd, allowing cboot to charge to vcin through the internal diode. When the PWM input is high, hdrv will start charging the gate of the high-side mosfet (Q1). During this transition, the charge is removed from the cboot and sent to the gate of the first quarter. When Q1 is turned on, VSWH rises to vin, forcing the boot pin to vin + vc (boot), which provides enough VGS boost for the first quarter. Completing the switching cycle, Q1 is turned off by pulling HDRV to VSWH.

Then cboot is to charge to vcin when vswh drops to pgnd. The HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate remains low. The adaptive gate driver circuit driver chip uses an advanced design to ensure minimal mosfet dead time while eliminating potential shoot-through (cross-conduction) currents. It senses the mosfet and adaptively adjusts the gate drive to make sure they don't go at the same time. related timing waveforms. To prevent overlap during low-to-high transitions (Q2 off to Q1 on), the adaptive circuit monitors the voltage at the LDRV pin. When the PWM signal goes high, after some time q2 starts to turn off the propagation delay (tpdl(ldrv)). Once the LDRV pin discharges below ~1.2V, Q1 starts to turn on with a delay tpdh(hdrv) after adaptation. To prevent overlapping transitions (Q1 off to Q2 on) during high-to-low transitions, the adaptive circuit monitors the voltage at the switch pins. When the PWM signal goes low, Q1 will start to turn off after a propagation delay (tpdl(hdrv)). Once the VSWH pin drops below ~2.2V, Q2 starts to turn on after the adaptive delay TPDH (LDRV). Additionally, vgsQ1 is monitored. When VGS(Q1) discharges below ~1.2V, A initiates a secondary adaptive delay, causing Q2 to drive after TPDH(LDRV) regardless of software state. The implementation of this function is to ensure that cboot does not fall below the 2.2V adaptive threshold for each switching cycle, especially when the power converter is sinking current. The second delay TPDH (HDRV) is longer than TPDH (LDRV).

Application Information Power Supply Capacitor Selection For the power supply input (vcin) of the fdmf8704, a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1µF, X7R or X5R capacitors. Place this capacitor close to the FDMF8704 vcinCGND pin. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (cboot) and an external Schottky diode, a bootstrap capacitor of 100nF, X7R or X5R capacitor is sufficient. The peak inrush current rating of the boot diode should be for the pickup circuit as it depends on the impedance of the entire boot circuit of the equivalent circuit, including the PCB trace. The boot diode must be sized enough to carry forward charging current. See Figure 14 for the boot diode average forward current. The bootstrap diode must have low vf and low reverse current leakage. The breakdown voltage of the bootstrap diode must be greater than the voltage booted to vswh. The printed circuit board layout guide shows the FDMF8704 and key parts. All high current paths such as vin, vswh, VOUT and GND copper should be short and wide for better stable current flow, heat dissipation and system performance. The following are guidelines that pcb designers should follow: 1. The input bypass capacitor should be close to the VIN and ground pins of the FDMF8704 to help reduce the input current ripple component caused by switching operations. 2. The minimum area of VSWH copper reduces switching noise emissions. The VSWH copper traces should also be wide enough to accommodate high currents. Other signal routing should be considered such as the pwm input and the path of the pilot signal taking care to avoid noise pickup from the vswh copper area. 3. The output inductor should be placed as close as possible to the FDMF8704 to reduce power loss due to copper traces. 4. The buffer voltage to suppress vswh oscillations and spikes should be placed near the FDMF8704. Resistors and capacitors need to be properly sized for power dissipation. 5. Place boot diodes, ceramic bypass capacitors, and boot capacitors close to VCIN and the boot pins of the FDMF8704 to provide stable power. Trace width and length should also be considered 6. Using multiple vias on each copper area to interconnect each via top, inside and bottom helps smooth current and heat conduction. Vias should be relatively large and reasonably inductive.