Features: Full-scale frequency set by external system clock (up to 2 MHz); very low linearity error (0.005% max at 1 MHz fs; 0.02% max at 2 MHz; no critical external components required; accurate 5V Voltage reference; low drift (25 ppm/C° max); dual or single supply operation; voltage or current input; MIL-STD-883 compliant versions available.

Product Description

The AD652 Synchronous Voltage-to-Frequency Converter (SVFC) is a powerful precision analog-to-digital conversion block with a typical 0.002% (0.005% maximum) nonlinearity at an output frequency of 100 kHz. The inherent monotonicity of the transfer function and wide range of clock frequencies allow conversion times and resolutions to be optimized for specific applications.

The AD652 uses a variation of charge balancing technology to perform the conversion function. The AD652 uses an external clock to define the full-scale output frequency, rather than relying on external capacitors for stability. The result is a more stable, more linear transfer function with significant application advantages in both single-channel and multi-channel systems.

Gain drift is minimized using a precision low-drift reference and low tc, on-chip, thin-film scaling resistors. In addition, laser afer trimming is used to reduce the initial gain error to less than 0.5%.

The analog and digital sections of the AD652 are designed to allow single-ended supply operation, simplifying the use of isolated supplies.

The AD652 has five performance grades. The JP and KP grades for the 20 lead PLCC package are specified for operation in the 0°C to +70°C commercial temperature range. The AQ and BQ ratings for the 16-lead Cerdip package are specified for operation over the -40°C to +85°C industrial temperature range. The AD652SQ operates over the entire -55°C to +125°C extended temperature range.

Product Highlights

1. Using an external clock to set the full-scale frequency enables the AD652 to achieve linearity and stability far superior to other monolithic VFCs. By using the same clock to drive the AD652 and setting the count period (via a suitable divider), the conversion accuracy is independent of changes in clock frequency.

2. The AD652 synchronous VFC requires only one external component (a non-critical integrator capacitor) to operate.

3. The AD652 includes a buffered, accurate 5V reference voltage.

4. The clock input of AD652 is compatible with TTL and CMOS, and can also be driven by negative power supply. The flexible open collector output stage provides sufficient current sink capability for TTL and CMOS logic as well as optocouplers and pulse transformers. A capacitor programmable one-shot is provided for selecting the optimal output pulse width for power reduction.

5. The AD652 can also be configured as a synchronous F/V converter for isolated analog signal transmission.

6. AD652 has a MILSTD-883 compliant version. For detailed specifications, see the analog device military data sheet or the current AD652/883B data sheet.

theory of operation

A synchronous VFC is similar to other voltage-to-frequency converters in that it uses an integrator to charge balance the input signal and uses an internal reference current. However, synchronous voltage-to-frequency converters (SVFCs) use an external clock instead of a one-shot as the primary timing element, which requires high-quality and low-drift capacitors. This allows the designer to determine the stability and drift of the system based on the selected external clock. A crystal oscillator can also be used if desired.

The svfc architecture provides other system advantages in addition to low drift. If the output frequency is measured by counting the pulses of the gated clock signal, then the stability of the clock is not important, and the device just works as a voltage-controlled divider, producing a high-resolution A/D. If a large number of inputs must be monitored simultaneously in a system, controlling the relationship between the timing relay frequency output pulse and the user-supplied clock greatly simplifies signal acquisition. Furthermore, if the clock signal is provided by the vfc, the output frequency of the svfc is proportional to the product of the two input voltages. Therefore, both signals are multiplied and ad-converted at the same time.

The pinout of the AD652 SVFC is shown in Figure 2 and Figure 3. A block diagram of a device configured as an SVFC along with various system waveforms is shown in Figure 4.

Figure 4 shows a typical up and down ramp integrator output for a charge-balanced vfc. After the integrator output exceeds the comparator threshold and the output of the AND gate goes high, nothing happens until the negative edge of the clock occurs to transfer information to the output of the d flip-flop. At this point, the clock level is low, so the latch does not change state. When the clock returns high, the latch output goes high and drives the switch to reset the integrator; at the same time, the latch drives the AND gate into a low output state. On the next negative edge of the clock, the low output state of the AND gate is transferred to the output of the d flip-flop. When the clock returns high, the latch output goes low and drives the switch back to integrated mode. At the same time, the latch drives the AND gate into a mode where it truly relays the information the comparator provides to it.

Since the reset pulse applied to the integrator is exactly one clock cycle, the only place where drift can occur is the change in the symmetry of switching speed versus temperature.

Since each reset pulse is identical, the AD652 SVFC produces a very linear voltage-to-frequency conversion relationship. Also, since all reset pulses are gated by the clock, there is no problem with dielectric absorption, causing the duration of the reset pulse to be affected by the length of time since the last reset.

Figure 4 shows that the period between output pulses is limited to an exact multiple of the clock period. Assume that the input current is exactly one quarter of the reference current value. To achieve charge balance, the output frequency is equal to the clock frequency divided by four: one clock cycle for reset and three clock cycles for integration. As shown in Figure 5. If the input current increases by a small amount, the output frequency should also increase by a small amount. Initially, however, no output change was observed for a small increase in input current. The output frequency continues to run at one quarter of the clock, delivering the 250µA average to the summing junction. As the input current is slightly greater than this, charge builds up in the integrator and the sawtooth signal begins to drift downward. As the integrator sawtooth moves down, the comparator's threshold increases earlier in each successive cycle until finally, a full cycle is lost. When cycles are lost, the integration phase lasts for two cycles of the clock instead of the usual three. So, in a long string of divide-by-4, there will be occasional divide-by-3; the average of the output frequency is very close to a quarter of the clock, but the instantaneous frequency can be very different.

Therefore, it is very difficult to observe the waveform on the oscilloscope. During this time, the signal output by the integrator is a sawtooth wave, and its envelope is also a sawtooth wave. See Figure 6.

Another view is that the output is about a quarter of the frequency of the phase modulated clock. Constant frequency can be thought of as accumulating phase linearly at a rate of 2πf radians per second. Therefore, the average output frequency (a little over a quarter of the clock) needs to accumulate phase at a rate. However, since the SVFC runs at exactly one quarter of the clock, it does not accumulate enough phase (see Figure 7). When the difference between the desired phase (average frequency) and the actual phase is equal to 2π, step-by-step phasing is taken in the case of instantaneously making up the deficit. The output frequency is then a stable carrier phase modulated by the sawtooth signal (see Figure 7). The period of the sawtooth phase modulation is the time required to accumulate a 2π phase difference between the desired average frequency and one quarter of the clock frequency. The sawtooth phase modulation amplitude is 2π.

As a result of this synchronization, there is a limit to the rate at which data can be extracted from the serial bit stream produced by the svfc. The output pulses are usually counted during fixed gate intervals and the result is interpreted as the average frequency. The resolution of this measurement is determined by the clock frequency and gate time. For example, if the clock frequency is 4mhz and the gate time is 4.096ms, the maximum count of 8192 results from a full-scale frequency of 2mhz. Therefore, the resolution is 13 bits.

Elf

Since each reset pulse is only one clock cycle in length, the full-scale output frequency is equal to half the clock frequency. At full scale, the current steering switch spends half its time on the summing junction; therefore, 0.5 mA of input current can be balanced. In an overrange condition, the output of the integrator op amp drifts in the negative direction and the output of the comparator remains high. The logic circuit is simply divided by 2 of the clock state.

Dual Supply, Positive Input Voltage SVFC Connection

Figure 8 shows the AD652 connection scheme for the traditional dual-supply positive input mode of operation. The ±V range is ±6 V to ±18 V. When +V is below 9.0 V, as shown in Figure 8, three additional connections are required. The first connection is to short pin 13 to pin 8 (analog ground to -V) and add a pull-up resistor to +V (as shown in Figure 21). The pull-up resistor is determined by the following equation:

These connections ensure that the 5V reference is working properly. Connect pin 16 to pin 6 (as shown in Figure 21) to ensure that the integrator output ramps down enough to trip the comparator.

The CERDIP packaged AD652 accepts a 0 V to 10 V or 0 mA to 0.5 mA full-scale input signal. The temperature drift of the AD652 is specified for the 0 V to 10 V input range using an internal 20 kΩ resistor. Gain drift is reduced by up to 100 ppm/°C (tc of a 20 kΩ resistor) if a current input is used. If an external resistor is connected to pin 5 to establish a different input voltage range, it will cause drift such that the Tc of the external resistor is different from the Tc of the internal resistor. The external resistors used to establish the different input voltage ranges should be chosen to provide a full-scale current of 0.5 mA (ie, 10 kΩ from 0 V to 5 V).

SVFC connection for negative input voltage

A voltage negatively related to ground can be used as the input to the AD652 SVFC. In this case, pin 7 is grounded and the input voltage is applied to pin 6 (see Figure 9). In this mode, the input voltage can be as low as 4 V above -V. In this configuration, the input is high impedance and only the 20 Na (typ) input bias current of the op amp must be supplied by the input signal. This is in contrast to the more common positive input voltage configuration, which has an input impedance of 20 kΩ and requires a 0.5 mA source.

SVFC connection for bipolar input voltage

A bipolar input voltage of ±5 V can be adjusted by injecting 250 µA into pin 5 (see Figure 10). The -5 V signal provides a zero-sum current at the integrator summing junction, resulting in a zero output frequency; the +5 V signal provides a 0.5 mA (full-scale) sum current, resulting in a full-scale output frequency.

Using an external resistor to inject bias current has a certain effect on the bipolar bias temperature coefficient. The ideal transfer curve for a bipolar input is shown in Figure 11. The user actually has four choices when it comes to injecting bipolar bias current into the op amp's inverting input:

1. Use an external resistor for R and an internal 20 kΩ resistor for R (as shown in Figure 10).

2. Use internal 20 kΩ resistors for R and external R.

3. Use two external resistors.

4. R and R use two internal resistors (only for PLCC version).

As shown in Figure 11, option 4 provides the closest function to the ideal transfer function. Figure 12 shows the effect of the transfer relationship on the other three options. In the first case, the slope of the transfer function is independent of temperature. However, v (the input voltage required to generate an output frequency of 0 Hz) and f (the output frequency at v = 0 v) vary with the displacement of the transfer function parallel to the voltage axis with temperature. In the second case, f remains constant, but v varies with temperature as the transfer function rotates around f. In the third case, for the two external resistors, the v-point remains constant as the slope and offset of the transfer function vary with temperature. If the third option is selected, the user should select low drift, matched resistors. zero zero zero zero zero zero

The AD652 in the PLCC package provides additional input resistance not found on CERDIP packaged devices. These resistors provide the user with additional input voltage range. In addition to the 10v range provided using the on-chip resistors in the cerdip, the plcc also provides 8v and 5v ranges. Figures 13a to 13c show the correct connections for these ranges at positive input voltages. For negative input voltages, connect an appropriate resistor to analog ground and apply the input voltage to +input pin 6 of the op amp.

The bipolar input voltage can be adjusted by injecting 250µA into pin 5 using a 5V reference and an input resistor. For ±5 V or ±2.5 V ranges, the reference output (pin 20) should be connected to pin 10. The input signal should then be applied to pin 8 (for ±5 V signals) and pin 7 (for ±2.5 V signals). Input connections in the ±5V range are shown in Figure 13D. In the ±4V range, the input signal should be applied to pin 9 and pin 20 should be connected to pin 8.

Gain and offset calibration

The gain error of the AD652 is laser corrected to within ±0.5%. If higher accuracy is required, the internal 20 kΩ resistor must be paralleled with the 2 mΩ resistor to produce a parallel equivalent resistance 1% lower than the nominal 20 kΩ value. Full-scale adjustment is then done using a 500 Ω series trimmer. See Figures 14 and 15. When using a negative input voltage, this 500Ω trimmer is tied to ground and pin 6 is the input pin.

This gain trim should be done with an input voltage of 9 volts and the output frequency should be adjusted to 45% of the clock frequency. Adjusting the gain with a 10 V input is not practical since the device enters divide-by-2 mode in an input overrange condition; if the gain is too high, the output frequency is exactly half the clock frequency and will not be adjusted until the exact scale factor is reached will change with adjustment. Therefore, gain adjustment should be done at 9 V input.

The offset of the op amp can be trimmed to zero with the trim scheme shown in Figure 14 for the cerdip package and the plcc package shown in Figure 15. One way to trim the offset is to ground pin 7 (8) of the CERDIP (PLCC) device and observe the waveform at pin 4. If the bias voltage of the op amp is positive, the integrator is saturated and the voltage is on the positive rail. If the offset voltage is negative, there is a small effective input current that causes the AD652 to oscillate; a sawtooth wave is observed at pin 4. The potentiometer should be adjusted until the downward slope of this sawtooth becomes very slow and the frequency drops to 1 Hz or less. In analog-to-digital conversion applications, an easier way to adjust the offset is to apply a small input voltage, such as 0.01% of full scale, and adjust the potentiometer until the correct digital output is achieved.

gain performance

AD652 gain error is specified as the difference in slope between the actual transfer function and the ideal transfer function over the full-scale frequency range. Figure 16 shows a typical gain error change versus clock input frequency normalized to 100kHz. Figure 16 shows a typical gain change normalized to the original 100 kHz gain, if the necessary gate time is reduced by increasing the clock frequency after using the AD652 with a full-scale clock frequency of 100 kHz.

reference noise

The AD652 has an on-board precision buffered 5V reference voltage available to the user. In addition to being used to offset non-rotating comparator inputs in voltage-frequency mode, this reference can be used for other applications such as offsetting inputs to process bipolar signals and providing bridge excitation. It can source 10mA and sink 100µA and is short circuit protected. The reloading of the reference does not change the gain of the VFC, but does affect the external reference. For example, a 10mA load interacting with a typical output impedance of 0.3Ω changes the reference voltage by 0.06%.

Digital Interface Considerations

The AD652 clock input has a high impedance input with a threshold voltage of two diode voltages relative to digital ground (about 1.2V at room temperature).

When the clock input is low, 5 to 10 µA flows out of this pin. When the clock input is high, no current flows.

The frequency output is an open collector pulldown capable of sinking 10mA at a maximum voltage of 0.4V. This drives 6 standard TTL inputs. The open collector pull-up voltage can be as high as 36 volts above digital ground.

Component selection

The AD652 integrated capacitor should be 0.02µF. If a large amount of normal mode glitch (greater than 0.1V) is expected and the clock frequency is less than 500kHz, a 0.1µF integrated capacitor should be used. Mylar, polypropylene or polystyrene capacitors should be used.

An open-collector pull-up resistor should be chosen to provide a sufficiently fast rise time. At low clock frequencies (100 kHz), larger resistor values (several kΩ) and slower rise times can be tolerated. However, at higher clock frequencies (1 MHz), lower resistor values should be used. The loading of the logic input being driven must also be considered.

For example, if you want to drive two standard TTL loads, you have to sink 3.2 mA, leaving 6.8 mA for the pull-up resistors if you want to keep the maximum low-level voltage at 0.4 volts. So a 680Ω resistor will be chosen ((5V – 0.4V)/6.8mA) = 680Ω.

A one-shot capacitor controls the pulse width of the frequency output. Pulses are triggered by the rising edge of the clock signal. The delay time between the rising edge of the clock and the falling edge of the frequency output is typically 200 ns. The pulse width is 5ns/pf, the minimum width is about 200ns, and pin 9 is floating. If a single pulse period longer than the clock period is accidentally chosen, the pulse width defaults to the clock period. One trigger can be disabled by connecting pin 9 to +V (Figure 17); the output pulse width is then equal to the clock period. Activate the single shot by connecting a capacitor from pin 9 to +V, -V or digital ground (+V preferred) (Figure 18).

digital terrestrial

Digital ground can be at any potential between -V and (+V – 4 V). This is useful in systems with derived ground rather than rigid power supplies. For example, in a small isolated power circuit, typically only one power supply is generated, with ground set by a voltage divider tap. Such a ground cannot handle the large currents associated with digital signals. Using the AD652 SVFC, digital ground can be tied to –V for a reliable logic reference, as shown in Figure 19.

Single supply operation

In addition to connecting the digital ground to –V, you can also connect the analog ground to –V of the AD652. Therefore, the unit really works with a single supply voltage of 12 V to 36 V. Figure 21 shows a positive voltage input and Figure 20 shows a negative voltage input.

In Figure 21, the comparator reference is used as a derived ground; the input voltage is referenced to this point and to the op amp common mode (pin 6 connected to pin 16). Since the input signal source must source a full-scale signal current of 0.5 mA into pin 7, the exact same current must also be drawn from the input reference potential. Therefore, this current is provided by the 5V reference voltage.

In single-supply operation, an external resistor, R, is required between supply +V and the 5V reference output. This resistor should be selected so that about 500 microamps of current will flow during operation. For example, with a supply voltage of +15 V, choose a 20 kΩ resistor ((15 V – 5 V)/500 μA = 20 kΩ).

Figure 20 shows a negative voltage input configuration using the AD652 in single-supply mode. In this mode, the signal source drives the + input of the op amp, requiring only 20 mA (typ) compared to the 0.5 mA required for a positive input voltage configuration. The voltage at pin 6 may go as low as 4 V to ground (–V pin 8). Since the input reference voltage is 5.0 V above ground, this leaves a 1 V window for the input signal. To drive the integrating capacitor with 0.5mA full-scale current, an external 2 kΩ resistor must be provided. This results in a 2 kΩ resistor and a 1 V input range. The external 2 kΩ resistors should be low tc metal film types for lowest drift degradation. S

Inverter

The AD652 SVFC can also be used as a frequency-to-voltage converter. Figure 22 shows the connection diagram for the F/V conversion. In this case, the negative input of the comparator is pulsed. Either comparator input can be used so that input pulses of either polarity can be applied to f/v.

In Figure 22, the + input is tied to a 1.2V reference, and the low-level TTL pulse is used as the frequency input. The pulse on the falling edge of the clock must be low. On the subsequent rising edge, the 1 mA current source switches to the integrator summing junction and boosts the voltage at pin 4. The 1 mA current is turned off after one clock cycle due to the AND gate. The average current delivered to the summing junction varies from 0 mA to 0.5 mA; using an internal 20 kΩ resistor, this will result in a full-scale output voltage of 10 volts at pin 4.

The frequency response of the circuit is determined by the capacitor; the -3db frequency is just the rc time constant. There is a compromise between Ripple and Response. If low ripple is required, a large value capacitor (1µf) must be used; if fast response is required, a small capacitor (1nf minimum) is used.

The op amp can drive a 5 KΩ resistive load to 10 V with a positive 15 V supply. If a large load capacitance (0.01µf) must be driven, the load must be isolated with a 50Ω resistor as shown. Because the 50Ω resistor is 0.25% of full scale and the specified gain error for the 20kΩ resistor is 0.5%, this extra resistor will only increase the total gain error to 0.75% of maximum.

The circuit shown is unipolar and only allows 0 V to +10 V output. Integrator op amps are not general purpose op amps. Instead, it has been optimized for simplicity and high speed. The biggest difference between this amplifier and a general-purpose op amp is the lack of an integrator (or level-shifting) stage.

Therefore, the voltage on the output (pin 4) must always be more than 1 V positive than the voltage on the input (pins 6 and 7). For example, in F-to-V conversion mode, the op amp's non-vertical input (pin 6) is grounded, which means the output (pin 4) cannot go below -1V. As shown, proper operation of the circuit never requires a negative voltage at the output.

The second difference between this op amp and a general-purpose amplifier is that the output is only attenuated by 1.5 mA toward the negative supply. Aside from the 1mA current used for voltage-to-frequency conversion, the only pull-down supply is the 0.5mA supply. The op amp draws a lot of current from the positive supply and is internally protected by current limiting. When no external current is supplied, the op amp output can be driven to within 4V of the positive supply. When the supply is 10mA, the output voltage can be driven to within 6V of the positive supply.

Decoupling and Grounding

It is good engineering practice to use bypass capacitors on the supply voltage pins and insert small value resistors (10Ω to 100Ω) in the supply lines to provide a measure of decoupling between circuits in the system. A 0.1µf to 1.0µf ceramic capacitor should be used between the supply voltage pin and the analog signal ground for proper bypassing on the AD652.

Also, larger board-level decoupling capacitors of 1µF to 10µF should be placed relatively close to the AD652 on each supply line. This precaution is essential in high-resolution data acquisition applications, where one expects to take advantage of the full linearity and dynamic range of the AD652.

Separate digital and analog grounds are provided on the AD652. Only the emitter of the open-collector frequency output transistor and the clock input threshold return to digital ground. Only the 5V reference is connected to analog ground. The purpose of the two separate grounds is to allow isolation between the high-precision analog signal and the digital portion of the circuit. On digital ground, a lot of noise can be tolerated without compromising VFC accuracy. This ground noise is unavoidable when switching large currents associated with frequency output signals.

At high full-scale frequencies, a pull-up resistor of about 500Ω is necessary to obtain a rise time fast enough to provide a well-defined output pulse. This means, for example, from a 5 V logic supply, an open collector output would draw 10 mA. Due to the self-inductance of the wire, excessive switch current can cause ringing when running long distances to ground. For example, the inductance of a 20-gauge wire is about 20 milliamps per inch; at the end of a 12-inch 20-gauge wire, a current of 10 milliamps switches in 50 nanoseconds, producing a voltage spike of 50 millivolts. These types of switching transients are easily handled by the AD652's separate digital ground.

Interference caused by the radiation of these fast transient electromagnetic energy remains a problem. Typically, voltage spikes are produced by inductive switching transients; these spikes can capacitively couple to other parts of the circuit. Another problem is the ringing of the ground and power lines due to the distributed capacitance and inductance of the wires. This ringing can also couple disturbances into sensitive analog circuits. The best way to solve these problems is to properly bypass the logic power supply of the AD652 package. A 1µf to 10µf tantalum capacitor should be connected directly to the power side of the pull-up resistor and to pin 12 of digital ground. The pull-up resistor should be connected directly to frequency output pin 11. Lead lengths on bypass capacitors and pull-up resistors should be kept as short as possible. Capacitors source (or sink) current transients, and large AC signals flow in physically small loops through capacitors, pull-up resistors, and frequency output transistors. It is important that the physical size of the loop is small for two reasons: first, if the wire is short, the inductance is small, and second, the loop cannot radiate RFI effectively.

Digital ground (pin 12) should be connected separately to power ground. Note that the leads of the digital power supply only carry DC current. There may be a DC ground drop due to different currents returned on the analog and digital grounds. This is not a problem; these features greatly simplify power distribution and ground management in large systems. Proper grounding techniques require that the digital and analog grounds be returned to the power supply separately. Additionally, the signal ground must be directly referenced to the analog ground (pin 6) at the package. More information on proper grounding and interference reduction can be found in HWOrt's Noise Reduction Techniques in Electronic Systems (John Wiley, 1976).

Frequency output multiplier

When used with standard voltage-to-frequency converters, the AD652 can be used as a frequency output multiplier. Figure 23 shows the low-cost AD654 VFC as the AD652 clock input. The picture also shows the second ad652 in f/v mode. The AD654 is set up to produce an output frequency of 0 kHz to 500 kHz over an input voltage (V) range of 0 V to 10 V. This output frequency is multiplied from 0 kHz–500 kHz to 0 MHz–1 MHz using R4, C1, and the XOR gate.

This 1 MHz full-scale frequency is then used as the clock input to the AD652 SVFC. Since the full-scale output frequency of the AD652 is half the clock frequency, a 1 MHz fs clock frequency establishes a maximum output frequency of 500 kHz for the AD652 when its input voltage (V) is 10 V. Therefore, the user's output frequency ranges from 0 kHz to 500 kHz, which is proportional to the product of V and V.

This can be expressed in equation form, where f is the ad654 output frequency and f is the ad652 output frequency:

The range photo in Figure 24 shows the outputs of V and V (top two traces) and FV (bottom trace).

single line multiplex data transmission

It is often necessary to measure several different signals and relay the information to some remote location using minimal cables. Multiple AD652 SVFC devices can be used with polyphase clocks to combine these measurements for serial transmission and demultiplexing. Figure 25 shows a block diagram of a single-wire multiplexed data transmission system with high noise immunity. Figure 26, Figure 27, and Figure 30 show the svfc multiplexer, a typical data transfer scheme, and the svfc demultiplexer, respectively.

multiplexer

Figure 30 shows the SVFC multiplexer. The clock inputs for the multiple SVFC channels are generated by the TIM9904A 4-phase clock driver, and the frequency outputs are combined by tying all the frequency output pins together (wired or connected). A single shot in the AD652 sets the pulse width of the frequency output pulse to be slightly shorter than a quarter of the clock period. Synchronization is achieved by applying one of the four available phases to a fixed ttl one shot ('121) and combining the output with an external transistor.

The width of the sync pulse is shorter than the width of the frequency output pulse to facilitate decoding the signal. The RC delay network on the one-shot input provides a slight delay between the rising edge of the clock and the sync pulse to match the AD652's 150ns delay between the rising edge of the clock and the output pulse.

transmitter

The multiplexed signal can be sent in any way that suits the task at hand. Pulse transformers or opto-isolators can provide galvanic isolation; extreme high-voltage isolation or transmission through harsh RF environments can be achieved through fiber optic links; telemetry can be achieved through wireless links. The circuit shown in Figure 27 uses the EIA RS-422 standard to transmit digital data over balanced lines. Figure 24 shows the waveforms of the four clock phases and multiplexed output signals. Note that sync pulses are present on every clock cycle, but data pulses are not more frequent than other clock cycles because the maximum output frequency from the svfc is half the clock frequency. The clock frequency used in this circuit is 819.2 kHz, which provides more than 16 bits of resolution if a gate time of 100 ms is allowed to calculate the pulses at the decoded output frequency.

SVFC Demultiplexer

The demultiplexer required to separate the combined signal is shown in Figure 30. The phase-locked loop drives another 4-phase clock chip to lock the reconstructed clock signal. Sync pulses differ from data pulses by their shorter duration. Each falling edge on the multiplexed input signal triggers a pulse; at the end of the first pulse, the multiplexed input signal is sampled by the d-type flip-flop. if

The signal is high, the pulse is short (sync pulse), and the Q output of the D flip-flop goes low. The d-flop is cleared after a short time (two gate delays) and the clock is rebuilt as a short, low-pass stream of pulses. If the multiplexed input is a data pulse, then when the d-flop samples at the end of a shot period, the signal is still low and no pulse appears at the reconstructed clock output. See Figure 29.

If a single frequency signal needs to be recovered, the multiplexed input is sampled with a d-flop at the appropriate location, determined by the rising edges of different phases generated by the clock chip. These frequency signals can be calculated as a ratio relative to the reconstructed clock, so it is not even necessary for the transmitter to be crystal controlled as shown in Figure 30.

Analog signal reconstruction

If the analog voltage needs to be reconstructed from the multiplexed signal, three additional AD652 SVFC devices are used as frequency-to-voltage converters, as shown in Figure 31. The comparator inputs of all devices are tied together, the "+" input is held at the 1.2v ttl threshold, and the "-" input is driven by multiple inputs. The three clock inputs are

Driven by the _ output of the clock chip. Remember, the data at the comparator input of the svfc is loaded on the falling edge of the clock signal and shifted up on the next rising edge. Note that the frequency signal for each data channel is available at the frequency output pins of each fvc.

Isolated front end

In some applications it may be desirable to have complete galvanic isolation between the analog signal being measured and the digital portion of the circuit. The circuit shown in Figure 32 is powered from a 5V supply and provides a self-contained, fully isolated analog measurement system. Power to the AD652 SVFC is provided by a chopper and transformer and is regulated to 15 V.

The chopper frequency and the AD652 clock frequency are both 125 kHz and the clock signal is relayed to the SVFC through a transformer. The frequency output signal is relayed through an opto-isolator and locked into a d-flip-flop. The chopper frequency is generated by the AD654 VFC and divided by 2 to develop the differential drive of the chopper transistor and ensure an accurate 50% duty cycle. A pull-up resistor on the D flip-flop output provides the chopper with a well-defined high-level voltage to equalize the drive in each direction. The 10µH inductance in the 5 V lead on the primary side of the transformer is necessary to balance any remaining unbalance in the driver every half cycle, thus preventing core saturation. The primary capacitor resonates the system so that with a light secondary load, the waveform is sinusoidal and the clock frequency is relayed to the SVFC. To adjust the chopper frequency, disconnect any load on the secondary supply and adjust the supply current drawn by the AD654 from the 5 V supply to the minimum value.

AD conversion

While performing AD conversion, the output pulses of the VFC are counted at a fixed gate interval. To achieve the maximum performance of the AD652, the fixed gate spacing should be generated using a multiple of the SVFC clock input. Counting in this way eliminates any errors caused by the clock (whether jitter, drift over time or temperature, etc.) because it is the ratio of the clock and output frequency being measured.

The resolution of the ad conversion measurement is determined by the clock frequency and gate time. For example, if 12-bit resolution is required and the clock frequency is 1 mhz (resulting in an ad652 fs frequency of 500 khz), the gate times are:

where n is the total number of codes for a given resolution.

Figure 33 shows the AD652 SVFC as an AD converter in block diagram form.

To provide ÷2n blocks, a microcontroller counter such as the 4020b can be used. The 4020B is a 14-stage binary ripple counter, it has a clock and master reset input, buffered outputs from the first stage and the last 11 stages. The output of the first stage is f÷2=f/2, and the output of the last stage is f÷2=f/16384. Therefore, using this microcontroller counter as a ÷2n block, a resolution of 13 bits can be obtained. Higher resolution can be achieved by cascading data type flip-flops or another 4020B with a counter.

Triangle modulator

The circuit in Figure 34 shows the ad652 configured as a delta modulator. A reference voltage is applied to the input of the integrator (pin 7) which sets the steady state output frequency to half the AD652's full scale frequency (1/4 of the clock frequency). When a 0 V to 10 V input signal is applied to the comparator (pin 15), the output of the integrator tries to track the signal. For the input in idle state (DC), the output frequency is half of full scale. For forward signals, the output frequency is between half and full scale; for reverse signals, the output frequency is between zero and half full scale. The output frequency corresponds to the slope of the comparator input signal.

Since the output frequency corresponds to the slope of the input signal, the delta modulator acts as a differentiator. Therefore, a delta modulator is a straightforward way to find the derivative of a signal. This is useful in systems where, for example, there is a signal corresponding to velocity and acceleration needs to be determined.

Figure 35 is a range photograph showing a 20kHz, 0V to 10V sine wave used as a comparator input and its ramp approximation at the integrator output. The clock frequency is 2mhz and the integrating capacitor is 360pf. Figure 36 shows the same input signal and its ramp approximation, and the output frequency corresponding to the derivative of the input signal. In this case the clock frequency is 50khz.

The choice of integrated capacitor is mainly determined by the input signal bandwidth. Figure 37 shows this relationship. Note that as the value of c decreases, the magnitude of the ramp approximated by the integrator becomes larger. This can be compensated by increasing the clock frequency. The effect of clock frequency on ramp size is shown in Figure 35 and Figure 36.

Bridge sensor interface

The circuit in Figure 38 illustrates a simple interface between the AD652 and a bridge sensor. The AD652 is an ideal choice because its buffered 5V reference can be used as bridge excitation to scale out errors related to gain drift. This reference supplies at least 10mA of external current, which is sufficient for bridge resistances of 600Ω and above. For example, if the bridge resistance is 120Ω or 350Ω, an external pull-up resistor (R) is required. R and can be calculated using the following formula:

An instrumentation amplifier is used to condition the bridged signal before presenting it to the SVFC. Due to its high common-mode rejection ratio, the AD652 minimizes common-mode error and can be set to any gain between 1 and 10,000 via three resistors, simplifying scaling of the part's nominal 10V input range.

When choosing these resistors, the following equations should hold:

Where 10 kΩ≤r≤20 kΩ, v is the maximum output voltage of the bridge.

The bridge output may be unipolar, like most pressure sensors, or bipolar, like some strain measurements. The reference input of the AD625 (pin 7) is only grounded if the signal is unipolar. However, if the bridge has a bipolar output, the AD652 reference can be tied to pin 7, converting the 5v signal (after gain) to the svfc's 0v to +10v input.