feature:

Serial digital data link requires few I/O pins; analog input track/hold functionality; 2-, 4-, or 8-channel input multiplexer options with address logic; 0V to 5V analog input range with single 5V supply; no zero-scale or full-scale adjustment required; TTL/CMOS input/output compatible; on-chip 2.6V bandgap reference; 0.3″ standard width 8-, 14-, or 20-pin PDIP packages; 14-pin, 20-pin small outline packages .

application:

Digital automotive sensors; process control monitoring; remote sensing in noisy environments; instrumentation; test systems; embedded diagnostics.

Main Specifications:

Resolution: 8bit; Conversion Time (fc = 1MHz): 8ms (max); Power Consumption: 20mW (max); Single Supply: 5VDC ('5%); Total Unadjusted Error: lsb and 1lsb ; No over-temperature missing code.

describe

The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 channels. Serial I/Os are configured to comply with the NSC Microwire serial data exchange standard, which facilitates interfacing with COPS to a range of controllers that can easily interface with standard shift registers or microprocessors.

The ADC08034 and ADC08038 provide 2.6V band-gap derived references. For over-temperature devices that provide specific voltage reference performance, see ADC08131, ADC08134, and ADC08138. Track/Hold function allows positive input to change during actual A/D conversion. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. Also, input voltage spans as small as 1V can be accommodated.

Absolute Maximum Ratings

(1) Unless otherwise specified, all voltages are measured as AgNd=dGnd=0 Vdc.

(2) Absolute maximum ratings indicate the limit of possible damage to the device.

(3) If military/aviation specific equipment is required, please contact Texas Instruments sales office/distributor for availability and specifications.

(4) When the input voltage vin of any pin exceeds the power supply (vin<(agnd or dgnd) or vin>vcc), the current of this pin should be limited to 5ma. The 20mA maximum package input current rating limits the pin count for 5mA input current to 4 pins.

(5) The maximum power consumption must be reduced at high temperature and determined by Tjmax, θja and ambient temperature Ta. The maximum allowable power loss at any temperature is Pd=(Tjmax-Ta)/θJa or the value given in Absolute Maximum Ratings, whichever is lower. For these devices, Tjmax=125°C. Typical thermal resistances (θja) for these parts when board mounted are as follows: ADC08031 and ADC08032 with case and CIN suffix 120°C/W, ADC08038 with CIN suffix 80°C/W. ADC08031 with CIWM suffix 140°C/W, ADC08032 140°C/W, ADC08034 140°C/W, ADC08038 with CIWM suffix 91°C/W.

(6) Human body model, 100 pf capacitor is discharged through 1.5 kΩ resistor.

Operating Rating

(1) The working rating indicates the working conditions of the equipment. These ratings do not guarantee specific performance limits. See Electrical Characteristics for guaranteed specifications and test conditions. Guaranteed specifications apply only to the test conditions listed. Certain performance characteristics may be degraded when the device is not operated under the listed test conditions.

(2) Unless otherwise specified, all voltages are measured according to AgNd=dGnd=0 Vdc.

Electrical Characteristics

The following specifications apply for VCC=VREF=+5 Vdc and FCLK=1 MHz unless otherwise specified. Limits in bold apply to Ta=Tj=Tmin to Tmax; all other limits Ta=Tj=25°C.

(1) The typical data is Tj=25°C, which represents the most likely parameter norm.

(2), specified as AOQL (average delivery quality level).

(3) The total unadjusted error includes offset, full scale, linearity, and multiplexer.

(4), ADC08032 cannot be tested.

(5) For the vehicle identification number (-≥ vehicle identification number (+), the digital code is 0000 0000. Two on-chip diodes are connected to each analog input terminal (see block diagram), and the analog input terminal will conduct the analog input voltage in the forward direction. , one diode goes below ground, or one diode goes above the VCC supply. When testing at low VCC levels (like 4.5V), a high level analog input (like 5V) can cause the input diodes to conduct, especially At high temperatures this will cause near full scale analog input errors. The specification allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed 50 mV of the supply voltage, the output code will be correct .Exceeding this range on an unselected channel will corrupt the reading of the selected channel. Therefore, a minimum supply voltage of 4.950 VDC is required to achieve an absolute input voltage range of 0 to 5 VDC over temperature variations, initial tolerances, and load conditions .)

(6) Measure the leakage current of the channel after selecting the single-ended channel and turning off the clock. For non-channel leakage current, two cases should be considered: one, when the selected channel is connected high (5 Vdc) and the remaining seven non-channels are connected low (0 Vdc), the total current through the non-channel is measured; the other In this way, when the selected channel is connected low and the non-channel is connected high, the total current through the non-channel is measured again. The two conditions used to determine the channel leakage current are the same, except that the total current through the selected channel is measured.

(7) For ADC08032, VREFin is internally connected to VCC, therefore, for ADC08032, the reference current is included in the power supply current.

Electrical Characteristics

The following specifications apply for VCC=VREF=+5 Vdc and TR=TF=20 ns unless otherwise specified. Limits in bold apply to Ta=Tj=Tmin to Tmax; all other limits Ta=Tj=25°C.

(1) The typical data is Tj=25°C, which represents the most likely parameter norm.

(2), specified as AOQL (average delivery quality level).

(3), 40% to 60% duty cycle range ensures normal operation at all clock frequencies. If the duty cycle of the available clock exceeds these limits, the minimum clock high or low time must be at least 450 ns. The maximum time the clock can be high or low is 100µs.

(4) Since the data msb first is the output of the comparator used in the successive approximation loop, an extra delay is built in to allow the comparator response time.

Function description

Multiplexer addressing

These converters are designed with a built-in sample-and-hold comparator structure that provides a differential analog input for conversion through a successive approximation procedure.

The actual converted voltage is always the difference between the specified "+" input terminal and "-" input terminal. The polarity of each pair of input terminals represents the most positive line expected by the converter. If the specified "+" input voltage is less than the "-" input voltage, the converter will respond with an all-zero output code.

A unique input multiplexing scheme is used to provide software-configurable single-ended, differential or pseudo-differential operation for multiple analog channels (it will convert the voltage difference between any analog input and the common terminal). This input flexibility greatly simplifies the analog signal conditioning required for sensor-based data acquisition systems. One converter package can now handle ground-referenced and true differential inputs as well as signals with arbitrary reference voltages.

A specific input configuration is assigned during the mux addressing sequence before starting a conversion. The MUX address selects which analog input to enable, and whether that input is single-ended or differential. Differential inputs are limited to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a differential pair, but channel 0 or channel 1 cannot act differentially with any other channel. In addition to selecting differential mode, polarity can also be selected. Channel 0 can be selected as a positive input, channel 1 can be selected as a negative input, and vice versa. This programmability is best illustrated by the mux addressing codes for the various product options shown in the table below.

The mux address is transferred into the converter via the di line. Since the ADC08031 contains only one differential input channel with fixed polarity assignment, addressing is not required.

The common input line (COM) on the ADC08038 can be used as a pseudo differential input. In this mode, the voltage on this pin is treated as a "-" input for any other input channel. This voltage does not have to be analog ground; it can be any reference voltage common to all inputs. This feature is most useful in single-supply applications, where analog circuits may be biased to a potential other than ground and the output signal is referred to as that potential.

Since the input configuration is software controlled, it can be modified as needed before each conversion. One channel can be treated as a single-ended ground-referenced input for one conversion; it can then be reconfigured to be part of another converted differential channel. Figure 19 illustrates the input flexibility that can be achieved.

The analog input voltage of each channel can go from 50mV below ground to 50mV above VCC (typically 5V) without degrading conversion accuracy.

digital interface

One of the most important features of these converters is their serial data link to the control processor. Using the serial communication format provides two very important system improvements; it allows many functions to be contained in a small package, and it eliminates the transmission of low-level analog signals by positioning the converter on the analog sensor; Noise immune digital data is transmitted back to the main processor.

To understand the operation of these converters, it is best to refer to the timing and functional block diagrams and follow the complete conversion sequence. For clarity, separate timing diagrams are shown for each device.

1. Start a conversion by pulling the CS (chip select) line low. This line must remain low throughout the conversion process. The converter is now waiting for the start bit and its mux assignment word.

2. On each rising edge of the clock, the state of the data in (di) row is clocked into the mux address shift register. The start bit is the first logical "1" that occurs on this line (all leading zeros are ignored). After the start bit, the converter expects the next 2 to 4 bits to be the mux assignment word.

3. When the starting position is shifted to the starting position of the mux register, the input channel is allocated and the conversion is about to start. An interval of one and a half clock cycles is automatically inserted (when nothing happens) to allow the selected mux channel to stabilize. At this point, the sars line goes high, indicating that a conversion is in progress, and the di line is disabled (no longer accepting data).

4. The data out (do) line is now out of tri-state and provides leading zeros for this one clock cycle of the mux.

5. During conversion, the output of the sar comparator indicates whether the analog input is greater (high) or less than (low) a series of continuous voltages generated from within the rated capacitor array (first 5 bits) and resistor ladder (last 3 bits). After each comparison, the output of the comparator is sent to the do line on the falling edge of clk. This data is the result of the conversion being shifted out (msb first) and can be read immediately by the processor.

6. After [1] clock cycles, the conversion is complete. The sars line returns low, indicating this later half-clock cycle.

7. The data stored in the successive approximation register is loaded into the internal shift register. If the programmer wishes, the data can be provided in lsb first format [this utilizes the shift enable(se) control line]. On the ADC08038, the SE line is pulled out, and if kept high, the LSB value remains valid on the DO line. When se is forcibly lowered, data is first clocked by lsb. On devices that do not include the SE control line, the data lsb first is automatically shifted out of the do line after the msb first data stream. Then the do line goes low and stays low until cs returns high. The ADC08031 is an exception because its data is output only in msb first format.

reference factor

The voltage vrefin applied to the reference input on these converters defines the voltage range of the analog input (the difference between vin(max) and vin(min) for the 256 possible output codes). This device can be used in both ratiometric measurement applications and systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance (as low as 1.3kΩ). This pin is the top of the resistor divider string and capacitor array used for successive approximation conversion.

In a ratiometric measurement system, the analog input voltage is proportional to the A/D reference voltage. This voltage is usually the system power supply, so the VREFin pin can be connected to VCC (done inside the ADC08032). This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, maintaining the same output code for a given input condition.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between very specific voltage limits. For the ADC08034 and ADC08038, a bandgap reference of 2.6V(1) is tied to VREFOUT. This can be bound to vrefin. A 100µf capacitor is recommended to bypass Vrefout. The LM385 and LM336 reference diodes are good low current devices to use with these converters.

The maximum value of the reference voltage is limited to the VCC supply voltage. However, the minimum value can be very small (see Typical Performance Characteristics) to allow direct conversion of the sensor output, providing an output span of less than 5V. Due to the increased sensitivity of the converter (1lsb equals vref/256), special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span.

(1) The typical data is Tj=25°C, which represents the most likely parameter norm.

analog input

The most important feature of these converters is that they can be located at an analog signal source and communicate with a control processor with a high noise immunity serial bit stream over a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy at the beginning, or possibly on a large common-mode voltage, there are several words in sequence.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is 1/2 the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

where: fcm is the frequency of the common mode signal; Vpeak is its peak voltage value, and fclk is the A/D clock frequency.

In order for a 60Hz common-mode signal to produce a 1/4 LSB error (≈5mV) when the converter is running at 250kHz, it must peak at 6.63V, which will be greater than the allowable value when it exceeds the maximum analog input limit.

The source resistance limit is important for the DC leakage current into the multiplexer. Bypass capacitors should not be used if the supply resistance is greater than 1kΩ. Worst-case leakage current ±1µA over temperature will result in a 1MV input error with a 1KΩ source resistance. If a high impedance signal source is required, an op amp rc active low pass filter can provide impedance buffering and noise filtering.

optional adjustment

zero error

The zero point of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value vin(min) is not grounded. By biasing any VIN (negative) input at that VIN (min) value, the converter can output a 0000 0000 numeric code for this min input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (vin) input. Zero error is the difference between the actual DC input voltage and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.0 0VDC) required to just convert the output digital code from 0000 to 0000 0001 .

full scale

Full-scale adjustment can be done by applying a differential input voltage (1.5 lsb lower from the desired analog full-scale voltage range) and then adjusting the size of the vrefin input (or vcc for adc08032) of the digital output code from 1111110 to 1111111.

Adjustment of any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. Apply a vin(+) equal to the desired zero reference voltage plus 1/2 LSB (where 1 LSB = analog span / 256 is used to calculate the LSB of the desired analog span) at the selected "+" input voltage, the zero reference voltage at the corresponding "-" input should then be adjusted to obtain a 00hex to 01hex code transition.

A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by:

where: vmax = high end of analog input range, and vmin = low end of analog range (offset zero).

The vrefin (or vcc) voltage is then adjusted to provide a code change from fhex to ffhex. This completes the adjustment process.

application