feature:

10 MHz to 300 MHz input frequency; 6.8 kHz to 270 kHz output signal bandwidth; 7.5dB single-sideband noise figure (SSB NF); 7.0 dBm input third-order intercept (IIP3); AGC free range up to -34 dBm 12 dB continuous AGC range; 16dB front-end attenuator; baseband I/Q 16-bit (or 24-bit) serial digital output; lo and sample clock synthesizer; programmable decimation factor, output format, AGC and synthesizer settings; 370Ω input impedance; 2.7 V to 3.6 V supply voltage; low current consumption: 17 mA; 48-lead LFCSP package.

application:

Multimode narrowband radio products; analog/digital UHF/VHF FDMA receivers; Tetra Pak, APCO25, GSM/EDGE; portable and mobile radio products; satellite communication terminals.

General Instructions

The AD9864 is a general-purpose IF subsystem that digitizes low-level, 10 MHz to 300 MHz IF inputs with signal bandwidths ranging from 6.8 kHz to 270 kHz. The AD9864's signal chain consists of a low noise amplifier (LNA), a mixer, a bandpass sigma-delta analog-to-digital converter (ADC), and a decimation filter with a programmable decimation factor. An automatic gain control (AGC) circuit provides 12dB of continuous gain adjustment of the AD9864. Auxiliary blocks include clock and local oscillator (lo) synthesizers.

The high dynamic range of the AD9864 and the inherent antialiasing provided by the bandpass Σ-∏ converter allow the device to handle blocking signals up to 95 dB stronger than the desired signal. This property generally reduces the cost of the radio by reducing IF filtering requirements. In addition, it supports multimode radios of different channel bandwidths, allowing if filters to be specified for the maximum channel bandwidth.

The SPI port programs many parameters of the AD9864, allowing the device to be optimized for any given application. Programmable parameters include synthesizer divider ratio, AGC decay and attack/decay time, received signal strength level, decimation factor, output data format, 16dB attenuator and selected bias current.

The AD9864 is packaged in a 48-wire LFCSP and can be powered from a single 2.7 V to 3.6 V supply. Total power consumption is typically 56mW, with a power-down mode available through the serial interface.

Single Sideband Noise Figure (SSB NF) Noise figure (nf) refers to the degradation of the signal-to-noise ratio (in decibels) of an IF input signal after passing through a component or system. It can be represented by the equation:

The term ssb applies to heterodyne systems that contain mixers. It means that the desired signal spectrum is only on one side of the lo frequency (i.e. the single sideband); therefore, a noise-free mixer has a noise figure of 3db.

The SSB noise figure of the AD9864 is determined by:

where: p is the input power of the unmodulated carrier; bw is the noise measurement bandwidth; -174 dBm/Hz is the thermal noise floor at 293 K.

Signal-to-noise ratio is the measured signal-to-noise ratio of the AD9864 in decibels. Note that p was set to -85 dbm to minimize any degradation of the measured SNR due to phase noise from the RF and LO signal generators. The if frequency, clk frequency and decimation factor are chosen to minimize any spurious components falling within the measurement bandwidth. Also note that the datasheet specification uses a 10 kHz bandwidth. All noise figures mentioned in this data sheet refer to single sideband noise figures.

Enter the third-order intercept (IIP3)

iip3 is an advantage number used to determine the susceptibility of a component or system to intermodulation distortion (imd) from its third-order nonlinearity. Two unmodulated carriers were injected with the specified frequency relationship (f1 and f2) into a nonlinear system showing third-order nonlinearity producing imd components at 2f1-f2 and 2f2-f1. iip3 graphically represents the extrapolated intersection of the carrier input power and the third-order imd component when plotted in db. The power difference (d in dbc) between the two carriers and the resulting third-order imd component can be determined by the equation:

Dynamic Range (DR)

Dynamic range is the measurement of a small target input signal (ptarget) in the presence of a large number of unwanted interfering signals (pinter). Often, a large signal can degrade some unwanted characteristic of a component or system, preventing it from correctly detecting smaller target signals. For the AD9864, an increased VGA attenuation setting typically reduces the noise figure, limiting its dynamic range.

The test method of AD9864 is as follows. Input a small target signal (unmodulated carrier) at the center of the IF frequency and adjust its power level (ptarget) to achieve

6 dB target. Then, before injecting the jamming signal, the power of the signal is increased by 3db. The offset frequency of the interfering signal is chosen so that the aliasing produced by the response of the decimation filter and the phase noise from lo (due to reciprocal mixing) do not fall back into the measurement bandwidth. For this, an offset of 110 kHz was chosen. The interfering signal (also an unmodulated carrier) is then injected into the input and its power level is increased to the point (p) where the target signal SNR drops to 6db. The dynamic range is determined by the equation:

Note that the AGC of the AD9864 is enabled for this test.

If you enter a clip point

The if input clip point is defined as the input power that causes the digital output level to be 2db below full scale. Unlike other linear components that typically exhibit soft compression (characterized by their 1db compression point), ADCs exhibit hard compression when their input signal exceeds their rated maximum input signal range. For the AD9864, which contains a Σ-∏ ADC, hard compression must be avoided as it can cause severe signal-to-noise degradation.

Serial Peripheral Interface (SPI)

spi is a bidirectional serial port. It is used to load configuration information into the registers listed in Table 6 and read back their contents. Table 6 provides a list of registers that can be programmed through the SPI port. Addresses and default values are given in hexadecimal.

theory of operation

The AD9864 is a general-purpose narrowband IF subsystem that digitizes low-level IF inputs from 10 MHz to 300 MHz with signal bandwidths ranging from 6.8 kHz to 270 kHz. The AD9864's signal chain consists of an LNA, a mixer, a bandpass Σ-∏ ADC, and a decimation filter with a programmable decimation factor.

The input lna is a fixed gain block with an input impedance of approximately 370Ω 1.4 pf. The LNA inputs are single-ended and self-biased, allowing AC-coupled inputs. The LNA can be disabled via the serial interface, providing a fixed 16 dB attenuation to the input signal.

The LNA drives the input port of a Gilbert-type active mixer. The mixer lo port is driven by an on-chip lo buffer that can be driven externally, single-ended or differentially. The lo buffer input is self-biased, allowing the lo input to be AC coupled. The open-collector output of the mixer drives an external resonant cavity consisting of a differential LC network tuned to the intermediate frequency of a bandpass Σ-∏ ADC.

The external differential LC box forms the resonator for the first stage of the bandpass Σ-∏ ADC. The slot lc value must be chosen for a center frequency of f/8, where fclk is the sampling rate of the ADC. The FCLK/8 frequency is the intermediate frequency digitized by a bandpass Σ-∏ ADC. On-chip calibration allows for standard tolerance inductor and capacitor values. Calibration is usually performed once at power up. clock

The ADC contains a sixth-order, multi-bit bandpass sigma-∏ modulator to achieve very high instantaneous dynamic range over a narrow frequency band centered at F/8. The modulator output is mixed in quadrature with baseband and filtered through three cascaded linear-phase fir filters to remove out-of-band noise. The first fir filter is a fixed, multiplied by 12, using a four-shot comb filter. The second fir filter also uses a fourth-order comb filter with programmable decimation from 1 to 16. The third level fir can be programmed to be a decimation of 4 or 5. The clock cascade decimation factor is programmable between 48 and 960. The decimation filter data is output through the chip's synchronous serial interface (ssi).

Additional features built into the AD9864 include lo and clock synthesizers, programmable AGC, and a flexible synchronous serial interface for output data.

The local oscillator synthesizer is a programmable phase locked loop (pll) consisting of a low noise phase frequency detector (pfd), a variable output current charge pump (cp), a 14-bit reference divider, a and b counters and a dual-modulus prescaler. The user simply adds the appropriate loop filter and VCO to complete the operation.

The clock synthesizer is equivalent to the lo synthesizer, but with the following differences: (1), does not include a prescaler or counter. (2) It includes a negative resistance core for generating VCO.

The AD9864 contains a variable gain amplifier (VGA) and a digital VGA (DVGA). Both can be operated manually or automatically. In manual mode, each gain is programmed via SPI. In automatic gain control mode, the gain is automatically adjusted to ensure that the ADC does not get stuck and that the rms output level of the ADC is equal to the programmable reference level.

The attenuation range of the vga is 12db, which is achieved by adjusting the full-scale reference level of the adc. The dvga gain is achieved by scaling the output of the decimation filter. In narrowband applications requiring 16-bit i and q data formats, dvga is most useful in extending dynamic range.

SSI offers a programmable frame structure allowing 24-bit or 16-bit i and q data, and flexibility by including attenuation and rssi data if desired.

Serial Port Interface (SPI)

The serial port of the AD9864 has 3-wire or 4-wire SPI capability, allowing read/write access to all registers that configure the internal parameters of the device. The default 3-wire serial communication port consists of clock (PC), peripheral enable (PE), and bidirectional data (PD) signals. The inputs to PC, PE, and PD contain a Schmitt trigger with a nominal 0.4V hysteresis centered on the digital interface supply (ie, VDDH/2).

The 4-wire spi interface can be enabled by setting the msb of the ssicrb register (register 0x19, bit 7) and register 0x3A to 0x00, so that the output data only appears on the doutb pins and the pd pins are used only as input pins . Note that systems sharing the SPI output lines may experience bus contention since the default power-up state sets doutb low. To avoid any bus contention, the doutb pin can be tri-stated by setting the fourth control bit in the three status bits (Register 0x3b, Bit 3). This bit can then be toggled to access the shared spi output line.

Every read and write SPI operation must be accompanied by an 8-bit instruction header. Auto-increment mode is only supported for write operations, allowing the entire chip to be configured in a single write operation. The command header is shown in Table 7. It includes a read/don't write indicator bit, six address bits, and a don't care bit. For read and write operations, the data bits immediately follow the instruction header. Note that address and data are always given msb first.

Figure 29 illustrates the timing requirements for write operations to the SPI port. The data (pd) associated with the instruction header is read on the rising edge of the clock (pc) after the peripheral enable (pe) signal goes low. To initiate a write operation, the read/no write bit is set low. After reading the instruction header, the eight data bits associated with the specified register are shifted into the data pin (pd) on the rising edge of the next eight clock cycles. PE remains low during surgery and rises at the end of metastases. If pe rises before eight clock cycles have elapsed, the operation is aborted. If pe is held low for another eight clock cycles, the destination address is incremented and another eight bits of data are shifted in. Likewise, if pe rises early, the current byte is ignored. By using this implicit addressing mode, the chip can be configured for a single write operation. Registers identified as frequently updated, i.e. those related to power control and AGC operation, have been allocated to adjacent addresses to minimize the time required to update them. Note that multibyte registers are big endian (the most significant byte has a lower address) and are updated when the least significant byte is written.

Figure 30 and Figure 31 illustrate the timing of 3-wire and 4-wire spi read operations. Although ad9864 does not require read access to function properly, it is often useful during the product development phase or for system authentication. Note that the readback enable bit (Register 0x3A, Bit 3) must be set for read operations with a 3-wire SPI interface. For 4-wire SPI operation, this bit remains low (Register 0x3A = 0x00), but DOUTB is enabled through the SSICRB register (Register 0x19, Bit 7). Note that for the 4-wire spi interface, the 8 data bits appear on the doutb pin with the same timing relationship as the data bits appearing on the pd in the case of the 3-wire spi interface.

The data (pd) associated with the instruction header is read on the rising edge of the clock (pc) after the peripheral enable (pe) signal goes low. If the read/no write indicator is set high, a read operation is performed. After reading the address bits of the instruction header, the eight data bits associated with the specified register are shifted out of the data pin (pd) on the falling edge of the next eight clock cycles. After the last data bit has been shifted out, the user must return pe high, causing PD to tri-state (for 3-wire chassis) and return to its normal state as an input pin. Since read operations do not support auto-increment mode, each register read operation requires an instruction header, and pe must return high before initiating the next read operation.

power-on reset

When the VDDD supply exceeds the threshold, the SPI registers are automatically set to their default settings at power-up. This ensures that the AD9864 is in a known state and in standby for the lowest power consumption. In the unlikely event that the spi registers have not been reset to their default settings, an equivalent software reset by writing 0x99 to register 0x3f can be used as the first spi write command for extra assurance .

Synchronous Serial Interface (SSI)

The AD9864 provides a high degree of programmability for its SSI output data format, control signals, and timing parameters to accommodate various digital interfaces. In the 3-wire digital interface, the AD9864 provides the frame synchronization signal (fs), clock output (clkout), and serial data stream (douta) signals to the host device. In a 2-wire interface, frame synchronization information is embedded into the data stream, so only the clkout and doota output signals are provided to the host device. The ssi control registers are ssicra, ssicrb, and ssiord.

The main output of the AD9864 is the converted i and q demodulated signals available from the ssi port as a serial bit stream contained within the frame. The output frame rate is equal to the modulator clock frequency (f) divided by the decimation factor of the digital filter programmed in the Decimator Register (0x07). The bitstream consists of an i-word followed by a q-word, where each word is 24 or 16 bits long and given msb first in two's complement. Two optional bytes may also be included in the ssi frame following the q-word. One byte contains the AGC attenuation and the other byte contains the clock byte contains the count of modulator reset events and an estimate of the received signal amplitude (relative to the full scale of the AD9864 ADC). Figure 32 shows the structure of the ssi data frame in multiple ssi modes.

If the eagc bit of ssicra is set, two optional bytes are output. The first byte contains the 8-bit attenuation setting (0=no attenuation, 255=24 dB attenuation), while the second byte contains a 2-bit reset field and a 6-bit received signal strength field. The reset field contains the number of modulator reset events since the last report, with a saturation value of 3. The received signal strength (rssi) field is a linear estimate of the signal strength at the output of the first decimation stage; 60 corresponds to a full-scale signal.

If the aagc bit of ssicra is not set, the two option bytes follow the i and q data as a 16-bit word. If the aagc bit is set, the two bytes follow the i and q data in an alternating fashion. In this alternate agc data mode, the lsb of the byte containing the agc decay is 0, and the lsb of the byte containing the reset and rssi information is always 1.

In a 2-wire interface, the embedded frame sync bit (EFS) in the ssicra register is set to 1. In this mode, frame information is embedded into the data stream, each 8-bit data is surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. fs is kept low or tri-stated (default) depending on the state of the sfst bit. Other control bits can be used to invert the frame sync (sfsi), to delay the frame sync pulse by one clock period (SLF), to invert the clock (SCKI), or to tri-state the clock (SCKT). Note that slfs is a don't care bit if efs is set.

The ssiord register controls the output bit rate (fclkout) of the serial bit stream. fclkout can be set equal to the modulator clock frequency (fclk) or its integer part. Equals fclk divided by the contents of the ssiord register. Note that fclkout must be chosen such that it does not introduce unwanted spurs within the passband of the signal of interest. The user must verify that the output bit rate is sufficient to accommodate the bits per frame required by the chosen word length and decimation factor. Idle (high) bits are used to fill each frame.

Figure 33 illustrates the output timing of an SSI port with multiple SSI control register settings for 16-bit I/Q data, and Figure 34 shows the associated timing parameters. Note that the same timing relationship holds for 24-bit i/q data, but the i and q word lengths are now 24 bits. In the default mode of operation, data is shifted on the rising edge of clkout after a pulse equal to the clock period is output from the frame sync (fs) pin. As mentioned above, the output data consists of 16-bit or 24-bit i samples, 16-bit or 24-bit q samples, and two optional bytes containing agc and status information. Switching characteristics of the digital output signal through the drive strength (ds) field of ssicrb. This feature can be used to limit switching transients and noise at the digital output that may eventually couple back into the analog signal path, potentially degrading the AD9864's sensitivity performance. Figures 35 and 36 show how nf varies with ssi settings at an IF frequency of 109.65mhz. The following two situations can be observed from these figures:

1. At higher signal bandwidth settings, nf becomes more sensitive to ssi output drive strength levels.

2. NF depends on the number of bits in the ssi frame, as the number of bits increases, these bits become more sensitive to the ssi output driver strength level. So choose the lowest ssi drive strength setting that still meets ssi timing requirements.

Sync with syncb

Many applications require the ability to synchronize one or more AD9864 devices to precisely align the output data with an external asynchronous signal. For example, receiver applications that employ diversity often need to synchronize the digital outputs of multiple ad9864 devices. Satellite communications applications using the tdma approach may require synchronization between payload bursts to compensate for reference frequency drift and Doppler effects. syncb can be used for this purpose. It is an active low signal that clears the decimation filter and the clock counter in the ssi port. The counters in the clock synthesizer are not reset because it is assumed that the clk signals of multiple chips will be connected. syncb also resets the modulator, resulting in massive pulses that must propagate through the AD9864's digital filter and ssi data formatting circuitry before valid output data can be recovered. As a result, when the syncb value is raised (independent of the decimation factor), the data samples unaffected by the sync pulse can be recovered to 12 output data samples. Because syncb also resets the modulator, syncb is only applied after the initialization phase has completed tuning of the bandpass sigma-delta adc. For applications that may perform periodic syncb signaling in synchronization with fs, it is recommended to apply the syncb assertion after the rising edge of fs and three clkout cycles before the arrival of the next fs pulse to avoid runt fs pulses that may interrupt the host dsp/fpga. Lastly, if syncb is not used, it must be tied high since it does not include an internal pull-up resistor.

Figure 37 shows the timing relationship between the clkout and fs signals of the syncb and ssi ports. When the clock synthesizer is enabled to generate the input ADC clock, syncb is considered an asynchronous active low signal and must be held low for at least half of the input clock cycle, i.e. 1/(2 × f). When syncb goes low, clkout stays high and fs stays low. When syncb returns high, clkout becomes active for one to two output clock cycles. If the external ADC clock input is supplied with the Sync Sync B signal, it is recommended that Sync B goes low and returns high on the falling edge of the CLKIN signal to ensure consistent CLKOUT delay relative to the rising edge of Sync B. Depending on the decimation factor of the digital filter and the ssiord setting, fs will then reappear for a few output cycles. Note that this delay is fixed and repeatable for any decimation factor and ssiord setting. To verify proper synchronization, monitor the fs signals of multiple AD9864 devices.

Interface with DSP

The AD9864 interfaces directly to an analog device programmable digital signal processor (DSP). Figure 38 shows an example of a BlackFin® family of processors such as the ADSP-BF609. The Blackfin DSP family of 16-bit products are optimized for low-power telecom applications with their dynamic power management capabilities, making them ideal for portable radio products. Code-compatible family members share essential core attributes of the microcontroller instruction set such as high performance, low power consumption, and ease of use. As shown in Figure 38, the AD9864's Synchronous Serial Interface (SSI) links the receive data stream to the DSP's serial port (SPORT). For AD9864 setup and register programming, the device is connected directly to the SPI port of the DSP. A dedicated select line (SEL) allows the DSP to use one SPI port to program and read the registers of multiple devices. The DSP driver code associated with this interface is available on the AD9864 product page.

Power Control

To minimize power consumption, the AD9864 has a number of SPI programmable power-down and bias control bits. When the AD9864 is powered on, all its functional blocks are in a standby state, that is, the stby register defaults to 0xFF. Each main block can then be started by writing 0 to the appropriate bits of the stby register. This scheme provides maximum flexibility to configure the IC to a specific application, as well as to customize the power-down and wake-up characteristics of the IC. Table 16 summarizes the function of each stby bit. Note that when all modules are in standby, the main reference circuit is also in standby, so the current is further reduced by 0.4 mA.

lo synth

The LO synthesizer shown in Figure 39 is a fully programmable phase-locked loop (PLL) capable of 6.25kHz resolution at input frequencies up to 300MHz and reference clocks up to 26MHz. It consists of a low noise, digital, phase frequency detector (pfd), variable output current charge pump (cp), 14-bit reference divider, programmable a and b counters, and a dual modulo 8/9 prescaler.

The A (3-bit) and B (13-bit) counters together with the dual 8/9 modulo prescalers realize an N divider of N=8×B+A. Additionally, a 14-bit reference counter (R counter) allows selection of input reference frequencies, including the PFD input. If the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO), a complete phase locked loop can be implemented. The A, B, and R counters are programmable through the following registers: LOA, LOB, and LOR. The charge pump output current can be programmed through the LOI register from 0.625mA to 5.0mA: ipump=(loi+1)×0.625mA

An on-chip fast-acquisition feature (enabled by the lof bit) automatically increases the output current for faster resolution during channel changes. The synthesizer can also be disabled using the lo spare bit in the stby register.

The lo (and clk) synths work as follows. The externally supplied reference frequency fref is buffered and divided by the value in the r counter. The internal fref is then compared to the split version of the vco frequency flo. The phase/frequency detector provides up and down pulses whose width varies according to the difference in phase and frequency of the detector input signal. The up/down pulses control the charge pump, making current available to charge the external low pass loop filter when there is a difference between the inputs of the pfd. The output of the low pass filter feeds an external vco whose output frequency f is driven such that its split version flo matches that of fref, closing the feedback loop. The Lo synthesis frequency is related to the reference frequency and the contents of the lo register, as follows: flo=(8×lob+loa)/lor×fref(3)

Note that the minimum value allowed in the lob register is 3, and its value must always be greater than the value loaded into loa.

An example helps to illustrate how to choose the values for loa, lob and lor. Consider an application using a 13mhz crystal oscillator (fref=13mhz) requiring fref=100khz and flo=143mhz, i.e. high side injection of fif=140.75mhz and fclk=18msps. Choose Lor to be 130 and make Fref=100 kHz. The n divider factor is 1430, which can be achieved by choosing lob=178 and loa=6.

The stability, phase noise, spurious performance, and transient response of the AD9864 lo (and clk) synthesizer are determined by the external loop filter, vco, divide-by-n factor, and reference frequency fref. A good overview of the theoretical and practical implementation of the pll synthesizer (featuring a 3-part series on Analog Dialogue) can be found on the Analog Devices website. A free software copy of Analog Devices, ADISimpl, a PLL synthesizer simulation tool, is also available on . Note that the ADF4112 can be used as an approximation to the AD9864's lo synthesizer when using this software tool.

Figure 40. Equivalent input to lo and ref buffers Figure 40 shows the equivalent input structure of the synthesizer lo and ref buffers (excluding the esd structure). The lo input is fed to the buffer of the lo synthesizer and to the lo port of the ad9864 mixer. Both inputs are self-biased, so ac-coupled inputs are tolerated. The lo input can be driven with single-ended or differential signals. The single-ended DC-coupled input ensures sufficient signal swing above and below the common-mode bias of the lo and ref buffers (ie, 1.75v and vddl/2). Note that the f input is slew rate dependent and must be driven with an input signal greater than 7.5v/µs to ensure proper synthesizer operation. If this condition cannot be met, an external logic gate can be inserted before the fref input to square the signal, allowing the fref input frequency to approach dc.

Quick access mode

When the phase difference between the divided lower limit lo (ie flo) and the divided lower limit reference frequency (ie fref) exceeds the threshold determined by the lofa register, the fast acquisition circuit attempts to increase the output current. The lofa register specifies a divisor for the fref signal that determines the period (t) of the clock for this dividend. This period defines the time interval used in the fast acquisition algorithm to control the charge pump current.

Assume the nominal charge pump current is at the lowest setting (loi=0), and denote this minimum current by i. When the output pulse from the phase comparator exceeds t, the output current of the next pulse is 2i. When the pulse is greater than 2t, the output current of the next pulse is 3i 0, and so on, up to 8 times the minimum output current. UT current. If the nominal charge pump current is greater than the minimum value (loi > 0), the above rule applies only if it results in a transient charge pump current increase. If the charge pump current is set to its lowest value (loi=0) and the fast acquisition circuit is enabled, the instantaneous charge pump current will never fall below 2 when the pulse width is less than t. Therefore, when fast acquisition is enabled, the charge pump current is given by:

IPUMP-FA= I × [1 = Max(1, LOI, Pulse Width/T)] . lofa's suggestion is set to lor/16. Choosing a larger value of lofa increases t, so for a given phase difference between the lo input and the fref input, the instantaneous charge pump current is less than the available current for the lofa value lor/16. Similarly, the smaller the lofa value, the smaller the t value, and the larger the current with the same phase difference. In other words, smaller lofa values allow the synth to respond faster to frequency jumps than larger lofa values. Take care to choose a large enough value for lofa (a value greater than 4 is recommended) to prevent the loop from oscillating back and forth in response to frequency jumps.

clock synthesizer

The clock synthesizer is a fully programmable integer-n phase-locked loop capable of supporting input clock and reference frequencies up to 26MHz. It is similar to the lo synth described in Figure 39 with the following exceptions:

(1), 8/9 prescaler and counter are not included.

(2) It includes a negative resistance core that acts as a VCO when used with an external LC box and a varactor diode.

The 14-bit reference counter and the 13-bit N divider counter are programmable through the CKR and CKN registers. The relationship between the clock frequency f and the reference frequency is as follows: fclk=(ckn/ckr×fref)

The charge pump current is programmable through the CKI register from 0.625mA to 5.0mA: ipump=(cki+1)×0.625mA.

The fast acquisition subcircuit of the charge pump is controlled by the ckfa register in the same way that the lo synthesizer is controlled by the lofa register. An on-chip lock detection feature (enabled by the CKF bit) automatically increases the output current for faster problem resolution during channel changes. The synthesizer can also be disabled using the ck spare bit in the stby register.

The AD9864 clock synthesizer circuit includes a negative resistance core, so only an external LC tank circuit with a varactor is required to implement a voltage controlled clock oscillator (VCO). Figure 41 shows the external components required to complete the clock synthesizer and the equivalent input circuit for the CLK input. The resonant frequency of the VCO is approximately determined by the series equivalent capacitance of L and C and C. Therefore, L, C, and C must be chosen to provide sufficient tuning range to ensure proper start-up oscillation and locking of the clock synthesizer. The C and L values must have a ±5% tolerance while L has a Q>20 at the desired clock frequency. oscillator oscillator var oscillator oscillator var oscillator oscillator oscillator

The bias voltage i of the negative resistance core has four programmable settings. LC tank circuits with low equivalent q may require higher negative resistance core bias settings to ensure proper oscillation. Choose R so that the common-mode voltage at CLKP and CLKN is approximately 1.6 V. The synthesizer can be disabled via the CK standby bit to allow the user to use external synthesizers and/or VCOs in place of those on the IC. Note that if an external CLK source or VCO is used, the clock oscillator must be disabled via the CKO standby bit. The phase noise performance of a biased clock synthesizer depends on several factors, including the clk oscillator i setting, the charge pump setting, the loop filter component values, and the internal f setting. Figure 42 and Figure 43 show how the measured phase noise (relative to external f) caused by the clock synthesizer varies with the i setting and charge pump setting for a -31dbm ifin signal at 73.35MHz and an external lo signal at 71.1MHz. Figure 42 shows that the best phase noise is achieved at the highest i(cko) setting, while Figure 43 shows that a higher charge pump value provides the best performance for a given loop filter configuration. The AD9864 clock synthesizer and oscillator were set up to provide a frequency of 18 MHz from an external frequency of 16.8 MHz. The following external component values were chosen for the synthesizer: r=390Ω, r=2 kΩ, Bias Ref Clock Bias Bias Clock Ref fD, C=0.68µF, C=0.1µF, C=91 pF, L=1.2 μH, C=Toshiba 1SV228 varactor.

If the low noise amplifier/mixer

The AD9864 consists of a single-ended LNA and a Gilbert-type active mixer, as shown in Figure 44, with the required external components. The LNA uses negative shunt feedback to set its input impedance at the IFIN pin, making it dependent on the input frequency. It can be modeled as about 370Ω 1.4 pf (±20%) below 100 MHz. Figure 45 and Figure 46 show the equivalent input impedance versus frequency characteristics of the AD9864. The increase in shunt resistance with frequency can be attributed to the decrease in bandwidth and hence the amount of negative feedback of the lna. Note that the signal input to the ifin must be AC coupled through a 10nf capacitor because the lna input is self biased.

The differential lo port of the mixer is driven by the lo buffer stage shown in Figure 44, which can be single-ended or differentially driven. Since it is self-biased, the lo signal level can be AC coupled, ranging from 0.3v pp to 1.0vp-p with negligible impact on performance. The open collector outputs of the mixers MXOP and MXON drive an external resonator consisting of a differential LC network tuned to the intermediate frequency of the bandpass Σ-∏ ADC, ie, FIF2_ADC=fclk/8. The two inductors provide a DC bias path for the mixer core through a 50Ω series resistor, which is used to suppress the common-mode response. The output of the mixer must be AC coupled to the inputs of the bandpass Σ-∏ adc, if2p, and if2n through two 100 pf capacitors to ensure proper tuning of the lc center frequency.

The external differential lc resonator constitutes the resonant element of the first resonator of the bandpass Σ-∏ modulator and must therefore be tuned to the f/8 center frequency of the modulator. The inductor must be chosen so that its impedance at fclk/8 is about 140, ie l=180/fclk. An accuracy of 20% was considered sufficient. For example, at fclk=18mhz, l=10µh is a good choice. Once the inductor is selected, the required slot capacitance can be used to calculate the clock using the following relationship: fclk/8=1/[2×π×(2l×c)].

For example, at fclk=18mhz and l=10µh, a capacitance of 250pf is required. However, to accommodate the ±10% inductance tolerance, the tank capacitance must be adjustable from 227 pF to 278 pF. Choosing an external capacitor of 180 pf ensures that even with a 10% tolerance and stray capacitance up to 30 pf, the total capacitance is less than the minimum required for the tank. Additional capacitance is provided by the AD9864 on-chip programmable capacitor array. Since the programming range of the capacitor array is at least 160 pf, the AD9864 has enough range to compensate for the tolerances of low-cost external components. Note that if f is increased by a factor of 1.44mhz to 26mhz so that fclk/8 becomes 3.25mhz, then reducing l and c by about the same factor (l = 6.9µh, c = 120pf) satisfies the previously stated requirements.

A 16 dB step attenuator is also included in the LNA/mixer circuit to prevent large signals (ie, >-18 dBm) from overdriving the sigma-delta modulator. In this case, the sigma-delta modulator becomes unstable, severely reducing the sensitivity of the receiver. The 16db step attenuator can be invoked by setting the attenuator bit (register 0x03, bit 7) to reduce the mixer gain by 16db. A 16db step attenuator can be used for potential targets or applications where the blocking signal may exceed the if input clip point. Although lna is driven to compress, if it is fm, the desired signal can still be recovered. Enables the gain compression feature of the 16db attenuator's lna and mixer.

Bandpass ∑-∏ ADC

The ADC of the AD9864 is shown in Figure 47. The ADC contains a sixth-order, multi-bit bandpass sigma-delta modulator that achieves very high instantaneous dynamic range in a narrow frequency band. The loop filter of the bandpass sigma-delta modulator consists of two continuous-time resonators and one discrete-time resonator, with each resonator stage contributing a pair of complex poles. The first resonator is an external LC tank, while the second is an on-chip active RC filter. The output of the lc resonator is AC coupled to the second resonator input through a 100 pf capacitor. The center frequency of these two continuous time resonators must be tuned to f/8 for the ADC to work properly. The center frequency of the discrete-time resonator automatically adjusts with f, so no tuning is required.

Figure 48 shows the measured power spectral density at the output of a non-CIMATED bandpass sigma-delta modulator. Note that once the lc and rc resonators of the sigma-delta modulator are successfully tuned, a wide dynamic range is achieved at the center frequency f/8. Out-of-band noise is removed by a decimation filter after the quadrature mixer.

The signal transfer function of the AD9864 has inherent antialiasing filtering due to the continuous time portion of the loop filter in the bandpass sigma-delta modulator. Figure 49 illustrates this behavior by plotting the nominal signal transfer function of the ADC for frequencies up to 2f. The notches that naturally occur at all frequencies aliased with the f/8 passband are clearly visible. Even at the widest bandwidth setting, the notch is deep enough to provide greater than 80dB of alias protection. Therefore, the wideband IF filtering requirements prior to AD9864 are primarily determined by the mixer's image band, which is shifted from the desired IF input frequency by f/4 (ie, 2 × f/8), not the one associated with the ADC any aliasing.

Figure 50 shows the nominal signal transfer function amplitude at frequencies around the fclk/8 passband. The width of the passband determines the attenuation of the transfer function, but even at the lowest oversampling rate (48) where the passband edge lies at ±fclk/192 (±0.005fclk), the gain change is less than 0.5dB. The amount of attenuation provided by the signal transfer function around fclk/8 should also be considered when determining the narrowband IF filtering requirements prior to the AD9864.

Figure 50. The magnitude of the ADC's signal transfer function around fclk/8 To achieve the full dynamic range of the ADC, the two continuous-time resonators of the sigma-∏ modulator must be tuned at system startup. To facilitate tuning of the LC tank, the capacitor array is internally connected to the mxop and mxon pins. The capacitance of this array is programmable from 0 pF to 200 pF ±20%, and can be programmed automatically or manually through the SPI port. The capacitors of the active rc resonators are also programmable. Note that since the tuning code is stored in the SPI register, the AD9864 can enter and exit standby mode without retuning.

When tuning the LC tank, the sample clock frequency must be stable and the lna/mixer, lo synth and ADC must all be in standby. Since the presence of large lo and if signals (>-40 dBm) at the input of the AD9864 can damage the calibration, these signals must be minimized or disabled during calibration. If the tune LC bit in Register 0x1C is set, a tune is triggered when the ADC comes out of standby. This bit is cleared when the tuning operation is complete (less than 6 ms). The tuning code can be read from the 3-bit capl1 (0x1d) and 6-bit capl0 (0x1e) registers. In a similar fashion, tuning of the rc resonator is activated if the tuning rc bit of register 0x1c is set when the ADC comes out of standby. This bit is cleared when tuning is complete. The tuning code can be read from the capr (0x1f) register. Setting the tune_lc and tune_rc bits will continuously tune the lc resonator and the active rc resonator. During the tuning process, the ADC does not work and the SSI port has neither data nor clock.

The following mechanism prevents the adjustment process from ending (i.e. Register 0x1C is not cleared):

(1) The CLK signal does not exist, or is not properly scaled/biased to the CLKP (and/or CLKN) pins, so the internal clock receiver cannot square the input clock signal. To determine if the CLK input signal is being received correctly, a clock signal is present at CLKOUT when the ADC is not in standby mode (Register 0x00) and the CLKOUT buffer is not tri-stated (Register 0x18).

(2) The LC resonator cannot resonate during the tuning operation. Check that the LC slot is using the correct value and that it is connected to the MXOP/MXON pins. Also check if a 100 pf capacitor is connected between the MXOP (MXON) and IF2P (IF2N) pins.

(3), Sycnb pin is low.

(4) The capacitance value (between MXOP/MXON and IF2P/IF2N pins) is greater than 100 pF.

The recommended sequence of SPI commands for tuning the ADC, Table 21 lists all the SPI registers associated with the bandpass Σ-∏ ADC. Note that the proposed sequence includes additional steps to enhance robustness. These steps are additional measures to prevent the backend ADC from generating an internally unstable signal that locks the state machine, thereby preventing the resonator from tuning. It also allowed five attempts to calibrate the resonator. As a further safeguard, the user can save the settings for Register 0x1d, Register 0x1e, and Register 0x1f determined during factory testing and reload these settings after five attempts. Note that this adjustment issue is extremely rare in devices shipped to date, and very low (<0.1%) in any suspect devices.

When the AD9864 is tuned, the noise figure reduction due only to the temperature drift of the lc and rc resonators is minimal. Since the temperature drift of rc resonators is practically negligible compared to lc resonators, the temperature drift characteristics of the external l and c components tend to dominate. Figure 51 shows the reduction in noise figure as the product of the LC values is allowed to vary from -12.5% to +12.5%. Note that the noise figure remains relatively constant within ±3.5% (±35000 ppm), which indicates that most applications do not require readjustment over the operating temperature range.

The decimation filter shown in Figure 52 consists of an fclk/8 complex mixer and three linear-phase fir filters in cascade: dec1, dec2, and dec3. Use a fourth-order comb filter, reducing 1 sample by a factor of 12. dec2 also uses a fourth-order comb filter, but its decimation factor is set by the m field of register 0x07. dec3 is a five-by-five fir filter or a four-by-four fir filter, depending on the value of the k bits in register 0x07. Therefore, the composite decimation factor can be set to 60×m or 48×m for k equal to 0 or 1, respectively.

The output data rate (f) is equal to the modulator clock frequency (fclk) divided by the decimation factor of the digital filter. Due to the transition region associated with the frequency response of the decimation filter, the decimation factor must be chosen such that fout is equal to or greater than twice the signal bandwidth, ensuring low amplitude ripple in the passband prior to demodulation and providing further The ability to apply specific digital filtering.

Figure 53 shows the response of the decimation filter with a decimation factor of 900 (k=0, m=14) and a sampling clock frequency of 18MHz. In this example, the output data rate (f) is 20 ksps and the available complex signal bandwidth is 10 khz, centered at dc. As shown, the first and second false frequency bands (occurring at even integer multiples of fout/2) have minimal attenuation but provide at least 88 db of attenuation. Note that signals with frequency offsets around odd integer multiples of fout/2 (i.e., 10 kHz, 30 kHz, and 50 kHz) fall back into the transition band of the digital filter. The response of a decimation filter with an output factor of 48 and a sampling clock frequency of 26 MHz.

Alias attenuation is at least 94db and occurs at frequencies at the edge of the fourth alias band. The difference between the alias attenuation characteristics of Figures 53 and 54 is due to the fact that the third decimation stage of Figure 53 has a decimation factor of 5, while the factor of Figure 54 is 4.

Variable Gain Amplifier Operation

automatic gain control

The AD9864 contains a variable gain amplifier (VGA) and a digital VGA (DVGA), as well as all the necessary signal estimation and control circuitry required to implement automatic gain control (AGC), as shown in Figure 59. The agc control circuit is highly programmable, allowing the user to optimize the agc response as well as the dynamic range of the AD9864 for a given application. The vga is programmable within 12db and is achieved within the adc by adjusting its full-scale reference level. Increasing the full scale of the ADC is equivalent to weakening the signal. By scaling the output of the decimation filter in the dvga, an additional 12db of digital gain range can be obtained. Note that the supply current (0.67mA) for VDDI and VDDF increases slightly as the VGA decays from 0dB to 12dB. The purpose of the VGA is to extend the usable dynamic range of the AD9864 by allowing the ADC to digitize the desired signal over a wide range of input power, as well as to recover low-level signals in the presence of large unfiltered interferers without saturating the ADC or clipping. In narrowband applications requiring 16-bit i and q data formats, dvga is most useful in extending dynamic range. In these applications, quantization noise due to internal truncation to 16-bit and external 16-bit fixed-point postprocessing can reduce the effective noise figure of the AD9864 by 1dB or more.

Enable dvga by writing 1 to the agcv field. VGA (and DVGA) can operate in user-controlled variable gain mode or automatic gain control (AGC) mode. It is worth noting that since the gain of the vga varies in the range of 12db, it has negligible phase error to the desired signal. This is because the bandwidth of the vga is much larger than the downconverted desired signal (centered at f/8) and remains relatively independent of the gain setting. As a result, the phase error of the phase modulated signal is minimal when the AGC changes the VGA gain while tracking the interferer or desired signal under fading conditions. Note that the envelope of the signal is still affected by the AGC setting.

Variable Gain Control

Variable gain control is enabled by setting the AGCR field of Register 0x06 to 0. In this mode, the gain of the vga (and dvga) can be adjusted by writing to the 16-bit agcg register. The maximum update rate of the agcg register through the spi port is fclk/240. The msb of this register is the bit that enables 16 db attenuation in the mixer. This feature allows the AD9864 to handle large-level signals beyond the VGA range (ie, greater than -18 dBm at the LNA input) to prevent the ADC from overloading. The lower 15 bits specify the attenuation of the remainder of the signal path. If DVGA is enabled, the attenuation range is -12dB to +12dB, because DVGA provides 12dB of digital gain. In this case, all 15 bits are valid. However, with the dvga disabled, the attenuation range extends from 0db to 12db, and only the lower 14 bits are useful. Figure 60 shows the relationship between the amount of attenuation and the AGC register setting for both cases.

Referring to Figure 59, the gain of the vga is set by an 8-bit control dac that provides a control signal to the vga appearing at the gain control pin (gcp). For applications implementing automatic gain control, the output resistance of the DAC can be reduced by a factor of 9 to reduce the attack time of the AGC response, resulting in faster signal acquisition. An external capacitor cdac from gcp to analog ground needs to smooth its output every time the dac is updated, and filter out broadband noise. Note that the cdac combined with the dac's programmable output resistance sets the -3db bandwidth and time constant associated with this rc network.

As discussed in the AGC section, a linear estimation of the received signal strength is performed at the output of the first decimation stage (dec1) and at the output of the dvga (if enabled). This data is available as a 6-bit rssi field within the ssi frame, 60 corresponds to the full-scale signal for a given AGC attenuation setting. The rssi field is updated at f/60 and can be used in conjunction with the 8-bit attenuation field (or agcg attenuation setting) to determine absolute signal strength. Note that the rssi data must be post-filtered to remove the AC ripple component that depends on the frequency offset relative to the if frequency.

The accuracy of the average rssi reading (relative to the if input power) depends on the frequency offset of the input signal relative to the if frequency, since both the response of the dec1 filter and the signal transfer function of the adc attenuate the mixer centered at f/8 down-converted signal level. As a result, the estimated signal strengths of input signals that fall around if are accurately reported, while those at higher and higher frequency offsets cause larger measurement errors. Figure 61 shows the normalized error of rssi readings as a function of IF frequency offset. Note that the significance of this error becomes apparent when determining the maximum input glitch (or blocking) level with the AGC enabled.

Automatic Gain Control (AGC)

The gain of the vga (and dvga) is automatically adjusted when the agc is enabled through the agcr field of register 0x06. In this mode, the gain of the vga is continuously updated at fclk/60 in an attempt to ensure that the maximum analog signal level going into the adc does not exceed the adc clip level and that the rms output level of the adc is equal to the programmable reference level. With the dvga enabled, the agc control loop also attempts to minimize the effect of 16-bit truncation noise before the ssi output by continuously adjusting the dvga's gain to ensure maximum digital gain is obtained without exceeding a programmable reference level.

This programmable level can be set 3db, 6db, 9db, 12db and 15db below the ADC saturation (clip) level by writing a value from 1 to 5 into the 3-bit AGCR field. Note that the ADC clip level is defined as 2dB below its full scale (LNA input is -18dBm with matched input and maximum attenuation). If AGCR is 0, automatic gain control is disabled. Since clipping of the ADC input degrades SNR performance, the reference level must also take into account the peak toms characteristics of the target (or interfering) signal.

Referring again to Figure 59, most AGC loops operate in the discrete time domain. The sampling rate of the loop is f/60; therefore, the registers associated with the AGC algorithm will be updated at that rate. When properly configured, the number of overloads and ADC resets and the AGC value (8 msb) within the final i/q update rate of the AD9864 can be read from the SSI data.

The agc performs digital signal estimation at the output of the first decimation stage (dec1) and at the output of the dvga after the last decimation stage (dec3). The rms power of the i and q signals is estimated by the equation: Xest[n] = Abs(I[n] + Abs(Q[n]) .

Signal estimation after the first decimation stage allows the AGC to handle out-of-band interferers and in-band signals that could overload the ADC. Signal estimation after dvga allows AGC to minimize the effects of 16-bit truncation noise.

When the estimated signal level falls within the range of the AGC, the AGC loop adjusts the vga (or dvga) attenuation settings so that the estimated signal level is equal to the programmed level specified in the AGC field. When properly configured, absolute signal strength can be determined from the contents of the attn and rssi fields available in the ssi data frame. Within this AGC tracking range,

The 6-bit value in the rssi field remains the same, while the 8-bit attn field changes depending on the vga/dvga setting. Note that the attn value is based on the 8 msb contained in the agcg field of Register 0x03 and Register 0x04.

Next, the agc control algorithm and user-adjustable parameters are introduced. First, consider the case where the in-band target signal is greater than all out-of-band interferers and the dvga is disabled. With the dvga disabled, a control loop based only on the target signal power measured post-dec1 is used to control the vga gain and track the target signal to the programmed reference level. If the signal is too large, the attenuation will increase with a proportionality constant determined by the AGCA settings. Larger agca values result in larger gain changes, which quickly track changes in signal strength. If the target signal is too small relative to the reference level, the attenuation is reduced; however, the proportionality constant is now determined by the agca and agcd settings. The agcd value is effectively subtracted from the agca, so a larger agcd results in a smaller gain change, which slows down tracking of fading signals.

The 4-bit code in the agca field sets the raw bandwidth of the agc loop. When agca=0, the minimum agc loop bandwidth is 50hz, assuming f=18mhz. Each additional agca increases the loop bandwidth by a factor of √2, so the maximum bandwidth is 9khz. The general expression for the attack bandwidth is the clock: BWA= 50 × (fCLK/18 MHz) × 2(AGCA/2)Hz .

Assuming that the loop dynamics are essentially those of a unipolar system, the corresponding attack time is: tATTACK= 2.2/(100 × π × 2(AGCA/2)) = 35/BWA.

The 4-bit code in the agcd field sets the ratio of attack time to decay time in the amplitude estimation circuit. When AGCD is zero, the ratio is 1. Incremental AGCD multiplies the decay time constant by 21/2, allowing a 180:1 range of decay time relative to attack time. Decay time can be from: tDECAY= tATTACK × 2(AGCD/2).

Figure 62 shows the AGC response to 30 Hz pulsed IF bursts at different AGC A and AgCD settings. The 3-bit value in the agco field determines the amount of attenuation added in response to a reset event in the ADC. Each increment in the AGCO is twice the weighting factor. At the highest AGCO setting, the attenuation changed from 0 to 12 dB in about 10 microseconds, while at the lowest setting, the attenuation changed from 0 to 12 dB in about 1.2 milliseconds. In both cases, FCLK = 18 MHz is assumed. Figure 63 shows the AGC attack time response for different AGCO settings.

Finally, the AGCF bits reduce the DAC source resistance by a factor of at least 10, which helps to achieve fast acquisition by reducing the RC time constant formed by the external capacitor connected from the GCP pin to ground (GCN pin). For an overshoot-free step response in the AGC loop, the capacitor connected from the GCP pin to the GCN ground pin is chosen so that the RC time constant is less than a quarter of the original loop.

Specifically: RC < 1/(8πBW) , where: R is the resistance between the GCP pin and ground (72.5 kΩ±30% if AGCF=0; <8 kΩ if AGCF=1). bw is the raw loop bandwidth.

Note that when c is chosen for this upper limit, the loop bandwidth increases by about 30%.

Now consider the situation described earlier, but with dvga enabled to minimize the effects of 16-bit truncation. With dvga enabled, the dvga gain is controlled based on the control loop of the greater of the two estimated signal levels (ie the output of dec1 and dvga). The dvga multiplies the output of the decimation filter by a factor of 1 to 4 (i.e. 0 dB to 12 dB). When the signal is small, the dvga gain is 4, and the 16-bit output is extracted from the 24-bit data produced by the decimation filter by reducing 2 msb and taking the next 16 bits. As the signal gets larger, the dvga gain decreases to the point where the dvga gain is 1 and the 16-bit output data is only 16 msb of the internal 24-bit data. Attenuation is achieved by the conventional method of increasing the full scale of the ADC as the signal becomes larger.

The additional 12dB of gain range provided by the dvga reduces the input reference truncation noise by 12dB and makes the data more tolerant of lsb corruption in the dsp. The price paid for extending the gain range is that the onset of the AGC action is 12dB lower, and if the bandwidth is set too wide, the AGC loop becomes unstable. The latter difficulty is due to the large delay of the decimation filters dec2 and dec3 when the user implements a large decimation factor. So, given the options, using 24-bit data is better than using

DVGA. Figure 64 indicates which AGCA values are reasonable for various decimation factors (DEC FAC). White cells indicate that the (Pump Factor/AGCA) combination worked well; light gray cells indicate increased ringing and AGC settling times; dark gray cells indicate combinations that cause the AGC circuit to be unstable or nearly unstable. Setting agcf=1 improves time-domain behavior at the cost of increased spectral spread.

Finally, consider the case of strong out-of-band interference (i.e., -18 dbm to -32 dbm for the matched IF input) that is larger than the target signal and large enough to be tracked by the control loop based on the output of dec1. The ability of the control loop to track this interferer and set the vga attenuation to prevent clipping of the ADC is limited by the accuracy of the digital signal estimation that occurs at the output of dec1. The accuracy of the digital signal estimation is a function of the frequency offset of the out-of-band interferer relative to the IF frequency, as shown in Figure 61. Interfering sources with higher and higher frequency offsets create larger measurement errors that can cause the control loop to inadvertently reduce the amount of VGA attenuation that can lead to ADC clipping. Figure 65 shows the maximum measured interferer signal level allowed by the AD9864 relative to its maximum target input signal level (0 dBfs = -18 dBm) as a function of normalized IF offset frequency (relative to f). Note that the increase in the allowable interference level over 0.04 × fclk is caused by the inherent signal attenuation provided by the ADC's signal transfer function.

System Noise Figure (NF) and VGA (or AGC) Control

The system noise figure of the AD9864 is a function of ACG attenuation and output signal bandwidth. Figure 66 depicts the nominal system nf as a function of agc attenuation for narrowband (20 kHz) and wideband (150 kHz) modes, fclk = 18 mHz. The figure also shows the snr observed at the output for the -2 dbfs input. The high dynamic range of the AD9864's internal ADC ensures that the system NF increases gradually with increasing AGC attenuation. In the narrowband (bw=20khz) mode, the system noise figure increases by less than 3db in the range of 12db agc, while in the wideband (bw=150khz) mode, the attenuation is about 5db. Therefore, the highest instantaneous dynamic range of the AD9864 occurs with an AGC attenuation of 12dB, because the AD9864 can accommodate an additional 12dB of peak signal level with only a modest increase in the noise floor.

As shown in Figure 66, the AD9864 can achieve a signal-to-noise ratio in excess of 100 dB in narrowband applications. In order to realize the full performance of the ad9864 in this application, it is recommended to use 24 bits to represent the i/q data. If 16-bit data is used, the effective system nf increases due to quantization noise in the truncated 16-bit data.

Figure 67 depicts the nominal system nf of 16-bit output data as a function of agc in both narrowband and wideband modes. In wideband mode, the nf curve is almost unchanged with respect to 24-bit output data, because the output snr before truncation is always smaller than the 96db snr that 16-bit data can support. However, in narrowband mode, the degradation of system nf is more severe when the output SNR approaches or exceeds that supported by 16-bit data. Furthermore, if the signal processing within the dsp adds noise at the level of the lsb, the system noise figure can be reduced even beyond that shown in Figure 67. This can happen, for example, in a fixed 16-bit DSP whose code is not optimized to handle AD9864 16-bit data with minimal quantization effects. To limit the effects of quantization within the AD9864, the 24-bit data is noise-shaped before 16-bit truncation, reducing the in-band quantization noise by 5dB (with 2× oversampling). Therefore, at a bandwidth of 10 kHz, the SNR performance of 98.8 dBfs can still be achieved with 16-bit data.

Application Notes

frequency planning

The LO frequency (and/or the ADC clock frequency) must be carefully chosen to prevent known internally generated spurs from mixing with the desired signal, thereby degrading the SNR performance. The main sources of spurs in the AD9864 are the ADC clock and digital circuits operating at 1/3 of FCLK. So the clock frequency (fclk) is the most important variable in deciding which lo (and therefore if) frequency is feasible.

Due to the large selection of low-cost crystal or SAW filters, many applications have frequency plans that utilize industry standard IF frequencies. If the selected IF frequency and ADC clock frequency cause problematic spurious components, select an alternate ADC clock frequency by slightly modifying the decimation factor and CLK synthesizer settings (if used) so that the output sample rate remains the same. Additionally, applications that require a certain tuning range must consider the location and magnitude of these spurs when determining the tuning range as well as the optimal IF and ADC clock frequency.

Figure 69 plots the measured in-band noise power at f = 18MHz as a function of lo frequency and the output signal bandwidth of 150 kHz in the absence of a signal. Any low frequencies that cause large spurs must be avoided. As shown in the figure, when lo is fclk/8=2.25 mhz, a larger stray harmonic will be generated away from 18 mhz, that is, n fclk ± fclk/8. Also problematic are the lo frequencies, whose odd-order harmonics (i.e. m×flo) are mixed with harmonics from fclk to fclk/8. This spurious mechanism is the result of the mixer being internally driven by the squared form of the lo input consisting of the lo frequency and its odd-order harmonics. These spurious frequencies can be calculated from the following relationship: m × f = (n ± 1/8) × f (12) where: m = 1, 3, 5... n = 1, 2, 3...LOCLK.

The second spurious source is a large piece of digital circuitry clocked at fclk/3. The problematic lo frequency associated with this spurious source is given by: fLO = fCLK/3 + n × fCLK ± fCLK/8(13) where n = 1, 2, 3...

Figure 70 shows that ignoring the lo frequencies for m=1, 3, and 5 given by Equation 12, and the lo frequencies given by Equation 13, can explain most of the spurs. Some of the remaining low-level spurs can be attributed to coupling of the ssi digital outputs. Therefore, the user is also advised to optimize the output bit rate (fclkout via the ssiord register) and digital output driver strength to achieve the lowest spurious and noise figure performance at a specific lo frequency and fclk setting. This is especially true for very narrowband channels where low-level spurs can degrade the sensitivity performance of the AD9864. Although there are many spurs, the sweet spot in the lo frequency is usually wide enough to accommodate the maximum signal bandwidth of the AD9864. As evidence of this characteristic, Figure 68 shows that the in-band noise is fairly constant over the lo frequency range from 70mhz to 71mhz.

spurious response

The spectral purity of the LO (including its phase noise) is an important consideration, as the LO spurs can mix with undesired signals present at the AD9864 IFIN input to produce an in-band response. To demonstrate the low LO spurious levels introduced in the AD9864, Figure 71 plots the demodulated output power as a function of the input IF frequency at 71.1 MHz LO frequency and 18 MHz clock frequency.

The two large −10 dbfs peaks near the center of the plot are the expected responses at f, ±f, where f = f/8, the expected responses at 68.85 MHz and 73.35 MHz. lo produces spurious responses at f±fresult and at ±far offsets of the desired response. Such close-up spurs are not visible on the plot; however, small spurious responses at f±f±f (at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz) are visible at the -90 dBfs level. These data suggest that ad9864 does a good job of maintaining the purity of the LO signal.

Figure 71 can also be used to measure how well the AD9864 suppresses unwanted signals. For example, the half-IF response (at 69.975mhz and 72.225mhz) is about -100dbfs, which gives 90db of selectivity to this spurious response. The maximum spurious response occurs at approximately -70dbfs when the input frequencies are 70.35mhz and 71.85mhz. These spurs are caused by third-order nonlinearities in the signal path (ie, abs[3×f−3×f]=f/8).

application

Example of a superheterodyne receiver

The AD9864 is ideal for analog and/or digital narrowband-to-band radio systems based on superheterodyne receiver architecture. Superheterodyne architectures achieve exceptional dynamic range and selectivity by using two or more downconversion stages to provide amplification of the signal of interest while filtering unwanted signals. The AD9864 greatly simplifies the design of these radio systems by integrating a full mid-band (excluding lo-VCO) while providing I/Q digital outputs (and other system parameters) for demodulation of analog and digital modulated signals. The exceptional dynamic range of the AD9864 generally simplifies IF filtering requirements and eliminates the need for an external AGC.

Figure 73 shows a typical double-conversion superheterodyne receiver using the AD9864. An RF tuner is used to select the signal of interest and downconvert it to the first IF suitable for the AD9864. A preselection filter can limit the rf input to the frequency band of interest before the tuner. The output of the tuner drives an IF filter that provides partial rejection of adjacent channels and interferers that might otherwise limit the receiver's dynamic range. Set the conversion gain of the tuner so that the peak value of the input signal level to the AD9864 is no greater than -18 dBm to prevent clipping. The AD9864 downconverts the first IF signal to a second IF signal that is exactly 1/8 the clock rate of the sigma-delta ADC (f/8) to simplify the digital quadrature demodulation process.

This second IF signal is then digitized by sigma-delta adc, demodulated into quadrature i and q components, filtered through matched decimation filters, and reformatted for a synchronous serial interface to the DSP. In this example, both the lo and clk synthesizers of the AD9864 are enabled, requiring some additional passive components (loop filter and clk oscillator for the synth) and VCO for the lo synthesizer. Note that not all required decoupling capacitors are shown.

The selection of the first IF frequency is usually based on the availability of low-cost standard crystal or SAW filters and system frequency planning considerations. In general, crystal filters are usually used for narrowband radios with channel bandwidths less than 50khz and ifs less than 120mhz, while saw filters are more suitable for narrowband radios with ifs greater than 70mhz and channel bandwidths greater than 50khz. The final stopband rejection required by the if filter depends on how much rejection is required at the AD9864 image band due to downconversion to the second if. This image band is offset from the first IF by twice the frequency of the second IF (±f/4, depending on high-side or low-side injection).

The selectivity and bandwidth of the IF filter depends on the amplitude and frequency offset of adjacent channel blockers that can drive the input of the AD9864 too quickly or generate in-band intermodulation products. Further suppression is performed in the AD9864 through its inherent bandpass response and digital decimation filter. Note that some applications require additional application-specific filtering to be performed in the DSP after the AD9864 to remove adjacent channels and/or implement a matched filter for optimal signal detection.

The output data rate f of the AD9864 is chosen to be at least twice the bandwidth or symbol rate of the desired signal to ensure that the decimation filter provides a flat passband response and allows for post-processing by the DSP. After f is determined, the decimation factor of the digital filter must be set such that the input clock rate f falls within the AD9864's rated operating range of 13MHz to 26MHz and the significant spurious products associated with fclk do not fall within the desired passband , resulting in a decrease in sensitivity performance. If spurious components are found to limit sensitivity performance, the decimation factor can often be modified slightly to find the spurious free passband. Given the choice, it is usually preferable to choose a higher fclk, since the filtering requirements of the first if usually depend on the transition region (±fclk/4) between the if frequency and the image frequency band. Finally, the output SSI clock rate, fclkout, and digital driver strength must be set to the lowest possible settings to minimize the potentially harmful effects of digitally induced noise while maintaining a reliable data link to the DSP. Note that the ssicra, ssicrb, and ssiord registers (0x18, 0x19, and 0x1a) provide a lot of flexibility in the optimization of the ssi interface.

Synchronization of Multiple AD9864 Devices

Some applications, such as receiver diversity and beam steering, may require two or more AD9864 devices to operate in parallel while maintaining synchronization. Figure 73 shows an example of how to cascade multiple AD9864 devices, with one device acting as the master and the other as the slave. In this example, all devices have the same SPI register configuration because they share the same SPI interface with the DSP. Since the state of each internal counter of the AD9864 device is unknown at initialization, the device needs to be synchronized via a syncb pulse (see Figure 37) to synchronize its digital filters and ensure precise time alignment of the data stream.

Although all devices' synthesizers are enabled, the slave's lo and clk signals come from the master's synthesizer and are referenced to an external crystal oscillator. All necessary external components (loop filter, varactor, LC and VCO) are included to ensure proper closed loop operation of the main synth. Note that the FREF input of the slave device must be grounded.

Note that although the VCO output of the LO synthesizer is coupled to the LO input of the slave, if the AD9864's Clk oscillator is enabled, all Clk inputs of the device must be DC coupled. This is because the CLK oscillator in each device requires DC current. Essentially, these negative impedance cores operate in parallel, increasing the effective q-value of the LC resonant circuit. r must be sized such that the sum of the oscillator's DC bias currents maintains a common-mode voltage of about 1.6v.

Split receive architecture

For those applications where instantaneous dynamic range requirements exceed the capabilities of a single AD9864 device, the split-path rx architecture may be attractive. To meet these higher dynamic range requirements, two AD9864 devices can be operated in parallel, with their respective clip points offset by a fixed amount. Adding a fixed amount of attenuation in front of the AD9864 and/or programming the attenuation settings of its internal vga can adjust the clip point of the input reference. To save energy and simplify hardware, the lo and clk circuits of the device can also be shared. Connect the sync pins of both devices and pulse this line low to sync both devices.

Figure 75 shows an example of how this concept might be used in a GSM base station. The signal chain consists of a highly linear RF front-end and IF stage and two AD9864 devices operating in parallel. The RF front end includes a duplexer and preselector filters to pass the GSM RF band of interest. A high-performance LNA separates the duplexer from the preselection filter while providing sufficient gain to minimize system nf. The rf mixer is used to downconvert the entire gsm band to a suitable if where most of the channel selectivity is achieved. The 170.6 MHz IF was chosen to avoid any self-inductive spurs from the AD9864. The IF stage consists of two saw filters isolated by a 15db gain stage.

The cascaded SAW filter response must provide sufficient choke rejection for the receiver to meet the sensitivity requirements under worst-case choke conditions. Composite responses with 27db, 60db and 100db rejection at frequency offsets of ±0.8mhz, ±1.6mhz and ±6.5mhz respectively provide sufficient blocker rejection to ensure that the ad9864 with the lower clip point is not blocked by any Overdrive. This configuration achieves the best receiver sensitivity under all blocking conditions.

The output of the last saw filter drives two AD9864 devices through a direct signal path and an attenuated signal path. The direct path corresponds to the ad9864 with the lowest clip point and provides the highest receiver sensitivity with a system noise figure of 4.7db. The device's VGA is set to maximum attenuation, so its clip point is about -17 dBm. Since the conversion gain from the antenna to the AD9864 is 19db, the digital output of this path is usually chosen unless the power of the target signal at the antenna exceeds -36dbm. The attenuation path corresponds to the ad9864 with the highest input reference clip point, and the digital output point for that path is set to 7dbm by inserting a 30db fader and setting the ad9864's vga to the middle of the 12db range. This setting results in a ±6db adjustment of the clip point, allowing the clip point difference to be calibrated to exactly 24db, so that a simple 5-bit shift will compensate for the gain difference. The attenuation path can handle signal levels up to -12dB at the antenna before overdriving it. Since the SAW filter provides sufficient blocking rejection, digital data from this path only needs to be selected if the signal of interest exceeds -36 dBm. Although the sensitivity of the attenuation path receiver is 20dB lower than that of the direct path, the strong target signal guarantees a sufficiently high carrier-to-noise ratio.

Since gsm is based on a tdma scheme, digital data (or path) selection can be done on a slot-by-slot basis. The AD9864 is configured to provide serial I and Q data at a frame rate of 541.67 ksps, with additional information including a 2-bit reset field and a 6-bit RSSI field. These two fields contain the information needed to decide whether to use the direct path or the fading path for the current time slot.

Pendant Mixer Mode

The AD9864 can operate in pendant mixer mode by connecting one of lo's self-biased inputs to ground (i.e. GNDI) or a positive supply (VDDI). In this mode, the AD9864 acts as a narrowband, bandpass Σ-∏ ADC as its mixer passes the IFIN signal without any frequency conversion. The ifin signal must be centered around the resonant frequency of Σ-∏adc, fclk/8, and the clock rate, fclk, and decimation factor must be chosen to suit the bandwidth of the desired input signal. Note that the lo synth can be disabled as it is no longer required.

Since the mixer does not have any losses associated with the mixing operation, the conversion gain through the lna and the mixer is higher, resulting in a nominal input clip point of -24dbm. SNR performance depends on the VGA attenuation setting, I/Q data resolution, and output bandwidth, as shown in Figure 76. Applications requiring the highest instantaneous dynamic range must set the VGA to maximum attenuation. Utilizing 24-bit i/q data enables many additional decibels of SNR performance at lower signal bandwidths.