Features: Industry Standard Pins with Enable Input 4.5 to 18V Operating Range 11.4a Peak Notch at VDD=12V 9.7A Sink/7.1A Source, Vout=6V Inverted Configuration (FAN3121) and Non-Inverted Configuration (FAN3122) Internal resistor shuts down driver if no input 23ns/19ns typical rise/fall time under 10nF load 20ns typical propagation delay time Choice of TTL or CMOS input threshold MillerDrive 8482 ; technology available thermally enhanced 3x3mm 8-lead MLP or 8-lead SOIC Package (Pb-Free Finish) Temperature Rating -40°C to +125°C

Application: Synchronous rectification circuit high efficiency mosfet switching switching power supply DC-DC converter motor control

Description: The fan3121 and fan3122 mosfet drivers are designed to drive n-channel enhanced mosfets providing high peak current pulses for low side switching applications. The driver can be used with TTL (FAN312XT) or CMOS (FAN312XC) input thresholds. Internal circuitry provides under-voltage lockout to keep the output low until the power-on voltage is within the operating range. The FAN312X driver contains the architecture of the final output stage of MillerDrive™. This bipolar/mosfet combination provides the current on/off process for the highest peak mosfet Miller plateau stage. The FAN3121 and FAN3122 drivers perform the function on enable pin 3 (en), previously on the industry standard pin. The pin is pulled up to VDD internally for active high logic and is available in standard operation. The FAN3121/22 are available in a 3x3mm 8-lead thermally enhanced MLP package or an 8-lead SOIC package.

Application Information: The FAN3121 and FAN3122 series are available in TTL or CMOS input configurations. In the FAN3121T and FAN3122T, the input threshold meets the industry standard TTL logic threshold independent of the VDD voltage, with a hysteresis voltage of approximately 0.7V. These levels allow the input to drive voltages above 2V from a range of input logic signal levels to be considered logic high. The drive signal for this TTL input should have fast rising and falling edges with a spin rate of 6V/µs or faster, so the rise time from 0 to 3.3V should be less than or equal to 550ns. The FAN3121 and FAN3122 outputs can be enabled or disabled using the fast response en-pin. If en is not connected externally, the driver is enabled by default with an internal pull-up resistor. The logic threshold on the pin has a TTL or CMOS part on the threshold. In the FAN3121C and FAN3122C, the logic input threshold depends on the VDD level, and at 12V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The cmos input configuration provides a hysteresis voltage of approximately 17% of VDD. CMOS inputs can be used with relatively slow edges (near DC) if good decoupling and bypassing techniques are incorporated into the system design to prevent noise from violating the input voltage hysteresis window. This allows precise timing intervals to be set by installing an RC circuit between the control signal and the input pins of the driver. The slowly rising edge driver introduces a delay between the control signal and the outer pin of the driver. Quiescent Supply Current In the IDD (Static) Typical Performance Characteristics, the curve is floated (output low) by all inputs/enables and indicates the IDD current for the lowest quiescent test configuration. For additional current flowing through the 100kΩ resistor input and output, the actual quiescent idd current in these cases is the value from the curve plus the additional current. MillerDrive™ Gate Drive Technology The FAN312X gate driver incorporates MillerDrive™ for the output stage, a combination of bipolar and MOS devices providing a wide range of supply voltage and temperature variations. Bipolar devices carry output currents that fluctuate between 1/3 and 2/3 vdd and mos devices pull the output high or low rail. The purpose of the Miller Drive™ architecture is to provide fast switching of high peak currents by the driver when the gate-drain capacitance of the MOSFET acts as an on/off process for zero-voltage switching MOSFET switching applications, even if the Miller plateau does not exist. This often happens in synchronous rectifier applications because the diodes are usually turned on at the mosfet. The output pin slew rate is determined by the VDD voltage and the output load. It's not user adjustable, but you can increase the series resistance if the rise or fall is slow and it takes time at the mosfet gate.

Under Voltage Lockout (UVLO) FAN312X startup logic is optimized to drive a low voltage ground referenced N-channel mosfet lockout (uvlo) function to ensure orderly ic startup When VDD rises, but is below the 4.0V operating voltage, this circuit keeps Low output, regardless of the state of the input pins. When activated after that part, the supply voltage must be turned off at the part. This hysteresis helps prevent shock when low VDD supply voltages have come from power supply switching. This configuration is not suitable for driving a high-side p-channel mosfet because the output voltage of the driver will turn the p-channel mosfet on when VDD is below 4.0V. VDD Bypass and Layout Considerations The FAN3121 and FAN3122 are available in 8-lead SOIC or MLP packages. In either package, VDD pins 1 and 8 and ground pins 4 and 5 should be connected together on the PCB. In a typical FAN312X gate driver application, there are fewer power mosfet gates that require high current pulses to charge and discharge with a 50ns interval. Bypass capacitors with low ESR and ESL should be connected directly between the VDD and GND pins to provide unacceptable ripple on the VDD supply for these high current pulses. To meet these small size requirements, 1µf ceramic capacitors or larger are often used with a dielectric material, such as X7R , to limit changes in capacitance to temperature and/or voltage applications. Shows the pulsed gate drive current path as the gate driver provides gate charging when the mosfet is turned on. Current is provided locally by the bypass capacitor CBYP and flows through the gate of the driver mosfet to ground. Resistive and inductive in the peak current path possible with the FAN312X series is minimized. The role of the localized cbyp is to contain the peak current pulses in the high drive mosfet circuit, preventing interference with the circuit in the sensitive analog pwm controller.

Thermal Guide Gate drivers used to switch MOSFETs and IGBTs can dissipate a lot of power at high frequencies. It is important to determine driver power losses and the resulting junction temperature application to ensure components are within acceptable temperature limits. The total power dissipation in the gate driver is PGate and Pdynamic two components: ptotal=pgate+pdynamic (1) Gate drive loss: The maximum power loss provides the result of the gate current (unit charge time) Turn on and off the load mosfet switching frequency . Power Loss The result of driving a mosfet at a specified gate-source voltage vgs, gate charge qg, at switching frequency, fsw, determined by: pgate = qgvgsfsw (2) Dynamic pre-drive/penetration current: A due to internal current The power loss consumption under dynamic operating conditions, including pin pull-up/pull-down resistors, can be obtained using the "IDD (no load) vs. frequency" characteristic graph for typical performance to determine the current idyll extracted from vdd under actual operating conditions : PdynamicVDD(3) Once the power dissipation in the driver is determined, the driver junction rise relative to the board is evaluated using the following thermal equation, assuming Ψjb is for a similar thermal design (heat dissipation and airflow): Tj=ptotalΨjb+tb (4) where? Tj = driver connection temperature; Ψjb = (psi) related thermal characteristic parameters to the total power consumption; and tb = board temperature, see the thermal characteristic table for the definition. In a full-bridge synchronous rectifier application, each fan 3122 drives a combination of two high-current MOSFETs in parallel (eg FDMS8640S). Typical gate charge mosfet per sr is 70nc, vgs=vdd=9v. At a frequency of 300kHz on one switch, the total power consumption is: PGate=270NC9V300kHz=0.378W (5) Power=2mA9V=18mW (6) Toto=0.396W (7) SOIC-8 has a connection board heat Ψjb=42°c The characterization parameter of /w. system application, the ambient local temperature of the device is the printed circuit board as well as the surface airflow. To ensure reliable operation, the maximum connection must prevent the device from exceeding the maximum rating of 150°C; with 80% derating, TJ will be limited to 120°C. Rearrange Equation 4 to determine the required board temperature to keep the junction temperature below 120°C: Tb, max = Tj - ptotalΨjb(8) Tb, max = 120°C – 0.396W42°C/W=104° C(9) For comparison, please replace the previous 3x3mm MLP package showing Ψjb=2.8°C/W, the 3x3mm MLP package can operate at a PCB temperature of 118°C while keeping the junction temperature below 120°C. This illustrates that the physically smaller thermal pad MLP package provides a more conductive path to remove thermal drivers. Consider the circuit size reliability improvement in reducing the overall lower junction temperature.