The ADS8329/30 are high speed, low power, successive approximation register (SAR) analog-to-digital converters (ADCs) using an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function.

The ADS8329/30 has an internal clock for running conversions, but can also be programmed to run conversions based on the external serial clock SCLK.

The ADS8329 has one analog input. Analog input is provided to two input pins: +in and –in. When a conversion begins, the differential inputs on these pins are sampled on an internal capacitor array. During conversion, both the +in and –in inputs are disconnected from any internal functions.

The ADS8330 has two inputs. Both inputs share the same common pin COM. The negative input is the same as the –in pin of the ADS8329. The ADS8330 can be programmed for manual channel selection or automatic channel selection mode, which automatically scans between channels 0 and 1.

analog input

When the converter enters holdover mode, the voltage difference between the +in and –in inputs is captured on the internal capacitor array. The voltage at the input is limited between agnd – 0.2v and agnd+0.2v, allowing the input to reject the same small signal as the input. The +In input has a range of -0.2 V to Vref+0.2 V. The input range [+In–(–In)] is limited to 0 V to Vref.

The (peak) input current through the analog input depends on many factors: sample rate, input voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during sampling. After the capacitor is fully charged, there is no more input current. The analog input voltage source must be able to charge the input capacitor (45 pF) to a 16-bit stable level within the minimum acquisition time (120 ns). When the converter enters holdover mode, the input impedance is greater than 1 GΩ.

Attention must be paid to the absolute analog input voltage. To maintain the linearity of the converter, the +in and –in inputs and ranges [+in-(–in)] should be within the specified range. Outside these ranges, the linearity of the converter may be out of specification. To reduce noise, a low bandwidth input signal should be used with a low pass filter. Care should be taken to ensure that the output impedances of the sources driving the +input and -input are matched. If this is not observed, the two inputs may have different settling times. This can lead to offset errors, gain errors, and linearity errors that vary with temperature and input voltage.

driver amplifier selection

The analog input of the converter needs to be driven with a low noise op amp such as ths4031 or opa365. It is recommended to install RC filters at the input pins to low pass the source noise. Two 20Ω resistors and a 470 pF capacitor are recommended. The input to the converter is a unipolar input voltage in the range of 0 V to Vref. The minimum –3dB bandwidth to drive an op amp can be calculated as: f3db = (ln(2) ×(n+1))/(2π × tACQ)

When n is equal to 16, the resolution of the ADC (for ads8329/30). When tacq = 120ns (minimum capture time), the minimum bandwidth of the driver amplifier is 15.6mhz. If the application increases the acquisition time, the bandwidth can be relaxed. OPA365, OPA827 or THS4031 from Texas Instruments is recommended. The ths4031 used to drive the converter in a source follower configuration is shown in a typical input drive configuration, Figure 52. For the ADS8330, a 0Ω series resistor (or no resistor at all) should be used on the COM pin.

Bipolar to Unipolar Driver

In systems where the input is bipolar, the ths4031 can be used in a reverse configuration with an additional DC bias applied to its + input to keep the input to the ads8329/30 within its rated operating voltage range. This configuration is also recommended when the ADS8329/30 are used in signal processing applications that require good signal-to-noise ratio and THD performance. DC bias can be derived from ref3225 or ref3240 reference voltage ic. The input configuration shown in Figure 53 is capable of delivering better than 91 dB signal-to-noise ratio and -96 dB total harmonic distortion at an input frequency of 10 kHz. If a bandpass filter is used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small to minimize the distortion introduced by the filter. In this case, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ads8329/30 large to keep the signal-to-noise ratio of the system high. Note that in this configuration, the system gain from +input to the output of the ths4031 is a function of the ac signal gain. A resistor divider can be used to scale the output of the ref3225 or ref3240 to step down the voltage at the DC input to the ths4031 to keep the voltage at the converter input within its rated operating range.

references

The ADS8329/30 can operate with an external reference voltage in the range of 0.3V to 5V. To ensure good performance of the converter, a clean, low noise, well decoupled reference voltage needs to be available on this pin. A low noise bandgap reference like the ref3240 can be used to drive this pin. A 22µF ceramic decoupling capacitor is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as possible to the pins of the device. REF- should be connected to the analog ground plane over the shortest possible distance.

Inverter operation

The ADS8329/30 has an oscillator that is used as an internal clock to control the slew rate. The minimum frequency of this clock is 21mhz. The oscillator is always on unless the device is in a deep power-down state, or the device is programmed to use SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time requires 3 cclks (equivalent to 120ns at 24.5mhz), and the conversion time requires 18 conversion clocks (cclk) (about 780ns) to complete a conversion.

If desired, conversions can also be run according to the external serial clock sclk programming. This allows system designers to implement system synchronization. The serial clock sclk is first reduced to 1/2 its frequency before being used as the conversion clock (cclk). For example, for a 42mhz sclk, this provides a 21mhz clock for conversion. If a conversion needs to be started on a specific rising edge of sclk when the external sclk is programmed as the source of the conversion clock (cclk) (and manual start of conversion is selected), the setup time between convst and this rising sclk edge should be observed. This ensures that the conversion is done in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between convst and sclk. In many cases, a transition can start after one sclk cycle (or cclk), resulting in 19 cclk (or 37 sclk) transitions. Once the synchronization is relaxed, the 20 ns setup time is not required.

The duty cycle of sclk is not critical as long as it meets the minimum high and low time requirements of 8ns. Since the ADS8329/30 are designed for high speed applications, a higher serial clock (SCLK) must be provided to maintain high throughput through the serial interface, so the clock period of SCLK must not exceed 1 microsecond (used as the conversion clock (CCLK)). The minimum clock frequency is also controlled by parasitic leakage of capacitive digital-to-analog (CDAC) capacitors inside the ADS8329/30.

Manual channel selection mode

The conversion cycle begins with the selection of the acquisition channel by writing the channel number to the command register (cmr). This cycle time can be as short as 4 serial clocks (SCLK).

Automatic channel selection mode

Channel selection can also be done automatically if the automatic channel selection mode is enabled. This is the default channel selection mode. The ADS8330 dual-channel converter has a built-in 2-to-1 multiplexer. If the device is programmed for automatic channel selection mode, the signals from channel 0 and channel 1 are acquired in a fixed order. In the next cycle, channel 0 is first accessed after a command cycle with cfr_d11 to 1 configured for automatic channel selection mode. This automatic access stops looping after the command loop with cfr_d11 set to 0.

start conversion

The end of acquisition or sampling instance (EOS) is the same as when the conversion started. This is initiated by turning the convst pin low for at least 40 ns. The convst pin can be turned up after the minimum requirements are met. convst is independent of fs/cs, so a common convst can be used in applications that require multiple converters to sample/hold simultaneously. The ADS8329/30 switches from sample mode to hold mode on the falling edge of the convst signal. The ADS8329/30 require 18 conversion clock (CCLK) edges to complete the conversion. The conversion time is equivalent to 1500ns, and the internal clock is 12mhz. The minimum time between two consecutive convst signals is 21 cclks.

If programmed like this (cfr_d9=0), it is also possible to start the conversion without using convst. When the converter is configured to auto trigger, the next conversion automatically starts 3 conversion clocks (cclk) after the conversion ends. These 3 conversion clocks (cclk) are used as acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 cclks.

Status output eoc/int

When the status pin is programmed as EOC and the polarity is set to active low, the pin operates as follows: When programmed as a manual trigger, the EOC output goes low immediately after CONVST goes low. EOC remains low during the entire conversion process and returns high at the end of the conversion. If automatic triggering is programmed, the EOC output goes low 3 conversion clocks (CCLK) after the previous rising edge of EOC.

This status pin is programmable. When the low time is equal to the conversion time, it can be used as an EOC output (cfr_d[7:6]=1, 1). This status pin can be used as an int (cfr_d[7:6] = 1, 0), set low at the end of a conversion and set high (cleared) on the next read cycle. The polarity of this pin, used for either function (EOC or INT), is programmable via cfr_d7.

Power down mode

The ADS8329/30 have comprehensive built-in power-down capabilities. There are three shutdown modes: deep shutdown mode, NAP shutdown mode and automatic NAP shutdown mode. All three power-down modes are enabled by setting the relevant cfr bits. The first two power-down modes are active when enabled. Wakeup command 1011b may resume device operation from power down mode. Auto-off mode works a little differently. When the converter is enabled in automatic NAP shutdown mode, the End of Conversion Instance (EOC) puts the device into an automatic NAP shutdown state. The start of sampling will resume converter operation. The contents of the configuration registers are not affected by any power-down modes. When NAP or deep power down is initiated, any in-progress conversion will be aborted.

Deep Power Down Mode

Deep power-down mode can be activated by writing to configuration register bit cfr_d2. When the device is in deep power-down mode, all blocks except the interface are powered down. External SCLK is blocked to the analog block. The analog block no longer has bias current and the internal oscillator is turned off. In this mode, the supply current drops from 7 mA to 4 mA in 100 ns. Wake-up time after power down is 1 microsecond. When bit d2 in the configuration register is set to 0, the device is in a deep power-down state. Setting this bit to 1 or sending a wake-up command allows the converter to recover from a deep power-down state.

nap mode

In NAP mode, the ADS8329/230 turn off the biasing of the comparators and medium voltage buffers. In this mode, the supply current drops from 7 mA in normal mode to about 0.3 mA within 200 ns after the configuration cycle. Wake (recovery) time from NAP shutdown mode is 3 cclks (120 ns, 24.5 MHz transition clock). Once the cfr_d3 bit in the control register is set to 0, the device will enter nap power-down mode regardless of the transition state. Setting this bit to 1 or sending a wake-up command can cause the converter to recover from the NAP shutdown state.

Auto capture mode

Auto capture mode is almost the same as capture mode. The only difference is when the device is actually powered off and the method of waking up the device. Configuration register bit d4 is only used to enable/disable auto-NAP mode. If auto-capture mode is enabled, the device turns off the bias after the conversion is complete, which means the end of the conversion will activate auto-capture shutdown mode. The supply current drops from 7mA to around 200mA in normal mode. convst restores the device and turns the bias on again in 3 cclks (120 ns, 24.5 MHz conversion clock). The device can also be woken up by disabling automatic NAP mode when bit d4 of the configuration register is set to 1. Any channel select command 0xxxb, wakeup command or set default mode command 1111b can also wake up the device from auto power off NAP.

Note: 1. This wake-up command is word 1011b in the command word. This command sets bits d2 and d3 in the configuration register to 1, not d4. However, the wake command does remove the device from any of these shutdown states (deep/nap/auto nap power down). 2. Wake-up time is defined as the time between when the host processor attempts to wake up the converter and when the conversion starts.

Total acquisition + conversion cycle time:

Auto: =21 cclks; Manual: ≥21 cclks;

Manual + depth ≥ 4sclk + 100 microseconds + 3 cclk + 18 cclk + 16 sclk + 1 microsecond power off:

Manual+NAP power off: ≥4 SCLK+3 CCLK+3 CCLK+18 CCLK+16 SCLK;

Manual+Auto NAP≥4 SCLK+3 CCLK+3 CCLK+18 CCLK+16 SCLK (with wake-up recovery) power down:

Manual+Auto NAP≥1 cclk+3 cclk+3 cclk+18 cclk+16 sclk (recovered with convst) Power off:

digital interface

The serial clock is designed to accommodate the latest high-speed processors with SCLK frequencies up to 50MHz. Each loop starts from the falling edge of fs/cs. The contents of the internal data register, which is available to the output register at eoc, is displayed on the sdo output pin on the falling edge of fs/cs. This is msb. Output data is valid on the falling edge of SCLK with a TD (SCLKF-SDovalid) delay so that the host processor can read it on the falling edge. The serial data input is also read on the falling edge of SCLK.

A complete serial I/O cycle begins and ends on the first falling edge of SCLK after the falling edge of FS/CS 16 (see note) on the falling edge of SCLK. The serial interface is very flexible. It works with cpol=0, cpha=1 or cpol=1, cpha=0. This means that the falling edge of fs/cs may fall when sclk is high. The same slack applies to the rising edge of fs/cs, where sclk may be high or low, as long as the last falling edge of sclk occurs before the rising edge of fs/cs.

Note: In some cases, one cycle is 4 SCLKs or up to 24 SCLKs depending on the read mode combination.

internal register

The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for the configuration data register (CFR).

write converter

There are two different types of register writes, a 4-bit write to cmr and a full 16-bit write to cmr plus cfr. The command set is listed in Table 3. A simple command requires only 4 SCLKs, and writes take effect on the 4th falling edge of SCLK. A 16-bit write or read requires at least 16 SCLKs.

Configure Converters and Default Modes

The converter can be configured using command 1110b (write cfr) or command 1111b (default mode). A write to cfr requires a 4-bit command followed by 12-bit data. 4-bit commands take effect on the 4th falling edge of SCLK. A cfr write takes effect on the 16th falling edge of sclk.

The default mode command can be achieved by simply binding sdi to +vbd. Once the chip is selected, SCLK will record at least 4 1s. The default value of cfr is loaded into cfr on the fourth falling edge of sclk.

The cfr defaults are all 1s (except for cfr_d1, which is ignored by the ADS8329 and always reads as 0). The same defaults apply to cfr after power-on reset (por) and switch reset.

read configuration register

The host processor can read the value programmed in cfr by issuing command 1100b. The timing is similar to reading conversion results, except that convst is not used and there is no activity on the eoc/int pins. The cfr value read contains the first four msbs of the converted data plus the valid 12-bit cfr content.

read conversion result

The conversion result is available at the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift data out via the SDO pin at any time, except in quiet areas. This is 20 ns before and 20 ns after the end of sampling (EOS). End of sampling (EOS) is defined as the falling edge of convst when using a manual trigger, or as the end of the third conversion clock (CCLK) after EOC if an automatic trigger is used.

The falling edge of fs/cs should not be placed at the exact moment (at least one conversion clock (cclk) delay) at the end of the conversion (by default, when eoc goes high), otherwise the data is corrupted. If fs/cs is placed before the end of the conversion, the previous conversion result is read. If fs/cs is placed after the conversion is over, the current conversion result is read.

The result of the conversion is 16-bit data in straight binary format, as shown in Table 4. Typically 16 SCLKs are required, except when more than 16 SCLKs are required (see Table 6). The data output of the serial output (SDO) is left-adjusted msb first. Trailing bits are first padded with the flag bits (if enabled) plus all zeros. sdo stays low until fs/cs rises again. When fs/cs is low, sdo is active. The rising edge of fs/cs 3 indicates the sdo output.

Note: When sdo is not in 3-state (when fs/cs is low and sclk is running), part of the conversion result is output at the sdo pin. The number of bits depends on how many SCLKs are provided. For example, a manual select channel command cycle requires 4 SCLKs, so the SDO outputs 4 msbs of the conversion result. The exception is that the SDO outputs all 1s in the loop immediately after any reset (PoR or software reset).

If sclk is used as the conversion clock (cclk), and continuous sclk is used, then during the sample time (6 sclk) it is not possible to clock all 16 sdo bits due to quiet zone requirements. In this case, it is best to read the conversion results during the conversion (36 SCLKs or 48 SCLKs in auto-sleep mode).

label mode

ads8330 includes a feature tag that can be used as a tag to indicate which channel is the source of the conversion result. Adds an address bit after reading lsb from sdo indicating which channel the result came from if tag mode is enabled. The address bits for channel 0 are 0 and the address bits for channel 1 are 1. The converter requires more sclk than the 16 required for a 4-bit command, plus 12-bit cfr or 16 data bits (because of the additional flag bits).

chain mode

The ADS8329/30 can operate as a single converter or in a system with multiple converters. When using multiple converters, the system designer can take advantage of a simple high-speed SPI-compatible serial interface by cascading them in a chain. A bit in the CFR is used to reconfigure the EOC/INT status pin as the secondary serial data input, the chain data input (CDI), for the conversion result of the upstream converter. This is a chained operation. A typical connection for three converters is shown in Figure 59.

When using multiple converters in chained mode, the first converter is configured in regular mode and the remaining converters downstream are configured in chained mode. When the converter is configured in chained mode, the cdi input data goes directly into the output registers, so the serial input data passes through the converter with 16 sclk (if the tag function is disabled) or 24 sclk delay, as long as cs is active. See Figure 60 for specific times. During this timing, the conversions in each converter are performed simultaneously.

Cascade manual trigger/read while sampling

When the converter is operating in chained mode, care must be taken to handle multiple CS signals. During the entire data transfer, the different chip select signals must be low (48 bits for the three converters in this example). The first 16-bit word after falling chip select is always the data from the chip that received the chip select signal.

Case 1: If the chip select is not toggled (CS remains low), the next 16 bits are the data from the upstream converter, and so on. As shown in Figure 60. If there is no upstream transformer in the chain, like transformer 1 in the example, the same data from the transformer will be repeated.

Case 2: As shown in Figure 61, if the chip select is toggled during a chain mode data transfer cycle, the same data from the converter is read repeatedly during all three discrete 16-bit cycles. This is not an ideal result.

Figure 62 shows a slightly different scenario where convst is not shared by the second converter. Converter 1 and Converter 3 have the same convst signal. In this case, converter 2 only passes the previous converted data downstream. The number of SCLKs required for a serial read cycle depends on the combination of different read modes, flag bits, chain modes, and channel selection methods (ie, automatic channel selection).

SCLK skew between converters and datapath delays through converters configured in chain mode affect the maximum frequency of SCLK. Latency is also affected by supply voltage and load. When the device is configured in chain mode, it may be necessary to reduce the speed of SCLK.

reset

The converter has two reset mechanisms, a power-on reset (por) and a software reset using cfr d0. These two mechanisms do not hold up internally. When a reset is issued (software or POR), all register data are set to default values (all 1s) and SDO outputs (during the period after reset) are set to all 1s. The state machine is reset to the powered state.

Figure 64. Digital output in reset state

When the device is powered on, when the avdd reaches 1.5v, the por sets the device to default mode. When the device is powered off, the por circuit requires the avdd to stay below 125mv for at least 350ms to ensure proper discharge of the internal capacitors and correct the behavior of the adc when powered up again. If AVDD drops below 400 mV, but remains above 125 mV, the internal Por capacitors are not fully discharged and the device needs a software reset to perform correctly after AVDD is restored (this situation is undefined in Figure 65 area shown).

Parts Change Notice 20071101001

The ADS8329 and ADS8330 devices have silicon changes per Texas Instruments Part Change Notification (PCN) number 20071101001. Details on this part change can be obtained from Texas Instruments' Product Information Center or by contacting your local sales/distribution office. This PCN covers devices with date codes 82xx and above.