feature

Low power consumption with minimal impact on battery life Multiple power-down modes AC-coupled with DC balancing 100NA in standby mode, 5mA typical operating conditions Up to 24 bits Up to 20MHz Parallel Interface Operating Voltage Conversion from 1.65V to 3.6V Ultra-Small and Cost-Effective Package High ESD Protection: >7.5kV HBM Parallel I/O Power Supply (VDDP) ranging from 1.65V to 3.6V

application

Microcontrollers or Pixel Interface Image Sensors Small Displays Liquid Crystal Displays, Cell Phones, Digital Cameras, Portable Game Consoles, Printers, PDAs, Video Cameras, Automotive General Description: FIN24C μserdes is a low power serializer/can help minimize cost Deserializers (serdes) and the ability to transmit wide signal paths. By using serialization the number of signals transmitted from one point to another can be significantly reduced. Typical reduction ratios for unidirectional paths are 4:1 to 6:1. For bidirectional operation, the signal reduction can be increased to nearly 10:1 using a half-duplex source. By using differential signaling, shielding and emi filters can also be minimized, further reducing the cost of serialization. Differential signaling is also important to provide a noise-insensitive signal that can withstand radio and electrical noise sources. The dramatic reduction in power consumption makes an impact on battery life in ultraportable applications. A unique word boundary technology ensures word boundaries are identified when deserializing data. This ensures that each word is properly aligned in the deserializer word by word through a unique sequence of clocks and data that does not repeat except word boundaries. One pll is sufficient for most applications, including bidirectional operation.

Embedded word clock operation The FIN24C transmits and receives serial data sources in synchronization with the bit clock. The bit clock is modified to create a word boundary word at the end of each data. Word boundaries are skipped by low clock pulses. This appears in the sequence as a clock stream of three consecutive times where the signal CKSO is still high. To implement this scheme, two additional data bits are required. During the word boundary phase, the data switches to high then low or low then high depending on the last bit of the actual data word. Some actual data words and data words with word boundary bits added are provided. Note that during serial transfers, 24-bit words are expanded to 26 bits. Bits 25 and 26 are defined relative to bit 24. Bit 25 is always the reciprocal of bit 24, and bit 26 is always the same as bit 24. This ensures that "0"-"1" "1"-"0" transitions are always in the embedded word stage with CKSO high. The serializer generates and embeds word boundary data bits and boundary clock conditions into the serial data stream. The deserializer looks for the word boundary condition data at the end to capture and transfer to the parallel port. The deserializer only uses the data to find and capture. These boundary bits are in the words sent to the parallel port. The lvcmos data i/olvcmos input buffer has a nominal threshold value equal to half VDDP. Input buffers are only operational when the device is running as a serializer. When the device is running as a deserializer, the input is closed to save power. The LVCMOS tri-state output buffers are rated at 1.8V with a source/sink current of 2mas. The output is active when the DIRI signal is asserted low. When the diri signal is asserted high, the bidirectional lvcmosI/O is in the high Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Unused LVCMOS input buffers must be tied to an active logic low or active logic high to prevent quiescent current consumption caused by floating inputs. Unused LVCMOS outputs should be left floating. Unused bidirectional pins should pass through high value resistors. If the FIN24C device is configured as a one-way serializer, unused data I/O can be used as unused input. If FIN24C is used as a deserializer, unused date I/O can be treated as unused output.

The differential I/O circuit FIN24C adopts FSC's proprietary CTL I/O technology. CTL is a low power, low EMI differential swing I/O technology. The ctl output driver generates a constant output source and sink current. The CTL input receiver senses current difference and direction from its connected output buffer. This is the same as LVDS, which uses a constant current source output, but a voltage sense receiver. Like lvds, input source termination resistors are used to properly terminate the transmission line. The FIN24C device contains internal termination resistors on the CKSI receiver and gated internal termination resistors on the DS input receiver. Gated termination resistors ensure termination regardless of the direction of data flow. The relatively high sensitivity of the current sensor CTL allows it to be driven at lower currents and lower voltages. In power-down mode, the differential input is disabled and powered down, and the differential output is in the high-z state. The CTL inputs have an inherent failsafe feature that supports floating inputs. when? The serializer's cksi input pair is unused, it can be left floating reliably. Or both inputs can be grounded. The CTL input can never be connected to VDD. It should be allowed to float when the deserializer's ckso output is unused. The phase locked loop circuit ckref input signal is used to provide a phase locked loop. The pll generates internal timing signals capable of transmitting data signals at 26 times the speed of the input ckref. The output of the PLL is a serial data stream. There are two ways to disable the pll: input mode 0 state (s1=s2=0) or the s1 and s2 signals when a low power-on is detected. Any other mode is done by asserting s1 or s2 high and providing the ckref signal input. The PLL goes through the lock sequence after powering up. Waits the specified number of clock cycles to the port before capturing valid data into the parallel system. When the µSerdes chipset goes from a powered-off state (s1, s2=0, 0) to a powered-on state (eg s1, s2=1, 1), the ckp on the deserializer will transition low for a short time and then return to high. After that, the deserializer's signal level at ckp corresponds to the serializer's signal level. Another way to shut down the pll is to stop the ckref signal (high or low). Internal circuitry detects the lack of conversion and turns off the PLL serial I/O off. However, the internal reference is not disabled, allowing the PLL to power up and relock in fewer clock cycles than when exiting mode 0. When a transition is seen on the ckref signal, the PLL is reactivated.