benefit

Fully optimize system efficiency. Higher levels of efficiency compared to traditional discrete methods are achievable components. Save up to 50% of PCB space compared to discrete solutions. higher frequency of operation. Simplifies system design and board layout. Reduce time component selection and optimization.

feature

12V Typical Input Voltage Output Current Up to 30A500kHz Switching Frequency Internal Adaptive Gate Driver Integrated Bootstrap Diode Peak Efficiency >90% Undervoltage Lockout Out of Phase Shutdown Output Disabled Low Profile SMD Package RoHS Compliant Driver Plus high current synchronous mosfet power stage solution for buck dc-dc applications. The device integrates a driver chip and two power mosfets, 8mm x 8mm, 56-pin, space-saving POWER88 8482 ; components. Fairchild Semiconductor Integrated Circuits The method utilizes a holistic solution to the dynamic performance of the drive field effect transistor, system inductance and resistance. The traditional discrete solution of the package parasite and the problem layout associated with it is greatly reduced. This comprehensive approach results in significant board space savings, thus maximizing footprint power density. This solution is based on the Intel™ DRMOS specification.

application

Desktop and server VR11.x V-core and non-V-core buck converters. Gaming consoles and high-end CPU/GPU powered desktop systems. High Current DC-DC Point of Load (POL) Converter Networks and Telecom Microprocessor Voltage Regulators Small Voltage Regulator Modules

Operation Description: The circuit description is a driver plus fet module optimized for synchronous buck conversion topology A single PWM input signal is all that is required to pre-drive the high-side and The low-side mosfets. Each part can drive the speed Up to 500khz. The low-side driver and the low-side driver (LDRV) designed to drive a ground referenced low RDS() n-channel mosfet than an internal connection between VCIN and CGND. When the driver is set, the output of the driver is a 180 degree phase output. The PWM input is low when the driver fails. High-side driver The high-side driver (HDRV) is designed to drive float. The biasing of the N-channel mosfet high-side driver is developed by a lifter supply circuit, which is started by built-in diodes and external capacitors Doolin, VSWH supports PGND, allowing CBoot to charge up to through the internal diodes. When the PWM input starts high, the HDRV will start filling High-side gates during this transition, loads from CBOOT and transported to Q1' as Q1 turns around, VSWH liters wine, forcibly pushes wine+vc+boot, which provides enough boost to complete the switching cycle, Q1 is switched by HDRV to VSWH. That's charging to VCIN when VSWH falls to PGND. High-definition output PWM input stage high-side gate is low when the driver fails. The adaptive gate driver circuit driver chip uses an advanced design that ensures minimal mosfet dead-time penetration (cross-conduction) currents that eliminate the potential. It senses the MOSFETs and adaptively adjusts the gate drives to make sure they don't act at the same time. See Figures 24 and 25 for related timing waveforms. To prevent overlap during low-to-high transitions (Q2 off to Q1 on), the adaptive circuit monitors the voltage on the LDRV pin. When the PWM signal goes high, Q2 will start to turn off after some propagation delay (tpdl(ldrv)). Once the LDRV pin discharges below ~1.2V, Q1 starts to turn on after an adaptive delay TPDH (HDRV). To prevent overlap during high-to-low transitions (Q1 off to Q2 on), the adaptive circuit monitors the voltage pin at the switch. When the PWM signal goes low, Q1 will start to turn off after some propagation delay (tpdl(hdrv)). Once the VSWH pin drops below ~2.2V, after an adaptive delay, Q2 starts to turn on TPDH (LDRV). In addition, the first quarter VGS was monitored. When vgs(q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in no matter the software state after TPDH(LDRV). This function is implemented to ensure that cboot charges every switch cycle, especially as the power converter current drops, the switch voltage does not drop below the 2.2V adaptive threshold. Second time delay TPDH (HDRV) is longer than TPDH (LDRV)

Supply Capacitor Selection For the power supply input (vcin) of the fdmf8700, a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1µF, X7R or X5R capacitors. Place this capacitor close to the FDMF8700 vcin and CGND pins. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (cboot) as well as internal diodes, selecting these components should be done after the high side mosfet has been selected. Determining the required capacitance uses the following formula: where qg is the total gate charge of the high-side mosfet and ∏vboot is the voltage drop allowed by the high-side mosfet driver. For example, the QGmosfet on the internal high voltage side is about 21nc@12vgs. The allowable sag is about 300 mV, and the required bootstrap capacitance is greater than 100 mV. Good quality ceramic capacitors must be used. where fsw is the switching frequency of the controller. The peak surge current rating of the internal diodes in the circuit should be checked, as this depends on the equivalent impedance of the entire boot circuit, including the pcb lines. For applications requiring higher intermediate frequencies, an external diode can be used in parallel with the internal diode. The printed circuit board layout guide shows the FDMF8700 and key parts. All high current paths such as vin, vswh, VOUT and GND copper should be short and wide for better stable current flow, heat dissipation and system performance. The following are guidelines that pcb designers should follow 1. Input bypass capacitors should be close to the VIN and ground pins of the fdmf8700 that help reduce the input current ripple component caused by switching operations. 2. The minimum area of VSWH copper reduces switching noise emissions. The VSWH copper traces should also be wide enough to accommodate high currents. Other signal routing should be considered such as the pwm input and the path of the pilot signal taking care to avoid noise pickup from the vswh copper area. 3. The output inductor should be placed as close to the FDMF8700 as possible to reduce power loss due to copper traces. 4. Place ceramic bypass capacitors and startup capacitors close to the VCIN and pilot pins of the FDMF8700 to stabilize power supply. Trace width and length should also be considered. 5. Use multiple vias on each copper area to interconnect the top, inner and bottom of each via to help smooth current and heat conduction. Vias should be relatively large and reasonably inductive.