feature

Highly flexible dual synchronous switching pwm controller includes the following modes: – DDR mode channel interference with non-inverting operation – 90° phase shift two-stage DDR mode input ripple – dual independent regulators 180 ° phase shift Complete DDR memory power solution – VTT tracks VDDQ/2 – VDDQ/2 buffered reference output Low-side mosfet or precision current sensing VCC using sense resistors under voltage lockout Wide power input range: 3 to 16V Excellent dynamic response and voltage feed forward Average current mode Control power good signal also supports DDR-II and HSTLTSSOP28 packages

application

DDR VDDQ and VTT Voltage Generation Desktop Computer Graphics Card General Description: The FAN5026 PWM controller provides high efficiency and two output voltages adjustable from 0.9V to 5.5V for powering I/O, chipset, and high Repository box and VGA card in performance computer. Synchronous rectification helps achieve high efficiency over a wide range of loads. The efficiency is to use the rds(on) of the mosfet as the current sensing component. Feedforward ramp modulation, average current mode control scheme and internal feedback compensation for fast response to load transients. The 180-degree phase shift of out-of-phase operation reduces input current ripple. This controller can be converted into a full DDR memory by activating designated pins to provide a power solution. In the DDR operating mode one channel tracks the output voltage of the other channel and provides the output current sink and power supply capability - features for proper powering of the DDR chip. Buffered references also provide the voltages needed for this memory. The FAN5026 monitors these outputs and generates a separate PGX (Power Good) signal output when the soft-start is complete within ±10% of the set value. Built-in overvoltage protection prevents the output voltage from exceeding 120% of the set value. Normal operation is to automatically resume leaving when the overvoltage condition disappears. When the soft-start sequence at this output has completed. The adjustable overcurrent function works by sensing the voltage drop across the lower mosfet. If precision current sensing is required, an external current sense resistor can optionally be used.

Circuit Description: Overview FAN5026 is a multi-mode, dual-channel PWM controller for graphics chipsets, SDRAM, DDR DRAM or other low output voltage power supply applications in PCs, VGA cards and set-top boxes. The integrated circuit integrates control circuits for the two synchronous buck converters. The output voltage can be set in the range of 0.9V to 5.5V per controller. external resistor divider. These two synchronous buck converters can operate from an uncontrolled DC source (such as a laptop battery) with voltages ranging from 5.0V to 16V, or 3.3V to 5V from the system rail. In either mode of operation, the IC is biased from the +5V supply. The pwm modulator uses average current mode control with input voltage feedforward to simplify feedback loop compensation and improve line management. Both pwm controllers have integrated feedback loop compensation to reduce the number of external components. The FAN5026 can be configured as a complete operational DDR solution. The second channel provides the ability to track the output voltage when the DDR pin is set high. the first channel. Prevents the PWM2 converter from entering hysteresis mode if the DDR pin is set high. In DDR mode, the buffered reference voltage (buffered voltage is provided by the REF2 pin required by the DDR memory chip through the PG2 pin. Since the current limit tolerance is largely dependent on the ratio of the external resistors, if the voltage on the RSENSE switch node side The drop is an accurate representation of the load current. When using a mosfet as a sensing element, a change in rds (on) results in a proportional change in iSN. This value does not vary only from device to device, but also has a typical junction temperature coefficient of about 0.4%/°C (refer to the mosfet data sheet of the actual value), so the actual value current limit setting value will decrease proportionally as the temperature of the mosfet chip increases. The current coefficient is 1.6 The limit setting value should compensate for all mosfet rds (on) changes, It is assumed that the heat sink of the mosfet will keep its working die temperature below 125°C.

More precise sensing can be achieved by using resistors. (r1) in place of the rds(on) 11 of the field effect transistor shown in the figure. This approach incurs higher losses, but yields greater gains in VDroop and iLimit accuracy. r1 is a low value (eg 10MΩ) resistor. The current limit (Ilimit) should be set high enough to allow the inductor current to rise briefly in response to the output load. Typically, a factor of 1.3 is sufficient. Also, since Ilimit is a peak current cutoff value, we need to multiply iLoad(max) by the inductor ripple current (we will use 25%) for the gate driver section adaptive gate control logic to convert the internal pwm control signal input mosfet gate drive signal Provides necessary magnification, horizontal movement and penetration protection. In addition, it has features that help optimize the performance of integrated circuits under various operating conditions. Because the switching time of the MOSFET can be determined from the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-source voltage of the upper and lower MOSFETs. This will not drive the next mosfet on by more than about 1 volt until the gate-source voltage of the previous mosfet drops lower. Again, the mosfet above is until the low voltage gate-to-source voltage mosfet has dropped below about 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without consideration for simultaneous conduction, or shoot-through. There must be a low resistance, low inductance path between the driver pin and the gate of the mosfet for the adaptive dead time circuit to work properly. Any delayed paths will be subtracted from the adaptively generated delay where dead-band circuits and shoot-through may occur. Frequency Loop Compensation Due to the realization of current mode control, the modulator has a unipolar ring with a slope of -1 at a frequency determined by the load. In the unipolar ring type, ro is the load resistance and co is the load capacitance. For this type of modulator, a type 2 compensation circuit is usually sufficient. Reducing the number of external components simplifies the design task, this pwm controller has an internally compensated error amplifier. Amplifiers and their responsive current-mode modulators and converters. Type 2 In addition to the pole at the origin, the amplifier has a pole-zero pair, at the zero and the pole. This region is also associated with a phase "bump" or "reduced" phase shift. The amount of phase shift reduction depends on the width of the flat gain region, with a maximum of 90 degrees. To further simplify converter compensation, the modulator gain is independent of the input voltage by providing the oscillator with a forward varying ramp of the VIN.

Zero frequency, amplifier high frequency gain and modulator gain selected to suit most typical applications. The crossover frequency will appear where the modulator attenuation equals the amplifier high frequency gain. The only task the system designer must complete is to specify the location of the output filter capacitors where the dominant pole of the load is somewhere below the zero frequency of the amplifier within a decade. With this compensation due to the pole-zero, it is easy to obtain sufficient phase margin to pair the phase "boost". Only when the main load pole is positioned too far to the left of the axis in frequency due to excessive output filter capacitance. In this case, ESR zeros in the range 10KHz...50KHz give some additional "boost" stage. Fortunately, in mobile applications, the trend is to keep the output capacitor as small as possible. If larger inductance values or lower ESR values are required for applications, additional phase margin can be achieved by disposing of zeros at the lc crossover frequency. This can be achieved by a capacitor on the feedback resistor to protect the inverter output from being monitored and protected from extreme overload, short circuit, overvoltage and undervoltage conditions. A continuous overload on the output sets the PGX pin low to lock the entire chip. Operation can be resumed by cycling the VCC voltage or by toggling the EN pin. If VOUT falls below the undervoltage threshold, the chip shuts down immediately. Overcurrent Sensing If the circuit's current limit signal ("ILIM DET", is high at the beginning of the clock cycle, the pulse skip circuit is activated and HDRV is inhibited. The circuit continues to jump in this manner for the next 8 years clock cycle. If loops anytime between 9 and 16, reaches "ILIM DET" again, sets overcurrent protection latch, disables chip "ILIM DET" does not occur between cycles 9 and 16, resumes normal operation over current The circuit resets automatically. Choice of power mosfet The losses in a mosfet are its switching (psw) and conduction (pcond) losses. In a typical application, the output of the fan5026 converter is low in voltage relative to the input voltage, so the lower The mosfet (q2) is cycling most of the time. Therefore, q2 should be chosen to minimize conduction losses, thus selecting a mosfet with low RDS(ON). In contrast, the high-side mosfet (q1) has a shorter RDS(ON). The duty cycle and therefore its conduction loss effect. However, most of the switching losses occur in the first quarter, so the main selection criterion for Q1 should be the gate charge. The switching spacing of the high-side loss mosfet, of which the drain is shown above The voltage and current sources on and the graphs below detail vg versus time constant current charges the gate. So the x-axis is also the gate charge (QG). CISS=CGD+CGS, which controls T1, T2 and T4 time. The CGD receive current is sent from the gate driver during T3 (when VDS falls). The charge (QG) parameter is - available or available from the MOSFET datasheet. Assume switching losses occur at the rising and falling edges, i.e. Q1's Switching losses pass through the mosfet when it has voltage.

Layout Considerations Switching converters, even during normal operation, generate short pulses of current if layout constraints are not observed. There are two sets of key components in DC-DC converters. Switching power supply components handle energy at high rates and are noise generators. Low-power components responsible for biasing and feedback functions are sensitive to noise. A multilayer printed circuit board is recommended. Specifies a solid layer for the ground plane. Dedicate another solid layer as a power layer and break this plane into a smaller island of common voltage levels. Note all nodes subject to high dv/dt voltages eg sw, hdrv and ldrv. All surrounding circuits will tend to couple from these nodes through stray capacitance. Don't make too many copper wires connecting to these nodes. Do not leave traces connected to adjacent feedback component traces. The use of high-density interconnect systems or microvias on these signals is not recommended. Using blind or buried vias should limit the low current range to only signals. The use of normal thermal vias is left to the discretion of the designer. Keep the routing trace source from the IC to the gate of the mosfet as short as possible, capable of handling a peak current of 2A. Minimize the area within the gate source to reduce stray inductance and eliminate parasitic pathways before gate ringing. Locate small critical components, such as soft-start capacitors and current-sense resistors, as close as possible to individual IC pins. FAN5026 adopts advanced packaging technology with a lead pitch of 0.6mm. High-performance simulations utilizing narrow lead-pitch semiconductors may require special considerations in PWR design and fabrication. Keeping the area properly clean is critical around these devices. It is not recommended to use any type of rosin or acid cored solder, or the use of flux manufacturing or repair processes that may cause corrosion or generate electromigration and/or eddy current sensitive low current signals near the current. when? The use of chemicals like these on or near the PWB is recommended to wash and dry the entire pressurized water tank completely before energizing.