feature

Industry Standard Pinout 4.5-V to 18-V Operating Range 5-A peak sink/source at VDD=12V; 4.3-A sink/2.8-A source at VOUT=6V; TTL or CMOS input threshold selection Three versions Dual independent drivers: - Dual Invert + Enable (FAN3223) - Dual Non-Invert + Enable (FAN3224) - Dual Input (FAN3225) - Internal resistor shuts down driver if no input MillerDrive 8482 ; technology 12 ns/9 ns Typical rise/fall time (2.2-nf load); 20 ns typical propagation delay matched to another channel Dual current capability of 1ns parallel channel 8-lead 3x3 mm MLP or 8-lead SOIC package Ambient temperature from -40°C to +125°C Automotive Qualified to AEC-Q100 (Version F085)

application

Software Itch Mode Power Efficient Mosfet Switch Itch Synchronous Rectifier Circuit DC-DC Converter Motor Control Automotive Qualification System (Version F085)

describe

The FA N3223-25 dual 4A gate driver family is designed to drive N-channel enhancement mode MOSFETs in low-side SW itch applications providing high peak current pulses at short SW intervals. The driver can select TTL or CMOS input thresholds. Internal circuitry provides an undervoltage lockout function by keeping the output low until the supply voltage is within the operating range. Additionally, the driver characteristics and the internal propagation delay between the A and B channels are timed for applications that require dual gate drivers, such as synchronous rectifiers. This also supports connecting TWO drivers in parallel to efficiently drive a single mosfet with twice the current capacity. The FA N322X driver contains the architecture of the final output stage of MillerDrive™. This bipolar mosfet combination minimizes switching losses at the miller platform level of the mosfet switch while providing rail-to-rail voltage switching and reverse current capability. The FAN3223 provides two inverting drivers and the fan3224 provides two non-inverting drivers. Each device has dual independent enable pins, which are open and unconnected by default. In the FA N3225, each channel has two inputs of opposite polarity, allowing S to be configured as non-inverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, the internal resistor biases the input and output to be pulled low to keep the power MOSFET off.

application information

Each member of the input threshold FA N322X driver family includes two identical channel current ratings that can be used independently or a single current capacity in parallel. On FA N3223 and FA N32 24, channels A and B can be enabled or disabled independently using ena or enb respectively. En for thresholds with CMOS or TTL inputs. If ena and enb are not connected, internal pull-up resistors make the driver channel by default. ena and enb have ttl thresholds in parts with ttl or cmos inx thresholds. If the input and output of channel A and channel B are paralleled to increase the drive current capacity, ENA and ENB should be connected together. The FA N322X series offers TTL or CMOS input thresholds. In the fan322xt, the input threshold meets the industry standard TTL logic threshold independent of the VDD voltage with a hysteresis voltage of approximately 0.4V. These levels allow signal levels to be considered logic high at voltages over 2V from a range of input logic drive inputs. The drive signal for the TTL input should have fast rising and falling edges with a slew rate of 6 V/µs or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. Reduced slew rate and circuit noise can cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, resulting in unstable operation. In the fan322xc, the logic input threshold is dependent on the VDD level, when VDD is 12V, the logic rising edge threshold is about 55% of VDD and the input falling edge threshold is about 38% of VDD. The CMOS input configuration provides a hysteresis voltage of approximately 17% of VDD. This CMOS input can use relatively slow edges. (Approaching DC) If good decoupling and bypassing techniques are included in the system design prevents noise from corrupting the input voltage hysteresis W. This allows for the passage of the control signal and the driver's pins. The slowly rising edge of the driver's pin is the control signal and the driver's output pin. The quiescent supply current generates a curve in IDD (static) typical performance characteristics with all inputs/floating (output) enabled) and indicates the test configuration. For other states, additional current flows through the input and 100 kΩ resistors on the output shown as n in the block diagram of each section. In these cases, the actual quiescent idd current is the value obtained from the curve plus the additional current. MillerDrive™ Gate Drive Technology The FA N322X gate driver incorporates the MillerDrive™ architecture for the output stage, a combination of bipolar and MOS devices that provide variations in supply voltage and temperature. Bipolar devices carry most of the current between 1/3 and 2/3 of the output switch vdd and mos devices pull the output high or low rail. The MillerDrive™ architecture is designed to act as an on/off process through the gate-to-drain capacitance mosfet in the miller plateau region. For the switching interval in the MOSFET, the driver provides high peak current for fast switching itch despite the absence of Miller plateau. This situation often occurs in synchronous rectifier applications because the body diode is usually switched on in the mosfet. The output pin slew rate is determined by the VDD voltage and the output load. It is not user adjustable, but the series resistance can be increased if the rise or fall time is slow. needs to be at the mosfet gate.

Undervoltage Lockout The FAN322X startup logic is optimized to drive the low voltage grounded N-channel mosfet lockout (uvlo) function, ensuring that the ic starts up in an orderly manner. When VDD rises, but falls below the uvlo level, the circuit maintains a low output regardless of the state of the input pins. When activating after that part, the supply voltage must be turned off in the part down. This hysteresis helps prevent chattering when a low VDD supply voltage has come from the power switch. This configuration is not suitable for driving a high-side p-channel mosfet because the output voltage of the driver will turn the P-channel power density below uvlo mosfet VDD bypass capacitor guidelines To make this IC fast turn on the device, local high frequency bypass capacitor, CBYP, low ESRESL should be connected to V DD and the ground pin of minimum trace length. This capacitor is typically a 47µF bias circuit on the driver and controller in addition to the bulk electrolytic capacitor, which is 10µF. A typical criterion for choosing the value of cbyp is to keep the ripple voltage on the VDD supply less than or equal to 5%. This usually reaches the load capacitance ceqv at a value greater than or equal to 20 times, defined here as qgate/vdd. A common choice for 0.1µf to 1µf or larger ceramic capacitors, such as X5R and with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, CBYP can be increased to 50-100 times CEQV, or cbyp can be divided into tw-o capacitors. One should be a larger value based on the equivalent load capacitance, and another smaller value like 1-10nf mounted closest to the VDD and GND pins to carry the higher frequency content of the current pulse. This bypass capacitor must supply from both driver channels, if the driver sw-itching at the same time, the composite peak current from the CBYP ice should be as large as the W-hen one channel is sw-itching. Layout and Hookup Guidelines The FA N3223-25 series gate drivers include fast-reacting input circuitry, short propagation delays, and power stages capable of outputting current peaks in excess of 4 A to facilitate voltage transition times below 10 ns to over 150 ns. The following layout and hookup guidelines are strongly recommended: Keep high current output and power ground paths separate from logic and enable input signal and signal ground paths. It is especially important to handle TTL level logic threshold inputs and enable pins in the driver. Minimize the length of the high-current traces as close to the load as possible. This reduces series inductance to improve high-speed switching itching, while reducing circuitry that can radiate EMI around the driver input. If the input of the channel is not connected externally, instruct the internal 100 kΩ resistor on the block diagram to command the low output. In noisy environments, it may be necessary to use a short output switch on an unused channel to prevent noise from causing spurious traces. Many high-speed traction circuits can be susceptible. from their outputs or other external sources, may cause the outputs to retrigger. These effects can be apparent if the circuit is tested in a breadboard or a non-optimal circuit layout with long input, enable, or output leads. For best results, keep all pin connections as short and direct as possible. The Fan 322X is compatible with many other industry standard drivers. To enable the pin in a single input part, there is an internal 100 kΩ resistor connected to vdd to enable the driver by default; this should be considered in the PCB layout. On and off current paths should be minimized, as described in the next section. The pulsed gate drive current path is shown when the pole driver provides gate charge to turn on the MOSFET. Current is provided locally by the bypass capacitor, CBYP, and S current through the driver mosfet gate and ground. To reach the peak possible peak current, resistive and inductive paths should be minimized. The localized cbyp behavior contains peak current pulses in the driver bank circuit, preventing them from interfering with sensitive analog circuits in the pwm controller.

Thermal Guide Gate drivers used to switch mosfets and igbt high frequency can consume a lot of pow. It is important to determine driver power losses and the resulting junction temperature application to ensure components are within acceptable temperature limits. The total power dissipation in the gate driver is two components, pgate and pdynamic: ptotal = pgate + pdynamic (1) pgate (gate drive losses): the most significant power supply losses (per unit time) due to gate current switching Switch the load mosfetsw frequency. Energy Dissipation Drives the MOSFET at the specified gate-source voltage vgs to generate gate charge qgsw The frequency, fsw, is determined by: pgate = qgvgsfswn(2)w where n is the number of driver channels in use (1 or 2). Dynamic (Dynamic Pre-Drive/Through Current): Power loss due to internal current consumption under dynamic operating conditions, including pin pull-up/pull-down resistors. Internally it can be estimated using current consumption (dynamic). Typical current-determining performance characteristics Practical idyll drawing conditions for vdd: Pdynamic = idyllic VDDN(3) where n is the number of driver ICs being used. Note that n is usually an IC, even if the IC has two channels, unless two or more driver ICs are heavily loaded in parallel with driver A. Once the power dissipation in the driver is determined, the driver junction rises with respect to the board CAN and is evaluated using the following thermal equation, assuming a similar thermal design (heat dissipation and airflow) Tj=ptotalΨjb+Tb(4)W: Here: Tj=driver connection temperature; Ψjb = (psi) thermal characteristic parameter total power dissipation versus temperature rise; and tb = board temperature, defined in the thermal characteristic table. To give a numerical example, assume a 12 V VDD (VBIAS) system with a synchronous rectifier switch gate total charge of 60 NCVGS = 7V. Therefore, parallel TWO devices 120 NC gate charge. At 300 kHz, the total power loss is: Pgate = 120 NC7 volts at 300 kHz Thermal Ψjb=42°c/w. Characterization parameter system application, local temperature around the device is the surface of the printed circuit board with airflow. To ensure reliable operation, the maximum connection must prevent the temperature of the device from exceeding the maximum rating of 150°C; W, 80% derated, TJ W will be limited to 120°C. Rearrange Equation 4 to determine the required board temperature to keep the junction temperature below 120°C: Tb, max=Tj-ptotalΨjb(8) Tb, max=120°C–0.54 W42 °C/W=97° C