General Instructions

The AD9238 is a dual, 3V, 12-bit, 20MSPS/40MSPS/65MSPS analog-to-digital converter (ADC). It features dual high-performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multi-stage differential pipeline structure with output error correction logic to provide 12-bit accuracy and guarantee no code loss over the entire operating temperature range at data rates up to 65 msps. The broadband, differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for a variety of applications, including multiplexed systems that switch full-scale voltage levels in continuous channels, and sampling inputs at frequencies well in excess of the Nyquist rate.

Dual single-ended clock inputs are used to control all internal conversion cycles. Duty cycle stabilizers are available to compensate for wide variations in the clock duty cycle, allowing the converter to maintain good performance. Digital output data is displayed in binary or two's complement format. The out-of-range signal indicates an overflow condition, and it can be used with the most significant bit to determine a low or high overflow. Fabricated on an advanced CMOS process, the AD9238 is available as a lead-free, space-saving 64-lead LQFP or LFCSP, and is specified over the industrial temperature range (-40°C to +85°C).

Product Highlights

1. Pin compatible with AD9248, 14-bit 20MSPS/40 MSPS/65 MSPS ADC.

2. Speed grade options are 20ms/sec, 40ms/sec and 65ms/sec, allowing flexible choice between power, cost and performance to suit the application.

3. Low power consumption: AD9238-65: 65 msps=600 megawatts, AD9238-40: 40 msps=330 megawatts, AD9238-20: 20 msps=180 megawatts.

4. Typical channel isolation is 85dB@f=10MHz.

5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/AD9238-65) maintains performance over a wide range of clock duty cycles.

6. Multiple data output option allows single port operation from data port A or data port B.

Features: Integrated dual 12-bit ADC; single 3 V supply operation (2.7 V to 3.6 V); SNR = 70 dB (to Nyquist, AD9238-65); SFDR = 80.5 dBc (to Nyquist, AD9238-65) ); low power: 300 mW/channel at 65 msps; differential input, 500 MHz, 3 dB bandwidth; excellent crosstalk immunity >85 dB; flexible analog input: 1 V PP to 2 V PP range; bias Shifted binary or two's complement data format; clock duty cycle stabilizer; output datamux option.

Applications: Ultrasonic equipment; direct conversion or IF sampling receivers; WB-CDMA, CDMA2000, WiMAX; battery powered instruments; handheld oscilloscopes; low cost digital oscilloscopes.

the term

Aperture delay

SHA performance is measured from the rising edge of the clock input to when the input signal is held transitioning.

Aperture jitter

Aperture delay variation for successive samples, manifested as noise at the ADC input.

Integral Nonlinearity (inl)

The deviation of each individual code for the line drawn from negative full scale to positive full scale. Points used as negative full scale occur 1/2 lsb before the first code transition. Positive full scale is defined as 1.5 LSBs past the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

Differential Nonlinearity (DNL, No Missing Codes) The ideal ADC shows a transcoding of exactly 1 lsb interval. dnl is the deviation from this ideal value. Guaranteeing no missing codes at 12-bit resolution indicates that all 4096 codes must be present in all working ranges.

offset error

When the analog value is less than vin+=vin-, a large carry conversion should occur. Offset error is defined as the deviation of the actual transition point from this point.

gain error

The first code transition should occur at 1/2 LSB of the analog value above negative full scale. The last conversion should occur at the analog value 1.5 lsb below the nominal full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

temperature drift

Temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the tmin or tmax value.

Power supply rejection

The specification shows the maximum change in full scale, from the value when the supply is at the minimum limit to the value when the supply is at the maximum limit.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first six harmonic components to the rms value of the input signal under test, expressed as a percentage or decibels relative to the peak carrier signal (dbc).

Signal-to-noise ratio measures the rms value of the input signal and the rms sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC. The value of sinad is expressed in db.

Effective number of digits (enob) using the following formula: ENOB=(SINAD-1.76)/6.02; ENOB can be calculated directly from its measured Snad for a sine wave input device with a given input frequency.

signal to noise ratio

Measures the ratio of the rms value of the input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC. The signal-to-noise ratio is expressed in decibels.

Spurious Free Dynamic Range (SFDR)

The difference in decibels between the rms amplitude of the input signal and the peak spurious signal, which may or may not be a harmonic.

Nyquist sampling

When the frequency components of the analog input are below the Nyquist frequency (f/2), this is often referred to as Nyquist sampling.

IF sampling

ADCs are not limited to Nyquist sampling due to aliasing effects. Higher sampling frequencies alias to the first Nyquist zone (DC-F/2) on the ADC output. The bandwidth of the sampled signal should not overlap with the Nyquist zone and aliasing. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies). clock

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be imd products.

Out of range recovery time

The time it takes for the ADC to regain the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

crosstalk

When an adjacent interfering channel is driven by a full-scale signal, couples to one channel driven by a (-0.5 dbfs) signal. Measurements include all spurs due to direct coupling and mixed components.

theory of operation

The AD9238 consists of two high performance ADCs based on the AD9235 converter core. The dual ADC paths are independent except for the shared internal bandgap reference source vref. Each of the ADC paths consists of a proprietary front-end SHA followed by a pipelined switched capacitor ADC. The pipeline ADC is divided into three parts, including 4-bit first stage, 8 1.5-bit stages and the last 3-bit flash. Each stage provides enough overlap to correct flash errors in previous stages. The quantized output of each stage is combined by a digital correction logic block into a final 12-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the corresponding clock.

Each stage of the pipeline (excluding the last stage) consists of a low-resolution flash ADC and a residual multiplier that drives the next stage of the pipeline. The remaining multipliers use the flash ADC outputs to control switched capacitor digital-to-analog converters (DACs) with the same resolution. The DAC output is subtracted from the stage's input signal, and the remainder is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called multiplying dac (mdac). A bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last level consists of a flash adc.

The input stage contains a differential SHA, which can be configured as AC or DC coupled in differential or single-ended mode. The output scratch block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted.

analog input

The analog input to the AD923 is a differential switched capacitor SHA, which is designed for optimum performance when dealing with differential input signals. The SHA input accepts inputs over a wide common-mode range. To maintain optimum performance, it is recommended to use the input common-mode voltage of the power supply.

The SHA input is a differential switched capacitor circuit. In Figure 32, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA switches to sampling mode, the signal source must be able to charge the sampling capacitor and stabilize within half the clock period. Small resistors in series with each input can help reduce the peak transient current required to drive the source output stage. Additionally, small shunt capacitors can be placed on the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In undersampling applications, any parallel capacitors should be removed. Combined with the driving source impedance, they limit the input bandwidth. For best dynamic performance, the source impedances driving vin+ and vin- should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the ADC's common mode rejection.

Internal differential reference buffers generate positive and negative reference voltages reft and refb, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to "medium supply", and the reference voltage and reference voltage range are defined as:

The above equations show that the reft and refb voltages are symmetrical around the mid-supply voltage, and by definition the input span is twice the value of the vref voltage.

The internal voltage reference can be pin-fixed to a fixed value of 0.5 V or 1 V, or adjusted within the same range as discussed in the Internal Reference Connections section. Set the ad9238 to a maximum input range of 2v pp for maximum signal-to-noise performance. When switching from 2vp-p mode to 1vp-p mode, the relative signal-to-noise ratio decreases by 3db.

The SHA can be driven from a source that keeps the signal peaks within the allowable range of the selected reference voltage. The minimum and maximum common-mode input levels are defined as:

The minimum common-mode input level allows the AD9238 to accommodate ground-referenced inputs. While the best performance is obtained with differential inputs, single-ended sources can be driven to either vin+ or vin-. In this configuration, one input accepts a signal, while the other input should be set to midscale by connecting it to the appropriate reference. For example, a 2 volt PP signal can be applied to VIN+, while a 1 volt reference voltage can be applied to VIN-. Then, the ad9238 receives an input signal that varies between 2v and 0v. In a single-ended configuration, the distortion performance can be significantly reduced compared to the differential case. However, this effect is less pronounced at lower input frequencies and lower speed grade models (AD9238-40 and AD9238-20).

Differential Input Configuration

As previously mentioned, the best performance is achieved when driving the AD9238 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and flexible interface to ADCs. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Salun key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is insufficient to achieve the true performance of the AD9238. This is especially useful for undersampling applications with sampling frequencies in the 70mhz to 200mhz range. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 33.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and too much signal power can also saturate the core, causing distortion.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, the sfdr and distortion performance is degraded due to large input common mode oscillation. However, if the source impedances at each input are matched, there should be little impact on the SNR performance.

Clock Inputs and Considerations

Typical high speed ADCs use two clock edges to generate various internal timing signals and, as a result, may be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9238 provides separate clock inputs for each channel. Clocks operating at the same frequency and phase achieve the best performance. Timing channels asynchronously can significantly degrade performance. In some applications, it is desirable to skew the clock timing of adjacent channels. The independent clock inputs of the AD9238 allow clock timing skew between channels (typically ±1ns) without significant performance degradation.

The AD9238 contains two clock duty cycle stabilizers, one for each converter, to retime non-sampling edges, providing an internal clock with a nominal 50% duty cycle. Maintaining a 50% duty cycle clock is especially important in high speed applications when proper track and hold times for the converter are required to maintain high performance. It is difficult to maintain a tightly controlled duty cycle on the input clock on the PCB. DCS can be achieved by connecting the DCS pin high.

The duty cycle stabilizer uses a delay locked loop to create non-sampling edges. So any change in sampling frequency takes about 2µs to 3µs to allow the dll to acquire and settle to the new rate.

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. The SNR degradation at a given full-scale input frequency (f) due only to aperture jitter (t) can be calculated as:

In the equation, the rms aperture jitter, t, represents the root sum squared of all jitter sources, including the clock input, the analog input signal, and the ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

For best performance, especially where aperture jitter can affect the dynamic range of the AD9238, it is important to minimize input clock jitter. The clock input circuit should use a stable reference; for example, use the analog power and ground planes to generate valid high and low numbers for the AD9238 clock input. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Consumption and Standby Modes

The power consumption of the AD9238 is proportional to its sampling rate. Digital (drvdd) power consumption is primarily determined by the strength of the digital driver and the load on each output bit. Digital drive current can be passed through: where n is the number of bits changed and c is the average load on the changed digital pins.

The analog circuits are optimally biased, so each speed grade provides excellent performance while reducing power consumption. Each speed grade dissipates baseline power at a low sampling rate that increases with increasing clock frequency.

Any channel of the AD923 can enter standby mode. This is done independently by asserting the pdwn_a or pdwn_b pins. It is recommended that the input clock and analog input remain static during stand-alone or full standby, which will result in a typical power consumption of the ADC of 1 mW. Note that if dcs is enabled, the clocks for the independent power-down channels must be disabled. Otherwise, significant distortion will occur on the active channel. Typical power consumption of 12 mW is incurred if the clock input remains active in total standby mode.

(PDWN_A = PDWN_B = HI) is reached when both channels are in full power down mode (pdwn_a = pdwn_b). In this case, the internal reference will be closed. When one or both channel paths are enabled after a power-down, the wake-up time is directly related to the recharge of the reft and refb decoupling capacitors and the duration of the power-down. Typically, it takes about 5 ms to restore full operation with fully discharged 0.1µf and 10µf decoupling capacitors on reft and refb.

digital output

The AD968 output driver can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interface logic. The output drivers are sized to provide enough output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

The data format can be selected as offset binary or two's complement. See the Data Formats section for details.

timing

The AD9238 provides a latched data output with a pipeline delay of seven clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal. The PD internal duty cycle stabilizer can be enabled on the AD9238 using the DCS pin. This provides a stable 50% duty cycle internal circuit.

The length and loading of the output data lines should be minimized to reduce transients within the AD9238. These transients can impair the dynamic performance of the converter. The minimum typical conversion rate of the AD9238 is 1 msps. Dynamic performance may degrade when clock rates are below 1 ms/sec. Single channel can save power, save medium power. The power-down channel shuts down the internal circuitry, but the reference buffer and shared reference remain powered. Wake-up time is reduced to a few clock cycles as the buffers and voltage reference remain powered.

Data Format

The AD923 data output format can be configured as two's complement or offset binary. This is controlled by the data format selection pin (dfs). Connecting dfs to agnd produces offset binary output data. Conversely, concatenating dfs to avdd will format the output data as two's complement.

Output data from the dual ADCs can be multiplexed onto a single 12-bit output bus. Multiplexing is accomplished by toggling the mux_select bit, which directs channel data to the same or opposite channel data port. When mux_select is logic high, channel a data is directed to the channel a output bus and channel b data is directed to the channel b output bus. When mux_select is logic low, the channel data is inverted, that is, channel a data is directed to the channel b output bus, and channel b data is directed to the channel a output bus. Multiplexed data can be used on either output data port by toggling the mux_select bit.

This same clock can be applied to the MUXYSELY PIN if the ADC is running with synchronized timing. Any skew between CKKYA, CLKHYB and MUXYSEAD will degrade AC performance. It is recommended to keep clock skew <100ps. After the rising edge of mux_select, either data port has the data of its respective channel; after the falling edge, the data of the alternate channel is put on the bus. Typically, other unused buses will be disabled by setting appropriate oeb high to reduce power consumption and noise. Figure 34 shows an example of the multiplexing mode. When multiplexing data, the data rate is twice the sampling rate. Note that in this mode, both channels must remain active, and the power down pin of each channel must be held low.

voltage reference

The AD9238 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD923, using the internal reference with a different external resistor configuration or an externally applied reference voltage. The input range of the adc tracks the linear variation of the reference voltage. If the ADC is driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).

Internal reference connection

The comparator in the AD9238 senses the potential at the sense pin and configures the reference into four possible states, as shown in Table 7. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 35), setting VREF to 1 V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a 0.5 V reference output. As shown in Figure 36, if a resistive divider is connected, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

In all reference configurations, reft and refb drive the ADC core and establish its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

It may be necessary to use an external reference to improve the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs are tracking each other, a single reference (internal or external) may be required to reduce gain matching errors to acceptable levels. A high-accuracy external reference can also be selected to provide lower gain and offset temperature drift. Figure 37 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes. When the detect pin is bound to avdd, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (reft and refb) for the ADC core. The input range is always twice the value of the reference voltage; therefore, the external reference voltage must be limited to a maximum of 1V. If the AD9238's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts the effect of the load on the internal reference voltage.

AD9238 LQFP Evaluation Board

The evaluation board supports the AD9238 and AD9248 and has five main parts: clock circuit, input, reference circuit, digital control logic, and output. Below is a description of each part. Table 8 shows the jumper settings and comment assumptions in the comment column.

The evaluation board requires four power connections to TB1: analog power for the DUT, power for the onboard analog circuits, power for the digital driver DUT, and power for the onboard digital circuits. It is recommended to use separate analog and digital supplies, with 3 V nominal on each supply. Each power supply is separate on board, and each IC includes the DUT, decoupled locally. All ground should be tied together.

Clock circuit

The clock circuit is designed for a low jitter sine wave source, AC coupled and level shifted before driving a 74vhc04 hex inverter chip (u8 and u9) whose output provides the clock to the part. Potentiometers (R32 and R31) on the horizontal shift circuit allow the user to vary the duty cycle as desired. The amplitude of the sine wave must be large enough to be within the trip point of the hexagonal inverter and within the power supply to avoid clipping noise. To ensure a 50% duty cycle inside the part, the AD9238-65 has an on-chip duty cycle stabilizer circuit that is enabled by inserting jumper JP11. The duty cycle stabilizer circuit can only be used when the clock frequency is higher than 40ms/sec.

Each channel has its own clock circuit, but usually both clock pins are driven by a 74VHC04 and solder jumper JP24 is used to connect the clock pins together. When the clock pins are connected together and only one 74VHC04 is used, the other channel's series termination resistor (R54 or R55, depending on which inverter is used) must be removed.

A data capture clock is created for each channel and sent to the output buffer for use in the data capture system when needed. Jumpers JP25 and JP26 are used to invert the data clock if necessary, and can be used to debug the data capture timing.

question.

analog input

The AD9238 achieves best performance with differential inputs. The evaluation board has two input options for each channel, a transformer (xfmr) and an ad8138, both of which perform single-ended to differential conversion. The xfmr has the best high frequency performance and the AD8138 is ideal for DC evaluation, low frequency inputs and differentially driving ADCs without loading a single ended signal.

The common mode level of both input options is set to provide IF from a resistive divider on the AVDD supply, but can also be driven from an external supply (using test points) TP12, TP13 for AD8138S and TP14, TP15 for XFMRS . To reduce distortion of the full-scale input signal when using the AD8138, place JP17 and JP22 in position B, and place the external negative supply on TP10 and TP11.

For best performance, use a low-jitter input source and a high-performance bandpass filter after the signal source and before the evaluation board (see Figure 39). For the xfmr input, use solder jumpers jp13, jp14 (for channel a) and jp20, jp21 (for channel b).

For AD8138 input, use solder jumpers JP15, JP16 for channel A and JP18, JP19 for channel B. Remove all soldering from unused jumpers.

Reference circuit

The EV kit circuit allows the user to select the reference mode via a series of jumpers and to provide an external reference if necessary. Refer to Table 9 to find the jumper settings for each reference mode. The external reference on the board is a simple resistor divider/zener diode circuit buffered by an AD822 (U4). The pot (R4) can be used to change the level of the external reference to fine tune the ADC full scale.

digital control logic

The digital control logic on the evaluation board is a series of jumpers and pull-down resistors that serve as digital inputs on the AD9238 for the following pins: power-down and output-enable bars for each channel, duty-cycle recovery circuitry, dual-complement output mode, Shared reference mode and MUX_select pins. See Table 8 for jumper locations for normal operation.

output

The outputs of the AD9238 (and the data clock discussed earlier) are buffered by the 74VHC541S (U2, U3, U7, U10) to ensure proper loading of the DUT outputs, and additional drive capability for the next part of the system. The 74VHC541S are latches, but on this evaluation board they are wired and act as buffers. If desired, the data clocks can be tied together using JP30. If the data clock is bound, either R39 or R40 must be removed, depending on the clock circuit being used.

Dual ADC LFCSP PCB

LFCSP PCBs require low jitter clock sources, analog sources, and power supplies. The PCB interfaces directly with the Analog Devices Standard Dual Channel Data Acquisition Board (HSC-ADCEVAL-DC), which together with ADI's ADC Analyzer™ software allows for fast ADC evaluation.

power connector

Power is supplied to the board through three removable four-wire power strips.

analog input

The evaluation board accepts a 2 V PP analog input signal at the ground center of the two SMB connectors (input A and input B). These signals are terminated on the primary side of their respective transformers. T1 and T2 are broadband RF transformers that provide single-ended to differential conversion, allowing the ADC to be driven differentially, minimizing even order harmonics. The analog signal can be low-pass filtered on the transformer secondary to reduce high frequency aliasing.

Optional op amp

The PCB has been designed to accommodate the optional AD8139 op amp as a convenient solution for DC-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36. Place r22, r23, r30 and r24.

clock

The clock inputs are buffered on the boards of U5 and U6. These gates provide buffered clocks for on-board latches u2 and u4, adc input clock, and dra and drb available at output connectors p3, p8. The clock can be inverted on the timing jumper of the corresponding clock mark. The clock path also offers various termination options. The ADC input clock can be set to bypass the buffers at P2 to P9 and P10, P12. Optional clock buffers U3, U7 can also be placed. Clock inputs can be bridged on TIEA, TIEB (R20, R40) to allow one clock to clock both channels from one clock source; however, best performance is obtained by driving J2 and J3.

voltage reference

The ADC detection pin is brought out to E41, and the internal reference mode is selected by connecting a jumper wire from E41 to ground (E27). External reference mode is selected by placing jumpers between E41 to E25 and E30 to E2. R56 and R45 allow programmable reference mode selection.

data output

The ADC output is locked on the PCB of U2 and U4. The ADC output has a recommended series resistance to limit the effect of switching transients on ADC performance.