Features 8-pin solution without sense line voltage Reduces external components Wide range Universal AC input voltage Fixed 65 kHz operating frequency Maximum duty cycle 97%
Output Over/Under Voltage Protection Input Loss of Field Protection Cycle-by-Cycle Peak Current Limiting Open-Loop Detection Low Power Consumption User Control Standby Mode Applications Power Factor Correction
The ucc28019 8-pin active power factor correction (pfc) controller uses a boost topology operating in continuous conduction mode (ccm). The controller is suitable for systems in the 100W to >2kW range and accepts a wide range of universal AC line input. Startup current during undervoltage lockout is less than 200 μA. The user can control the low-power standby mode by pulling the VSENSE pin below 0.77 V.
The average current mode control is adopted without input line sensing, which realizes low-distortion waveform shaping of the input current and reduces the number of single components of the material. Simple external networks allow flexible compensation of current and voltage control loops. The switching frequency is fixed internally and adjusted to better than 5% accuracy at 25°C. Fast 1.5 A peak gate current drives external switches.
Many system level protection features include peak current limit, soft overcurrent detection, open loop detection, input brown output detection, output overvoltage protection/undervoltage detection, no-supply discharge path on VCOMP, and overload protection on ICOMP. Soft-start limits the boost current during startup. Trim's internal reference provides accurate protection thresholds and regulation setpoints. An internal clip limits the gate drive voltage to 12.5V.
Typical application diagram

application information
UCC28019 Operation
The ucc28019 is a switch mode controller for boost converters for power factor correction operating at fixed frequency in continuous conduction mode. The UCC28019 requires few external components to operate as an active power factor correction preregulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz, ensuring that both fundamental and second harmonic components of the conducted EMI noise spectrum are below the EN55022 conducted band measurement limit of 150 kHz.
Its tightly trimmed internal 5V reference provides precise output voltage regulation over a typical world-wide 85V to 265V AC mains input range from zero to full output load. Available system loads range from 100w to 2kw and can be extended in special cases.
The adjustment is done in two loops. Under continuous inductor current conditions, the inner current loop forms the average input current to match the sinusoidal input voltage. Under very light load conditions, depending on the boost inductor value, the inductor current may be discontinuous, but despite the higher harmonics, it still meets the requirements of class d according to IEC 1000-3-2. An external voltage loop regulates the output voltage on VCOMP (depending on line and load conditions), and VCOMP determines an internal gain parameter to maintain a low distortion steady state input current waveform power supply
The UCC28019 operates from an external bias supply. It is recommended that the device be powered by a regulated auxiliary power supply. This device is not intended for use with a bootstrap bias supply. The bootstrap bias supply is fed by the input high voltage through a resistor with sufficient capacitance on VCC to maintain the voltage on VCC until current can be supplied from the bias winding on the boost inductor. The minimum hysteresis of VCC requires an unreasonable value of hold capacitor.
During normal operation, when the output is regulated, the current drawn by the device consists of the rated operating current plus the current supplied to the gate of the external boost switch. The decoupling of the bias supply must account for switching currents in order to keep the ripple voltage on VCC to a minimum. From VCC to GND, a minimum 0.1µF ceramic capacitor is recommended, with short and wide traces.

Device Supply States The device bias operates in several states. During startup, VCC undervoltage lockout (UVLO) sets the minimum operating DC input voltage for the PFC controller. There are two uvlo thresholds. The controller turns on when the uvlo turn-on threshold is exceeded. If VCC falls below the UVLO lower shutdown threshold, the controller will shut down. During the uvlo process, the current consumed by the device is minimal. After the unit starts, soft start (SS) is initiated and the output is increased in a controlled manner to reduce stress on external components and prevent output voltage overshoot. During soft-start, after output regulation, the device draws its normal operating current. If any of several fault conditions are encountered, or if the device is put into standby by an external signal, the device will consume a reduced standby current.
The output vcomp of the soft-start voltage loop transconductance amplifier is pulled low during uvlo, ibop and olp (open loop protection)/standby. After the fault is removed, the soft-start controls the rate of rise of VCOMP to obtain linear control of the duty cycle over time. During soft-start, a constant 30µA current is fed into the compensation element, causing the voltage on this pin to rise linearly until the output voltage reaches 85% of its final value. At this point, the source current begins to decrease until the output voltage reaches 95% of its final rated voltage. The soft-start time is determined by the choice of voltage error amplifier compensation components and is user-programmed according to the desired loop crossover frequency. Once vout exceeds 95% rate voltage, edr will no longer be suppressed

Soft-Start System Protection System-level protection features keep the system within safe operating ranges:

output protection status
VCC undervoltage lockout (UVLO)
During startup, uvlo keeps the device off until vcc rises above the 10.5-v enable threshold vccon. With a typical 1v uvlo hysteresis to eliminate noise, the device will shut down when vcc drops to the 9.5v disable threshold vcc off.

Input Brown Output Protection (IBOP)
The VINS (Sense Input Line Voltage) input provides the designer with a way to set the desired supply rms voltage level at which the PFC preregulator should start, Vac (on), and the desired supply At the rms voltage level, it should be off, Vac (disconnected). This prevents unnecessary continuous operation of the system at or below the "brown output" voltage, where excessive line current may overheat components. Additionally, since the VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that might not trigger the VCC UVLO shutdown.

Input Brown Output Protection (IBOP)
The input line voltage is sensed directly from the rectified AC supply voltage through a resistor divider filter network, providing a scaled and filtered value at the VINS input. When VINS falls below (from high to low) 0.8 V, IBOP puts the device in standby mode, VINS brownout_th. When VIN rises (from low to high) by more than 1.5 V, the device will come out of standby. The Ivins_0 V bias current from VINS is less than 0.1 μA. With such a low bias current, there is little concern about any set point error caused by this current flowing through the sensing network. The highest reasonable resistance value for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Note that higher resistor values are more susceptible to noise pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the type of resistors used and their voltage ratings, rvins1 should employ multiple series resistors to reduce voltage stress.

Open Loop Protection/Backup (OLP/Backup)
If the output voltage feedback element fails and disconnects (open loops) the VSENSE input signal, the voltage error amplifier may increase the gate output to the maximum duty cycle. To prevent this, the internal pull-down force vSense is low. If the output voltage drops below 16% of the rated voltage, causing VSENSE to drop below 0.8V, the device is in standby, i.e. the PWM switching is stopped, and the device is still on, but consuming less than 3 mA of standby current . This shutdown feature also gives the designer the option to pull vSense low using an external switch.
Output Undervoltage Detection (uvd)/Enhanced Dynamic Response (edr)
Enhanced dynamic response (edr) can speed up the slow response of the low bandwidth voltage loop under large load changes

Overvoltage protection, open loop protection/backup overcurrent protection

The inductor current is induced by a low value resistor rsense in the input rectifier loop. The other side of the resistor is connected to system ground. Voltage is induced on the rectifier side of the sense resistor, and the voltage is always negative. There are two overcurrent protection functions: peak current limit (PCL) to prevent inductor saturation, and soft overcurrent (SOC) to prevent output overload.
Soft Overcurrent (SOC) / Peak Current Limit (PCL)
Soft overcurrent (SOC)

SOC limits input current. When the current sense voltage on the ISENSE reaches -0.73V, the SOC is activated, affecting the internal VCOMP level and adjusting the control loop to reduce the PWM duty cycle.
Peak Current Limit (pcl)
The peak current limit operates on a cycle-by-cycle basis. When the current-sense voltage on the iSense reaches -1.08 V, the PCL is activated, terminating the active switching cycle. The voltage of ISENSE is amplified by a fixed gain of -1.0, and then the leading edge is covered to improve noise immunity against false triggering.

gate driver

The gate output uses a current-optimized structure to directly drive large-value MOSFET total gate capacitance at high switching speeds. An internal clamp limits the voltage on the gate of the mosfet to 12.5v. The external gate drive resistor rgate limits the rise time and suppresses ringing caused by the parasitic inductance and capacitance of the gate drive circuit, thereby reducing EMI. The final value of the resistor depends on parasitic elements and other considerations related to the layout. Between the gate and ground, a 10-kΩ resistor close to the mosfet gate discharges stray gate capacitance and prevents accidental dv/dt triggering of turn-on.
Current Loop The entire system current loop consists of a current averaging amplifier stage, a pulse width modulator (pwm) stage, an external boost inductor stage and an external current sensing resistor.
The negative polarity signals of the ISENSE and ICOMP function current sense resistors are buffered and inverted at the ISENSE input. The internal positive signal is then averaged by a current amplifier (GMI) whose output is the ICOMP pin. The voltage across icomp is proportional to the average inductor current. Add a grounded external capacitor to the icomp pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is determined by the internal VCOMP voltage. This gain is non-linear to accommodate the worldwide AC line voltage range. The icomp is internally connected to 4v when the device is in fault or standby.
Pulse Width Modulator

The pwm stage compares the icomp signal to a periodic ramp to generate a leading edge modulated output signal that is high when the ramp voltage exceeds the icomp voltage. The slope of the ramp is defined by a nonlinear function of the internal VCOMP voltage.
At the beginning of the cycle, the pwm output signal triggered by the internal clock always starts low. The output remains low for a minimum off-time, toff (min), after which the ramp rises linearly to intersect the icomp voltage. The intersection of the ramp icomp determines toff, and therefore doff. Since doff=vin/vout in the boost topology equation, and vin is a sinusoidal waveform, and icomp is proportional to the inductor current, the control loop forces the inductor current to follow the input voltage waveform to maintain boost regulation. Therefore, the average input current is also sinusoidal.
control logic
The output of the PWM comparator stage is passed to the gate driver stage, which is controlled by various protection functions integrated into the IC. The gate output duty cycle can be as high as 99%, but always has a minimum off-time toff (min). Normal duty cycle operation can be interrupted directly by the OVP and PCL on a cycle-by-cycle basis. UVLO, IBOP and OPL/Stand also terminate the gate output pulse and further inhibit the output until SS operation begins.
voltage loop
The outer control loop of the pfc controller is the voltage loop. The circuit is composed of pfc output sensitive stage, voltage error amplifier stage and nonlinear gain generating circuit.
The output sense resistor divider network from the pfc output voltage to gnd constitutes the sense block of the voltage control loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulated reference voltage.
As with the VINS input, the very low bias current at the VSENSE input allows selection of the highest practical resistor value for the lowest power dissipation and backup current. Small capacitors from vsense to gnd are used to filter signals in high noise environments. The filter time constant should typically be less than 100 microseconds.
Voltage Error Amplifier The output current produced by the transconductance error amplifier (GMV) is proportional to the difference between the voltage feedback signal at vsense and the internal 5-V reference voltage. This output current charges or discharges the compensation network capacitor on the VCOMP pin to establish a VCOMP voltage suitable for system operating conditions. Proper selection of compensation network components can achieve a stable pfc preregulator over the entire AC line range and 0-100% load range. The total capacitance also determines the rate of rise of the VCOMP voltage during soft-start, as previously described.
During any fault or standby state, the amplifier output VCOMP is pulled to GND to discharge the compensation capacitor to the initial zero state. Typically, large capacitors have a series resistance that delays full discharge by their respective time constants (perhaps a few hundred milliseconds). If the vcc bias voltage is removed quickly after the uvlo, the normally discharged transistor on the vcomp will lose driving force and a large amount of voltage may be left on the large capacitor, negating the benefits of the subsequent soft start. The ucc28019 includes a parallel discharge path without vcc bias to further discharge the compensation network after vcc is removed.
When the output voltage disturbance is greater than 5%, the amplifier will exit linear operation. During overvoltage, the ovp function acts directly to turn off the gate output until vsense returns to within 5% of the regulation value. In a brown-out condition, the uvd function calls the edr, which immediately increases the internal vcomp voltage by 2v and increases the external vcomp charge current to typically 100µA to 170µA. This higher current helps charge the compensation capacitor to the new operating level faster, improving transient response time.
Nonlinear gain generation
The voltage at vcomp is used to set the current amplifier gain and pwm ramp. As mentioned before, this voltage is buffered internally and then modified by the edr and soc functions.
As vcomp changes, the current gain and pwm slope are adjusted together to suit different system operating conditions (set by AC line voltage and output load level), providing a low distortion, high power factor input current waveform.
Layout Guidelines As with all pwm controllers, the effectiveness of filter capacitors on signal pins depends on ground return integrity. The pins of the UCC28019 are ideal for separating high di/dt induced noise on the power supply ground from the low current quiet signal ground required for adequate noise immunity. In the ground plane of the printed circuit board, the star point ground of the GND pin of the device can be simply cut off, and the capacitors on ISENSE, VINS, VCOMP, and VSENSE (C11, C12, C15, C17, and C16, respectively) must return directly to The quiet part of the ground plane, indicated by the signal GND, not the high current return path of the converter, as indicated by the power supply GND.