Features: 300 MHz internal clock rate; fsk, bpsk, psk, chirp, am operation; dual integrated 12 digital-to-analog converters (DACs); ultra-high-speed comparators, 3ps rms jitter; excellent dynamic performance; 100 MHz ( ±1 MHz) 80 dB SFDR at output; 4× to 20× programmable reference clock multipliers Dual 48-bit programmable frequency registers; dual 14-bit programmable phase offset registers; 12-bit programmable amplitude modulation and on/off output shaping Keying function Single-pin FSK and BPSK data interface; PSK capability through input/output interface; linear or nonlinear FM chirp function and single frequency point frequency hold function; frequency ramp fsk; automatic two-way frequency sweep; x-correction; simplified control interface; 10 MHz serial 2-wire or 3-wire SPI compatible; 100mhz parallel 8-bit programming; 3.3V single supply; multiple power-down capabilities; single-ended or differential input reference clock; small 80-lead LQFP or TQFP , with exposed padding.

Applications: Flexible quadrature low frequency synthesis; programmable clock generators; FM chirp sources for radar and scanning systems; test and measurement equipment; commercial and amateur RF exciters; less than 25 ps rms total jitter in clock generator mode.

General Instructions

The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology coupled with two internal high-speed, high-performance quadrature DACs to form digitally programmable I and Q synthesizer functions. When referenced to an accurate clock source, the AD9854 produces highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as agile LOs in communications, radar, and many other applications. The innovative high-speed DDS core of the AD9854 provides 48-bit frequency resolution (1 μHz tuning resolution for 300 MHz system CLK). Keeping 17 bits ensures excellent SFDR.

The circuit structure of the AD9854 allows the simultaneous generation of quadrature output signals at frequencies up to 150 MHz.

100 million new frequencies per second. The sine wave output (externally filtered) can be converted to a square wave by an internal comparator for flexible clock generator applications. The device provides two 14-bit phase registers and a single pin for bpsk operation.

For higher order PSK operations, the I/O interface is available for phase change. 12-bit i and q digital-to-analog converters, coupled with an innovative dds architecture, provide excellent wideband and narrowband output sfdr. If quadrature functions are not required, the Q DAC can also be configured as a user-programmable DAC. When configured with a comparator, the 12-bit control DAC facilitates static duty cycle control in high-speed clock generator applications.

Two 12-bit digital multipliers allow programmable amplitude modulation, on/off output shaping keying and precise quadrature output amplitude control. A chirp function is also included to facilitate wideband swept frequency applications. The AD9854's programmable 4× to 20× REFCLK multiplier circuit internally generates the 300 MHz system clock from an external low frequency reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source.

A direct 300 MHz clock is also available with single-ended or differential inputs. Supports enhanced spectral quality for single-needle regular fsk and ramp fsk. Using advanced 0.35µm CMOS technology, the AD9854 provides a high level of functionality on a single 3.3V supply.

The AD9854 is pin-to-pin compatible with the AD9852 monophonic synthesizer. Specified for operation over the extended industrial temperature range 8722 ; 40°C to +85°C.

Specification

V=3.3 V±5%, R=3.9 KΩ, external reference clock frequency=30 MHz, AD9854ASVZ REFCLK multiplier enabled at 10×, AD9854ASTZ external reference clock frequency=20 MHz, REFCLK multiplier at 10× enabled unless otherwise specified.

1. The reference clock input is configured to accept a 1 v pp (typical) DC offset square wave or sine wave centered at half the applied v or 3 v ttl level pulse input.

2. The internal 400 mV PP differential voltage swing is equal to 200 mV PP applied to both REFCLK input pins.

3. The I and Q gain unbalance can be digitally adjusted to less than 0.01 dB.

4. The pipeline delay is fixed for each individual block; however, if the first 8 msb of an adjustment word are 0, the delay will become longer. This is due to insufficient phase accumulation per system clock cycle to generate sufficient LSB amplitude to the DAC.

5. If features such as inverse SnC with 16 pipeline delays can be omitted, the overall delay is reduced by this amount.

6. The I/O UD CLK transfers data from the I/O port buffer to the programming register. This transfer is measured with the system clock.

7. Duty cycle changes from 1MHz to 100MHz, 1V PP sine wave input, 0.5V threshold.

8. Indicates the contribution of the inherent period of the comparator to the period jitter. The input signal is 1v, 40mhz square wave, and the measuring device is wave crest dts-2075.

9. The comparator input is derived from the analog output section through an external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V PP. The comparator output is connected to 50Ω.

10. Avoid overdriving digital inputs. (Refer to the equivalent circuit in Figure 3.)

11. Simultaneous operation of the device at a maximum ambient temperature of 85°C and a maximum internal clock frequency is not recommended if all device features are enabled. This configuration may result in a violation of the maximum die attach temperature of 150°C.

12. All functions are enabled.

13. All features are enabled except reverse sinc.

14. All functions except inverse sinc and digital multiplier.

15. Disabling the inverse sinc filter reduces power consumption by about 30% in most cases.

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal resistance

The heat sink of the AD9854ASVZ 80-lead TQFP package must be soldered to the PCB.

To determine the junction temperature on the application PCB, use the following formula:

Where: TJ is the junction temperature expressed in degrees Celsius. t is the case temperature in degrees Celsius, measured by the user at the top center of the package. Case Ψ=0.3°C/W. JT; Partial discharge is power dissipation (PD).

theory of operation

The AD9854 quadrature output digital synthesizer is a highly flexible device suitable for a wide range of applications. The device consists of an NCO with 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filter, digital multiplier, two 12-bit/300MHz DACs, a high-speed analog comparator, and interface logic. This highly integrated device can be configured as a synthetic LO, flexible clock generator or FSK/BPSK modulator.

Analog Devices, Inc. provides technical tutorials on the theory of operation of device function blocks. This tutorial includes a technical description of signal flow through DDS devices and provides basic application information for various digital synthesis implementations. This file is a tutorial on digital signal synthesis techniques, available from the DDS Technology Library on the Analog Devices DDS website/dds.

operating mode

The AD9854 has five programmable modes of operation. To select a mode, three bits in the control register (parallel address 1f hex) must be programmed.

Mono (Mode 000)

This is the default mode when the master reset pin is asserted. It can also be accessed if the user programs this mode into the control register. The phase accumulator responsible for generating the output frequency gets a 48-bit value from the Frequency Tuning Word 1 register which defaults to 0. The default values of the remaining applicable registers further define the monophonic output signal quality.

The default value after master reset configures the device with an output signal of 0 Hz zero phase. At power up and reset, the outputs of the i and q dacs are dc values equal to the midscale output current. This is the default mode amplitude setting of 0. See the On/Off Output Shaping Keying (OSK) section for more details on output amplitude control. All or some of the 28 program registers must be programmed to generate user-defined output signals.

Figure 35 shows the transition from the default condition (0Hz) to the user-defined output frequency (F1). As with all analog device DDS devices, the value of the frequency tuning word is given by: FTW=(expected output frequency × 2)/sysclkn

where: n is the phase accumulator resolution (48 bits in this case); the desired output frequency is expressed in Hertz; the FTW (frequency tuning word) is a decimal number.

Once the decimal number is calculated, it must be rounded to an integer and then converted to binary format, a sequence of 48 binary-weighted ones and zeros. The basic sine wave DAC output frequency range is from DC to half SyscLk.

The change in frequency is phase-continuous, which means that the first sampled phase value of the new frequency is referenced from the last sampled phase value of the previous frequency.

The I and Q DACs of the AD9854 are always 90° out of phase. The 14-bit phase register does not independently adjust the phase of each dac output. Instead, both DACs are equally affected by changes in phase offset.

Mono mode allows the user to control the following signal qualities: output frequency to 48-bit precision; output amplitude to 12-bit precision; user-defined fixed amplitude control; variable, programmable amplitude control; automatic, programmable, single-pin control on/off Off output shaping keying; output phase to 14-bit precision

These qualities can be changed or modulated via the 8-bit parallel programming port at 100 MHz parallel byte rate or 10 MHz serial rate. Incorporating this property allows FM, AM, PM, FSK, PSK, and ASK operations in monophonic mode.

Undamped FSK (Mode 001)

When undamped fsk mode is selected, the output frequency of dds is a function of the value loaded into frequency tuning word register 1 and frequency tuning word register 2 and the logic level of pin 29 (fsk/bpsk/hold). A logic low on pin 29 selects f1 (frequency tuning word 1, parallel address 4hex to parallel address 9hex), a logic high selects f2 (frequency adjustment word 2, parallel register address A hex to parallel register address F hex) system). The change in frequency is phase-continuous and internally aligned with the fsk data pin (pin 29); however, there is a deterministic pipeline delay between the fsk data signal and the DAC output.

The undamped fsk mode shown in Figure 36 represents a conventional fsk, radio teletype (rtty) or teletype (tty) transmission of digital data. fsk is a very reliable means of digital communication, but its bandwidth utilization of the radio frequency spectrum is very low. Tilting fsk, as shown in Figure 37, is a way to save bandwidth.

Tilt FSK (Mode 010)

This mode is a method of fsk where the change from f1 to f2 is not instantaneous, but is done in a frequency sweep or slope (the slope sign means the sweep is linear). Although linear frequency sweeping (or frequency ramping) is easy to automate, it is only one of many options. Other frequency conversion schemes can be implemented by varying the ramp rate and ramp step size in a segmented fashion.

A frequency ramp, whether linear or non-linear, needs to output many intermediate frequencies between f1 and f2 in addition to the primary frequencies f1 and f2. Figures 37 and 38 depict the frequency versus time characteristics of the linear ramp fsk signal.

Note that in oblique fsk mode, the delta frequency word (dfw) is required to be programmed to a positive two's complement value. Another requirement is to program the lowest frequency (f1) in the frequency tuning word 1 register.

The purpose of ramped fsks is to provide better bandwidth rejection than conventional fsks by replacing instantaneous frequency changes with more gradual, user-defined frequency changes. The dwell time at F1 and F2 can be equal to or much greater than the time spent at each intermediate frequency. The user controls the dwell time at f1 and f2, the number of intermediate frequencies, and the time spent on each frequency. Unlike undamped fsk, ramp fsk requires the lowest frequency to be loaded into the f1 register and the highest frequency to be loaded into the f2 register.

Several registers must be programmed to indicate the resolution of the DDS IF steps (48 bits) and the time each step takes (20 bits). Additionally, the CLR ACC1 bit (low-high-low) in the control register should be toggled prior to operation to ensure that the frequency accumulator starts with an all-zero output condition. For segmented nonlinear frequency translation, the registers must be reprogrammed during the frequency translation process to affect the desired response.

Parallel Register Address 1a (hex) to Parallel Register Address 1c (hex) include the 20-bit ramp rate clock registers. This is a countdown counter that outputs a pulse every time the count reaches 0. The counter activates when a logic level change occurs at the fsk input pin 29. This counter runs at the system clock rate, up to 300 MHz. The time period between each output pulse is as follows: (n+1) × system clock period

where n is the user-programmed 20-bit ramp rate clock value.

The allowable range for n is 1 to (2-1). The output of this counter clocks the 48-bit frequency accumulator shown in Figure 39. The ramp rate clock determines the amount of time spent at each intermediate frequency between f1 and f2. When the target frequency is reached, the counter stops automatically. The dwell time at f1 and f2 is determined by the duration that the fsk input pin 29 remains high or low after reaching the desired frequency. 20 parallel register address 10 hex to parallel register address 15 hex including 48-bit, two's complement, incremental frequency word registers. Whenever this 48-bit word receives a clock pulse from the ramp rate counter, it is accumulated (to the output of the accumulator). The output of this accumulator is added to or subtracted from the f1 or f2 frequency word, and then fed into the input of a 48-bit phase accumulator that forms the numerical phase step of the sine-cosine wave output. In this manner, the output frequency increments and decrements in frequency according to the logic state of pin 29 . This ramp rate is a function of the 20-bit ramp rate clock. When the destination frequency is reached, the ramp rate clock stops, stopping the frequency accumulation process.

In general, the value of the delta frequency word is much smaller compared to the value of the f1 or f2 tuning word. For example, if f1 and f2 are 1khz apart at 13mhz, the delta frequency word may only be 25hz.

Figure 41 shows that switching too early causes the gradient to immediately reverse itself and continue at the same rate and resolution until the original frequency is reached.

The control register contains a triangular bit at the parallel register address 1f hex. Setting this bit high in Mode 010 will cause automatic rise and fall between F1 and F2 without having to toggle pin 29, as shown in Figure 40. Once the triangle bit is set high, the logic state of pin 29 has no effect. This function uses the ramp rate clock time period and the step size of the incremental frequency word to form a continuous sweeping linear ramp from f1 to f2 and back to f1, with equal dwell times at each frequency. Use this feature to automatically scan between any two frequencies from DC to Nyquist.

In ramped fsk mode with the triangle bit set high, when the rising edge of the triangle bit occurs, the automatic frequency sweep starts at f1 or f2, depending on the logic level on pin 29 (the fsk input pin) (Figure 42). If the fsk data bits are high instead of low, select f2 instead of f1 as the starting frequency. Additional flexibility in ramping fsk mode is provided by the AD9854's ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramp from f1 to f2 and vice versa. To generate these nonlinear frequency changes, it is necessary to combine linear ramp segments of different slopes. This is accomplished by programming and performing a linear ramp at a rate or slope, and then changing the slope (by changing the ramp rate clock or the delta frequency word, or both). The ramp can be changed as frequently as needed to create the desired nonlinear frequency sweep response before reaching the destination frequency. These segment changes can be precisely timed using the 32-bit internal update clock (see the Internal and External Update Clocks section). The nonlinear ramp fsk has the appearance of a chirp function as shown in Figure 43. The difference between the ramp fsk function and the chirp function is that fsk is limited to operations between f1 and f2, while chirp operations do not have f2 to limit the frequency.

Two other control bits (clr acc1 and clr acc2) are available in oblique fsk mode, allowing more options. If clr acc1 (register address 1f hex) is set high, the 48-bit frequency accumulator (acc1) output is cleared and a retriggerable single pulse of one system clock duration is used. If the clr acc1 bit is held high, a pulse is sent on each rising edge of the update clock. The effect is to interrupt the current ramp, reset the frequency to the starting point (f1 or f2), and then continue rising (or falling) at the previous rate. This happens even if the static f1 or f2 destination frequency has been reached. Alternatively, the clr acc2 control bit (register address 1f hex) can be used to clear the frequency accumulator (acc1) and phase accumulator (acc2). When this bit is set high, the output of the phase accumulator will cause the DDS to output 0 Hz. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in an output of 0 Hz. To return to the last DDS operation, CLR ACC2 must be set to logic low.

Chirp (Mode 011)

This mode is also known as pulse frequency modulation. Most chirped systems use chirp sweep mode, but the AD9854 can also support nonlinear modes. In radar applications, using chirp or pulse frequency modulation, operators can greatly reduce the required output power to achieve the results that a single-frequency radar system would produce. Figure 43 shows a very low resolution nonlinear chirp showing the different slopes produced by varying the time step (ramp rate) and frequency step (increment).

The AD9854 allows accurate, internally generated linear or externally programmed nonlinear, pulsed or continuous frequency modulation over the entire frequency range, duration, frequency resolution, and sweep direction. All of these are user programmable. Figure 44 shows a block diagram of the fm chirp component.

FM chirp basic programming steps:

1. Program the starting frequency in frequency tuning word 1 (ftw1) from parallel register address 4hex to parallel register address 9hex.

2. Program the frequency step resolution to 48 bits, two's complement incremental frequency word (parallel register address 10 hex to parallel register address 15 hex).

3. Program the rate of change (time per frequency) to the 20-bit ramp rate clock (parallel register address 1a hex to parallel register address 1c hex).

When programming is complete, the I/O update pulse at pin 20 turns on the programming command. The necessity of the binary delta frequency word is to define the direction of movement of the FM chirp. If the 48-bit incremental frequency word is negative (msb is high), the incremental frequency change is in the negative direction of ftw1. If the 48-bit word is positive (msb is low), the incremental change in frequency is in the positive direction of ftw1. It is important to note that ftw1 is just the starting point of the fm chirp. There is no need to return the built-in constraints of FTW1. Once the FM chirp starts, it can move freely (under program control) within the Nyquist bandwidth (DC to half the system clock). However, an immediate return to FTW1 can be easily achieved.

In FM chirp mode there are two control bits (CLR ACC1 and CLR ACC2) that allow a return to the starting frequency FTW1 or 0 Hz. When the clr acc1 bit (register address 1f hex) is set high, the 48-bit frequency accumulator (acc1) output is cleared and has a retriggerable one-shot pulse of one system clock duration. The accumulator's 48-bit incremental frequency word input is not affected by the CLR ACC1 bit. If the clr acc1 bit is held high, a pulse is sent to the frequency accumulator (acc1) on every rising edge of the I/O update clock. The effect is to interrupt the current chirp, reset the frequency to the frequency programmed into ftw1, and continue chirping at the previously programmed rate and direction. The frequency accumulator output in clear chirp mode is shown in Figure 45. Shown in the figure is the I/O update clock, which can be user-supplied or internally generated.

Alternatively, the clr acc2 control bit (register address 1f hex) can be used to clear the frequency accumulator (acc1) and phase accumulator (acc2). When this bit is set high, the output of the phase accumulator will cause the DDS to output 0 Hz. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in an output of 0 Hz. To return to the last DDS operation, CLR ACC2 must be set to "logic low". This bit is useful in generating pulse frequency modulation.

Figure 46 illustrates the effect of the clr acc2 bit on the dds output frequency. Note that reprogramming the register while the CLR ACC2 bit is high allows loading the new FTW1 frequency and slope.

Another function only available in chirp mode is the hold pin (pin 29). This function stops sending the clock signal to the ramp rate counter and stops sending any further clock pulses to the frequency accumulator (acc1). The effect is to stop chirping at the frequency before the hold pin was pulled high. When pin 29 returns low, the clock and chirp resume. In the hold state, the user can change the programming registers; however, the ramp rate counter must resume operation at its previous rate until a count of 0 is obtained before loading a new ramp rate count. Figure 47 shows the effect of the hold function on the DDS output frequency.

A 32-bit automatic I/O update counter can be used to construct complex chirp or ramp FSK sequences. Since this internal counter is synchronized to the AD9854 system clock, program changes can be precisely timed. For this change, the user only needs to reprogram the required registers before automatic I/O update clock generation.

In chirp mode, the target frequency is not specified directly. If the user has no control over the chirp, the dds will automatically limit itself to the frequency range between dc and nyquist. Unless terminated by the user, the chirp continues until power is removed.

When the chirp destination frequency is reached, the user can choose any of the following actions:

(1) Use the hold pin or load all 0s into the increment frequency word register of the frequency accumulator (acc1), stop at the target frequency.

(2) Use the HOLD pin function to stop the chirp, then reduce the output amplitude by using the digital multiplier stage and output shaping keying pin (pin 30) or by using the program register control (address 21 to address 24 Hex).

(3) Use the CLR ACC2 bit to abruptly end the transfer.

(4) Continue the chirp by reversing the direction and returning to the previous or another destination frequency in a linear or user-directed fashion. If this involves reducing the frequency, the negative 48-bit incremental frequency word (msb set to 1) must be loaded into register 10 hex to register 15 hex. Any decrementing frequency step of the delta frequency word requires the msb to be set to logic high.

(5) Continue chirping, immediately return to the starting frequency (f1) in a sawtooth manner, and then repeat the previous chirping process using the clr acc1 control bit. Automatic, repeating chirps can be established by issuing CLR ACC1 commands at precise time intervals using a 32-bit update clock. Adjust the timing interval or change the incremental frequency word to change the chirp range. It is the user's responsibility to balance chirp duration and frequency resolution to obtain an appropriate frequency range.

BPSK (mode 100)

Binary, biphase, or bipolar phase shift keying is a quick way to select between two pre-programmed 14-bit output phase offsets that also affect the AD9854 pin 29, bpsk pin The logic state controls the selection of phase adjustment register 1 or phase adjustment register 2. When low, pin 29 selects phase adjustment register 1; when high, pin 29 selects phase adjustment register 2. Figure 48 shows the phase change of the output carrier for four cycles.

Basic bpsk programming steps

1. Program the carrier frequency to frequency tuning word 1.

2. Program the appropriate 14-bit phase word into Phase Adjust Register 1 and Phase Adjust Register 2.

3. Connect the bpsk data source to pin 29.

4. Activate the I/O update clock when ready.

Note that for higher-order PSK modulation, the user can use the serial or high-speed parallel programming bus to select the tone mode and program phase adjustment register 1.

Using the AD9854 to update the clock inside and outside

This update clock function consists of a bidirectional I/O pin (pin 20) and a programmable 32-bit down counter. To program changes to be transferred from the I/O buffer registers to the DDS active core, either a clock signal (low-to-high edge) must be provided externally to pin 20, or the clock signal must be generated internally by the 32-bit update clock.

When the user provides an external update clock, it is internally synchronized to the system clock to prevent partial transfers of program register information due to violations of data setup or hold times. This mode allows the user full control over when updated program information takes effect. The default mode of the update clock is internal (internal update clock control register bit is logic high). To switch to external update clock mode, the internal update clock control register bit must be set to logic low. The internal update mode generates automatic periodic update pulses at user-set intervals.

The internally generated update clock can be generated by programming the 32-bit update clock register (address 16 hex to address 19 hex) and setting the internal update clock control register bit (address 1F HEX) to logic high. The Update Clock Down Counter function operates at half the rate of the system clock (150 MHz maximum) and counts down from a 32-bit binary value (programmed by the user). When the count reaches 0, an automatic I/O update of the DDS output or function will be generated. The update clock is routed internally and externally to pin 20 to allow the user to synchronize the programming of update information with the update clock rate. The time between update pulses is given as: (n+1) (system clock cycle × 2)

where n is a user-programmed 32-bit value, and the allowable range for n is 1 to (2-1).

The internally generated update pulse output from pin 20 has a fixed high time of 8 system clock cycles.

Programming the update clock register to a value less than 5 will cause the I/O UD CLK pin to remain high. While the update clock can work in this state, it cannot be used to indicate when data is being transferred. This is the effect of the minimum high pulse time when I/O UD CLK is used as an output.

On/Off Output Shaping Keying (OSK)

The on/off OSK function allows the user to control the amplitude and time slope of the I and Q DAC output signals. This feature is used for burst transmission of digital data to reduce the adverse spectral effects of short and sudden bursts of data. The user must first enable the digital multiplier by setting the OSKEN bit (control register address 20 hex) to logic high in the control register. Otherwise, if the osk en bit is set low, the digital multiplier responsible for amplitude control is bypassed and the i and q dac outputs are set to full-scale amplitude.

In addition to setting the osk en bit, the second control bit osk int (also at address 20 hex) must be set to logic high. Logic high selects linear internal control of the output ramp up or ramp down function. A logic low in the osk int bit switches control of the digital multiplier to a user-programmable 12-bit register, allowing the user to dynamically change the amplitude conversion in almost any way. As shown in Table 8, these 12-bit registers (labeled Output Shape Key I and Output Shape Key Q) are located at address 21 hex to address 24 hex. The maximum output amplitude is a function of the R resistor and is not programmable when OSK INT is enabled.

The transition time from zero scale to full scale must also be programmed. The transition time is a function of two fixed elements and one variable. The variable element is a programmable 8-bit ramp rate counter. This is a down counter, clocked at the system clock rate (300 MHz max), and generates a pulse when the counter reaches 0. The pulse is routed to a 12-bit counter that increments with each pulse received. The output of the 12-bit counter is connected to a 12-bit digital multiplier. When the input value of the digital multiplier is 0, the input signal is multiplied by 0, resulting in zero scale. When the value of the multiplier is all 1s, the input signal is multiplied by the value 4095 or 4096, resulting in almost full scale. There are also 4094 remaining fractional multiplier values, which produce output amplitudes scaled according to the binary value.

The two fixed elements of the transition time are the period of the system clock (driving the ramp rate counter) and the amplitude order (4096). For example, if the AD9854's system clock is 100 MHz (10 ns period), and the ramp rate counter is programmed to count a minimum of 3, the conversion takes two system clock cycles (one rising edge loads the countdown value, and the other rising edge turns the counter from 3 is reduced to 2). If the countdown value is less than 3, the ramp rate counter will pause and thus generate a constant scaling value to the digital multiplier. This suspension condition may have application to the user. The time relationship between the 8-bit countdown value and the output pulse is as follows: (n+1)×system clock period, where n is the 8-bit countdown value. It takes 4096 pulses to advance a 12-bit up-counter from zero to full scale. Therefore, the minimum output waveform keying ramp time for a 100mhz system clock is 4096 × 4 × 10ns ≈ 164 μs

The maximum ramp time is: 4096 × 256 × 10 nanoseconds ≈ 10.5 milliseconds. Finally, changing the logic state of pin 30, when osk int is high, the output shaping keying automatically executes the programmed output envelope function. A logic high on pin 30 causes the output to rise linearly to full-scale amplitude and remain there until the logic level goes low, causing the output to drop to zero-scale.

I and Q DACs

The sine and cosine outputs of the dds drive the q and i DACs respectively (300 msps max). The maximum amplitude of these outputs is set by the DAC R resistor located at Pin 56. These are current output DACs with a maximum full-scale output of 20mA; however, the nominal 10mA output current provides the best spurious free dynamic range (SFDR) performance. The value of r is 39.93/i, where i is expressed in amperes. The DAC output compliance specification limits the maximum voltage developed at the output to -0.5 V to +1 V. Voltages generated beyond this limit can cause excessive distortion of the DAC and may cause permanent damage. The user must select an appropriate load impedance to limit output voltage fluctuations to compliance limits. For optimal sfdr, the two DAC outputs should terminate equally, especially at higher output frequencies where harmonic distortion errors are more prominent.

Both DACs are preceded by an inverse Sin(x)/x filter (also called an inverse SUNC filter) that pre-compensates the DAC output frequency as a function of frequency to achieve a flat amplitude response from DC to Nyquist. Both DACs can be controlled when not needed by setting the DAC PD bit high (HEX control at address 1D).

Control the digital-to-analog converter

The 12-bit Q DAC can be reconfigured to perform as a control or auxiliary DAC. Controlling the DAC output can provide DC control levels to external circuits, generate AC signals, or enable duty cycle control of on-board comparators. When the src q dac bit in the control register (parallel address 1f hex) is set high, the q dac input switches from an internal 12-bit q data source (default setting) to an external 12-bit with two's complement data supplied by the user. Data is transferred to the 12-bit Q DAC registers (Address 26 Hex and Address 27 Hex) via the serial or parallel interface at a maximum data rate of 100 MHz. This dac is clocked to the system clock, has a maximum of 300 msps, and has the same maximum output current capability as the i dac. A single R resistor on the AD9854 sets the full-scale output current of both DACs. When not needed, the control DAC can be powered down individually to save power by setting the Q DAC power-down high (address 1D HEX). The control dac outputs are designated as iout2 and iout2, pin 52 and pin 51, respectively.

Inverse sinc function

The inverse sinc function precompensates the input data to the output spectrum of the DACSDAC, which is inherently sine(x)/x roll-off. This makes it possible to output wideband signals (such as qpsk) from the DAC without significant amplitude changes as a function of frequency. The inverse sine function can be bypassed to significantly reduce power consumption, especially at higher clock speeds. The inverse sinc function does not apply to the q-path when the q-dac is configured to control the dac. The inverse sinc is on by default and is bypassed by making the bypass inverse sinc bit high in the control register 20 hex.

refclk multiplier

The refclk multiplier is a pll-based programmable reference clock multiplier that allows the user to select integer clock multiplication values in the range of 4× to 20×. With this feature, the user can input 15 MHz at the RIFCK input to generate an internal system clock of 300 MHz. Five bits in control register 1e hex set the multiplier value. The RIFCK multiplier function can be bypassed, allowing the AD9854 to clock directly from an external clock source. The system clock to the AD9854 is the output of the REFCLK multiplier (if it is turned on) or the REFCLK input. RIFCLK can be a single-ended or differential input, enabled by setting Pin 64, DIF-CLK, low or high, respectively.

PLL range bits

The pll range bits select the frequency range of the refclk multiplier pll. For operation from 200 MHz to 300 MHz (internal system clock rate), the PLL range bits should be set to logic 1. For operation below 200 MHz, the PLL range bits should be set to logic 0. The pll range bits adjust the pll loop parameters within each range for optimum phase noise performance.

Phase Locked Loop Filter

The pll filter pin (pin 61) provides the connection for the external zero compensation network of the pll loop filter. The zero compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μf capacitor. The other end of the net should be as close as possible to pin 60, AVDD. For best phase noise performance, the clock multiplier can be bypassed by setting the bypass PLL bit in the control register address 1E HEX.

Differential Reference Clock Enable

High enable on diff clk enable pin - Integrated clock inputs, REFCLK and REFCLK (pin 69 and pin 68 respectively). The minimum differential signal amplitude required at the REFCLK input pin is 400 mV pp. The center point or common mode range of differential signals can be between 1.6 V and 1.9 V. When pin 64 (diff clk enable) is clamped low, refclk (pin 69) is the only valid clock input. This is called single-ended mode. In this mode, pin 68 (REFCLK) should be fixed low or high.

high speed comparator

The comparators are optimized for high speed, featuring greater than 300 MHz switching rates, low jitter, sensitive inputs, and built-in hysteresis. It also has an output level of 1v pp minimum to 50Ω or cmos logic level to high impedance loads. The comparators can be powered down individually to save power. This comparator is used in clock generator applications to square the filtered sine wave produced by dds.

power down

Programming registers allow several individual stages to be powered down to reduce power consumption while maintaining the functionality of the desired stage. These stages are identified in Table 8 address 1d hex. Power down is achieved by setting specified bits to logic high. A logic low indicates that the stage is powered up. Additionally, or most importantly, significant power reduction can be achieved by programming the control register in address 20 HEX to bypass the inverse SUNC filter and digital multiplier stage. Again, a logic high causes the stage to be bypassed. Of particular importance is the inverse sinc filter; this stage consumes a lot of power. A complete power down occurs when all four PD bits are in control register 1d hex is set to logic high. This reduces power consumption by about 10 MW (3 mA).