Features: ±2 A, 50 V continuous output rating; low rds (on) output (270 mΩ, typical); programmable mixed, fast and slow current decay modes; serial interface control chip function; low power synchronous rectification ; Internal uvlo and thermal shutdown circuits; cross current protection.

describe

Designed for pulse width modulation (PWM) current control of DC motors, the A358 is capable of continuous output current of ±2 A and an operating voltage of 50 V. The internal fixed off-time PWM current control sequential circuit can be programmed through the serial interface to operate in slow, fast and mixed current decay modes.

Phase and enable input terminals are provided for controlling the speed and direction of a DC motor with an externally applied pwm control signal. The enable input can be programmed via the serial port as a fast or slow current decay PWM bridge. Internal synchronous rectification control circuitry is provided to reduce power consumption during PWM operation. Internal circuit protection includes hysteretic thermal shutdown and cross-current protection. No special power-up sequence is required.

The A3958 is available in two power packs, a 24-pin plastic dip with exposed thermal lugs (package suffix "B") and a 24-pin SOIC with internal fuse (package suffix "B") LB"). In both cases, the power pins are at ground potential and electrical isolation is not required. Each package type is lead free, 100% matte tin leadframe.

Selection Guide Box Part Numbers: A3958SB-T * 24-pin dip, 15 thermal lugs per tube; A3958SLBTR-T 24-pin SOICW, 1000 internal fuse pins per roll.

serial interface.

The A3958 is controlled by a 3-wire (clock, data, strobe) serial port. Programmable features allow maximum PWM configuration to motor drive requirements. Serial data is clocked from D19.

d0–d1 blank time. According to the table below, the current sense comparator is shielded when any output driver is on. fosc is the input frequency of the oscillator.

D2–D6 fixed off time. The fi ve bit word sets the fi xedoff time for the internal pwm current control. Break time is:

where n=0…31

For example, when the oscillator frequency is 4MHz, the off-time can be adjusted from 1.75µs to 63.75µs in 2µs increments.

d7–d10 fast decay time. A four-bit word sets the fast decay portion of the fixed off-time of the internal pwm control circuit. This only has an effect if the mixed decay mode is selected (via bit D17 and the mode input terminal). For tfd>toff, the device will operate effectively in fast decay mode. The fast decay part is:

where n=0…15

For example, when the oscillator frequency is 4MHz, the fast decay time can be adjusted from 1.75µs to 31.75µs in 2µs increments.

D11 synchronous rectification mode. Active mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. Passive mode allows current reversal, but will shut down the synchronous rectifier circuit if the load current reverses to the current limit set by VREF/RS.

D12 Synchronous rectification enabled.

D13 External PWM decay mode. Bit d13 determines the current decay mode when chopping is enabled with external pwm current control.

D14 enables logic. Bit D14, with ENABLE, determines whether the output driver is in the chopped (off) (ENABLE=D14) or on (ENABLE≠D14) state.

D15 Phase Logic. Bit d15 is combined with phase to determine whether the device is working in forward (phase≠d15) or reverse (phase=d15) state.

D16 GM range selection. Bit D16, and range, determines whether VREF is divided by 5 (range ≠ D16) or by 10 (range = D16).

D17 Internal PWM mode. Bit D17, AND mode, selects slow (mode = D17) or mixed (mode = D17) current decay.

D18 test mode. D19 sleep mode. Bit D18 low (default) operates the device in normal mode. D18 is for testing purposes only. Users should not change this bit. Bit d19 selects sleep mode to minimize power consumption when not in use. This disables most of the internal circuitry including the regulator and charge pump. On power-up, the serial port is initialized to all 0s. Bit D19 should be programmed high for 1 ms before attempting to enable any output drivers.

Serial port write timed operation. Data is recorded into the shift register on the rising edge of the clock signal. Normally, the strobe will remain high and will only be lowered when a write cycle is initiated. See the diagram below and these specifications for minimum timing requirements.

a. Data setting time…………15ns

b. Data retention time ...... 10 nanoseconds

c. Set the flash to the rising edge of the clock…………50ns

d. Clock high pulse width ...... 50 ns

e. Clock low pulse width ...... 50 ns

f. Set clock rising edge to strobe...50ns

g. Strobe pulse width...50 ns

This internally generated voltage is used to operate the receiver side DMOS output. The VREG terminal should be grounded separately from the 0.22µF capacitor.

Function Description:

Internally monitored, in the event of a fault, the device output is disabled. A charge pump is used to generate a gate supply voltage greater than vbb to drive the source dmos gate. A 0.22µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22µf ceramic capacitor should be connected to the charge pump.

CP and VBB act as reservoirs to operate high-end DMOS equipment. The CP voltage is internally monitored and in the event of a fault, the source output of the device is disabled.

downtime. If a fault occurs (junction temperature is too high, or voltage on CP or VREG is too low), the output of the device will be disabled until the fault condition is removed. At power-up, if VDD is low, the UVLO circuit disables the driver and resets the data in the serial port to all zeros.

PWM timer function. Pulse Width Modulation Timer

Programmable through the serial port (bits D2–D10) to provide an off-time PWM signal to the control circuit. In mixed current decay mode, the first part of the off time operates in fast decay until the fast decay time count (serial bits D7–D10) is reached, and then slowly decays for the remainder of the off time period (bits D2–D6). If the fast decay time is set longer than the off time, the device is effectively operating in fast decay mode. In conjunction with the mode, bit d17 selects mixed decay or slow decay. When the source driver is turned on, current spikes occur due to the reverse recovery current of the clamp diode and/or switching transients related to distributed capacitance in the load. To prevent this current spike from falsely resetting the source enable latch, the sense comparator is masked. The blanking timer runs after the off-time counter (see bits D2-D6) to provide programmable blanking. The blank timer is reset when the timer is chopped or the phase is changed. For external PWM control, a phase change or enable will trigger the blanking function. PWM blank timer.

Synchronous rectification. When a PWM off cycle is triggered by the ENABLE CHOP command or the internal fixed off time period, the load current is recycled according to the decay mode selected by the control logic. The A3958 synchronous rectification function will turn on the opposing pair of DMO outputs during current decay and effectively short the body diode using a low rds (on) driver. This will significantly reduce power dissipation and eliminate the need for external Schottky diodes.

Synchronous rectification can be disabled in active mode, passive mode, or via the serial port (bits D11 and D12).

In slow travel mode, active or passive mode selection has no effect. When synchronous rectification is enabled, slow decay mode can be used as an effective braking mode. The load current is regulated by an internal fixed off-time pwm control circuit. When the output of the DMOS H-bridge turns on, the current in the motor windings increases until a trip is reached as determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the range logic level, and serial data bit D16 value:

When Range=D16…………ITRIP=VREF/10RS

When range≠D16…………ITRIP=VREF/5RS

At the trigger point, the detection comparator resets the sourceenable latch, turning off the source driver. The load inductance then cycles the current through the serial port's programmed off time period. The current path during recirculation is determined by the slow/mixed current decay mode (d17) and the configuration of the synchronous rectification control bits (d11 and d12).

Application Information:

Current Sensing: To minimize inaccurate sensing of ITRIP current levels caused by ground tracking IR dips, the sense resistor should have a separate ground return to the device ground terminal. For low value sense resistors, the IR titer in the trace of the PCB sense resistor can be significant and should be taken into account. Sockets should be avoided as they may introduce changes in RS due to contact resistance.

Brake: The maximum value of rs is rs≤0.5/itrip. Braking is accomplished by driving the device in slow decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping via a combination of D14 and the enable input terminal. Since current can be driven in either direction through the DMOS driver, this configuration effectively shorts out the BEMF generated by the motor as long as chopper mode is enabled as long as it is asserted. It is important to note that the internal pwm current control circuit does not limit the current when braking because the current does not flow through the sense resistor. The maximum braking current can be approximated as VBEMF/RL.

Thermal Protection: Care should be taken to ensure that the maximum ratings of the device are not exceeded under worst-case braking conditions at high speeds and high inertia loads. Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.

Layout: Printed circuit boards should use heavy duty ground planes. For best electrical and thermal performance*, the driver should be soldered directly to the circuit board. The ground side of the RS should have a separate path to the equipment ground terminal. This path should be physically as short as possible and should not connect any other components. It is recommended to place a 0.1µf capacitor between the sensor and ground, as close as possible to the device; the load power supply terminal vbb should be separated from the electrolytic capacitor (recommended greater than 47µf) placed as close as possible to the device.