The W25Q128 FV ( 128M -bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. The flexibility and performance of the 25Q series far exceeds that of ordinary serial flash devices. They are great for code tracing to RAM, executing code directly from dual/quad spi (xip), and storing speech, text and data. The device operates on a 2.7V to 3.6V supply with current consumption as low as 4mA active and 1 microA off. All equipment is provided in a space saving package.
The W25Q128FV array is organized into 65536 programmable pages of 256 bytes each. Programmable up to 256 bytes at a time. Pages can be erased in groups of 16 (4KB sector erase), 128 groups (32 KB block erase), 256 groups (64KB block erase), or the entire chip (chip erase). w25q128fv has 4096 erasable sectors and 256 erasable blocks respectively. Small 4KB sectors allow for greater flexibility in applications requiring data and parameter storage.
W25Q128FV supports standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI and Quad Peripheral Interface (QPI) in 2 instruction cycles: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). Supports SPI clock frequencies up to 104MHz, allowing dual I/O equivalent clock frequencies of 208MHz (104MHz x 2) and quad I/O equivalent when using fast-read dual/quad I/O and QPI instructions The clock frequency is 416MHz (104MHz x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash. Continuous read mode allows efficient memory access, and the instruction overhead of reading a 24-bit address is only 8 clocks, allowing true xip (execute-in-place) operations.
A hold pin, write protect pin and programmable write protect, top or bottom array control, provide further control flexibility. Additionally, the device supports jedec standard manufacturer, device id and sfdp registers, a 64-bit unique serial number, and three 256-byte security registers.
Features New spiflash memory family – W25Q128FV: 128Mbit/16Mbyte – Standard spi: clk, /cs, di, do, /wp, /hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /HOLD
– Four SPIs: CLK, /CS, IO0, IO1, IO2, IO3
--qpi:clk,/cs,io0,io1,io2,io3
– Software and Hardware Reset Highest Performance Serial Flash – 104MHz Single, Dual/Quad SPI Clock – 208/416MHz Equivalent Dual/Quad SPI
– 50MB/s continuous data transfer rate – Over 100,000 erase/program cycles – Over 20 years of data retention Only 8 clocks to address memory – Quad Peripheral Interface (QPI) reduces instruction overhead – Allows true xip (execute in place) operation – Better than x16 parallel flash Low power, wide temperature range – Single 2.7 to 3.6V Power Supply – 4MA Active Current, <1µA Power Down (Typical)
-40°C to +85°C Operating Range Flexible Architecture with 4KB Sectors - Unified Sector/Block Erase (4K/32K/64K Bytes) - Program 1 to 256 Bytes/Programmable Pages - Erase/ Program Suspend and Resume Advanced Security Features – Software and Hardware Write Protection – Power Lock and OTP Protection – Top/Bottom, Supplemental Array Protection – Single Block/Sector Array Protection – 64-bit unique ID per device
– Found Parameter (SFDP) Register – 3x256 Byte Security Register with OTP Lock – Bit Space Efficient Packing of Volatile and Non-Volatile Status Registers – 8-pin SOIC/VSOP 208 mil
- 8-pin PDIP 300 mil – 8-pad wson 6x5 mm/8x6 mm
- 16-pin SOIC 300 mil (add/reset pin)
– 24-Ball TFBGA 8x6mm – Contact Winbond for KGD and other options Package Type and Pin Configuration Pin Configuration SOIC/VSOP 208 mil

Pin Description Chip Select (/cs)
The spi chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (do or io0, io1, io2, io3) pins are at high impedance. When deselected, device power consumption is in standby unless an internal erase, program, or write status register cycle is in progress. When CS is brought low, the device will be selected, power consumption will increase to the active level, and instructions can be written to and read from the device. After power up, /cs must transition from high to low in order to accept new commands. The /cs input must track the VCC supply level at power up and power down (see "Write Protection" and Figure 58). This can be accomplished using a pull-up resistor on the /CS pin if desired.
Serial data input, output and IOS (DI, DO and IO0, IO1, IO2, IO3)
The W25Q128FV supports standard SPI, dual SPI and quad SPI operation. Standard SPI instructions use a unidirectional DI (input) pin to serially write an instruction, address, or data to the device on the rising edge of the serial clock (CLK) input pin. Standard SPIs also use a unidirectional do (output) to read data or status from the device on the falling edge of clk.
Dual SPI and Quad SPI instructions use bidirectional IO pins to serially write commands, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set. When qe=1, the /wp pin becomes io2, and the /hold pin becomes io3.
Write Protect (/wp)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written to. Used in conjunction with the Status Register's Block Protection (CMP, SEC, TB, BP2, BP1, and BP0) and Status Register Protection (SRP) bits, portions as small as 4KB sectors or entire memory arrays can be hardware-protected. The /WP pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /wp pin function is not available because this pin is used for io 2. The pin configuration for quad I/O operation is shown in Figure 1A-C.
keep (/hold)
The /hold pin allows to hold the device while it is active. When /hold goes low, when /cs goes low, the do pin will be in high impedance and the signals on the di and clk pins will be ignored (don't care). When held high, device operation can resume. The /HOLD function may be useful when multiple devices share the same SPI signal. The /HOLD pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /hold pin function is not available since this pin is used for io3. The pin configuration for quad I/O operation is shown in Figure 1A-C.
Serial Clock (CLK)
The SPI serial clock input (CLK) pin provides the timing of serial input and output operations. (see SPI)
4.6 reset (/reset)
The /reset pin allows the controller to reset the device. For the 8-pin package, when QE=0, the IO3 pin can be configured as an A/STOP pin or an A/RESET pin, depending on the status register setting. When qe=1, the /hold or /reset functions do not work with 8-pin configurations. On the 16-pin SOIC package, a dedicated/reset pin is provided, which is independent of the QE bit setting.
block diagram

Function description
W25Q128FV Serial Flash Operation Diagram

Standard SPI Description
The W25Q128FV is accessed through an SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data In (DI), and Serial Data Out (DO). The standard SPI instruction uses the DI input pin to serially write an instruction, address, or data to the device on the rising edge of clk. The do output pin is used to read data or status from the device on the falling edge of clk.
SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. The main difference between Mode 0 and Mode 3 is the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the serial flash. For mode 0, the clk signal is typically low on the falling and rising edges of /cs. For Mode 3, the CLK signal is normally high on the falling and rising edges of /cs.
Dual SPI Instructions
The W25Q128FV supports dual SPI operation when using commands such as "Fast Read Dual Output (3BH)" and "Fast Read Dual I/O (BBH)". These instructions allow data to be transferred to and from the device at 2 to 3 times the rate of normal serial flash devices. Dual SPI read instructions are great for quickly downloading code to RAM (code shadowing) at power up or executing non-speed critical code directly from the SPI bus (XIP). When using the dual SPI instruction, the di and do pins become bidirectional I/O pins: io0 and io1.
Four SPI instructions
The W25Q128FV uses functions such as "Fast Read Quad Output (6BH)", "Fast Read Quad I/O (EBH)", "Word Read Quad I/O (E7H)" and "Octal Word Read Quad Channel I/O (E3H)” and other commands support four-channel SPI operation. These instructions allow data to be transferred to and from the device at 4 to 6 times the rate of normal serial flash. Quad-read instructions provide significant improvements in sequential and random access transfer rates, allowing fast code tracing directly to RAM or execution from the SPI bus (XIP). When using the quad spi instruction, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3, respectively. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set.
QPI description
The W25Q128FV supports Quad Peripheral Interface (QPI) operation only when switching the device from standard/dual/quad SPI mode to QPI mode using the "enter qpi(38h)" command. The typical spi protocol requires 8 serial clocks, and the byte-long instruction code can only be transferred to the device through the di-pin. The qpi mode utilizes all four io pins to input instruction code, so only two serial clocks are required. This can significantly reduce SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are unique. Only one mode can be active at any given time. The "enter qpi(38h)" and "exit qpi(ffh)" instructions are used to switch between these two modes. The default state of the device is standard/dual/quad SPI mode after power up or after a software reset using the "reset(99h)" command. To enable qpi mode, the nonvolatile four-bit enable bit (qe) in Status Register 2 needs to be set. When using the qpi instruction, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3, respectively. The operating mode of the device is shown in Figure 3.
Hold Function For standard SPI and dual SPI operation, the /hold signal allows w25q128fv operation to be suspended when activated (when /cs is low). The /hold function may be useful in situations where spi data and clock signals are shared with other devices. For example, consider whether the page buffer is only partially written when a priority interrupt requires use of the SPI bus. In this case, the /HOLD function can save the state of the instruction and the data in the buffer, so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and dual SPI operation, not quad SPI or QPI. The four-bit enable bit qe in Status Register 2 is used to determine whether the pin is used as/retained as a pin or as a data input/output pin. When qe=0 (factory default value), the pin is /hold; when qe=1, the pin becomes an I/O pin, and the /hold function is no longer available.
To initiate the A/HOLD condition, a device with /CS low must be selected. If the CLK signal is already low, the A/HOLD state will activate on the falling edge of the /HOLD signal. If CLK is not already low, the /hold condition will activate after the next falling edge of CLK. If the CLK signal is already low, the /HOLD condition will terminate on the rising edge of the /HOLD signal. If CLK is not low, the /hold condition will terminate after the next falling edge of CLK. In the A/HOLD state, the serial data output (do) is high impedance and the serial data input (di) and serial clock (clk) are ignored. The chip select (/cs) signal should remain active (low) for the entire duration of the /hold operation to avoid resetting the device's internal logic state.
Software reset and hardware/reset pins
The W25Q128FV can be reset to the initial power-on state through a software reset sequence, either in SPI mode or QPI mode. This sequence must contain two consecutive commands: enable reset (66h) and reset (99h). If the command sequence is successfully accepted, the device will take about 30us (trst) to reset. No commands are accepted during reset.
For WSON-8 and TFBGA package types, the W25Q128FV can also be configured to utilize the hardware/reset pin. The hold /rst bits in Status Register 3 are configuration bits for the /hold pin function or reset pin function. When HOLD/RST=0 (factory default value), the pin acts as the A/HOLD pin described above; when HOLD/RST=1, the pin acts as the A/RESET pin. Turn the /reset pin low for at least 1us (treset*) to reset the device to its initial power-on state. Any ongoing program/erase operations will be interrupted and data corruption may occur. When /reset is low, the device will not accept any command input.
If the qe bit is set to 1, the /hold or /reset functions will be disabled and the pin will become one of the four data I/O pins.
For the SOIC-16 package, the W25Q128FV provides a dedicated /reset pin in addition to the /hold (IO3) pin shown in Figure 1b. Driving the /reset pin low for at least 1us (treset*) resets the device to its initial power-on state. The HOLD/RST bit or the QE bit in the status register does not affect the function of this dedicated/reset pin.
The hardware/reset pin has the highest priority of all input signals. A low drive/reset for at least 1us (treset*) will interrupt any ongoing external/internal operations, regardless of the state of the other SPI signals (/cs, clk, ios, /wp and/or /hold).
NOTE: While faster/reset pulses (as short as a few hundred nanoseconds) will usually reset the device, at least 1us is recommended to ensure reliable operation.
Write-protecting applications using non-volatile memory must consider the possibility of noise and other adverse system conditions that could compromise data integrity. To solve this problem, the w25q128fv provides several ways to protect data from accidental writes.
Write protection feature Time delay write disable after device reset when VCC is below threshold A single block/sector lock for array protection Use of a power-down command Write-protected lock write-protection of status registers until next power-up Use of an array of status registers and one-time program (OTP) write protection of security registers*
*Note: This feature is available on special order. Please contact Winbond for details.
On power-up or power-down, the W25Q128FV will remain in reset when VCC is below the threshold of VWI (see Power-up Timing and Voltage Levels and Figure 43). When reset, all operations are disabled and no commands are recognized. All program and erase related instructions are further disabled due to the time delay of TPUW during power up and after VCC voltage exceeds VWI. This includes Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instructions. Note that the chip select pin (/cs) must track the VCC supply level at power up until the VCC minimum level and TVSL delay is reached, and must also track the VCC supply level at power down to prevent the opposite command sequence. If desired, a pull-up resistor/CS can be used to achieve this.
After power-up, the device is automatically in a write-disabled state with the Status Register Write Enable Latch (WEL) set to 0. Before accepting a Page Program, Sector Erase, Block Erase, Chip Erase, or Write Status Register command, the Allow Write command must be issued. The Write Enable Latch (WEL) is automatically cleared to a writable state of 0 upon completion of a program, erase or write instruction.
Software-controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protection (srp0, srp1) and Block Protection (cmp, sec, tb, bp[2:0]) bits. These settings allow part or the entire memory array to be configured as read-only. Used in conjunction with the Write Protect (/WP) pin, status register changes can be enabled or disabled under hardware control. See the Status Register section for more information. In addition, the power-down command provides an additional level of write protection because all commands except the release power-down command are ignored.
w25q128fv also provides another method of write protection using separate block locks. Each 64kb block (except for the top and bottom blocks, 510 blocks in total) and each 4kb sector within the top/bottom block (32 sectors in total) are equipped with individual block lock bits. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, the erase or program command issued to the corresponding sector or block will be ignored. When the device is powered up, all individual block lock bits will be 1, so the entire memory array is protected from erasing/programming. The "Single Block Unlock (39h)" instruction must be issued to unlock any particular sector or block.
The wps bit in Status Register 3 is used to decide which write protection scheme should be used. When wps=0 (factory default), the device will use only cmp, sec, tb, bp[2:0] bits to protect specific areas of the array; when wps=1, the device will use individual block locks for write protection .
Status and Configuration Registers
The W25Q128FV provides three status and configuration registers. The Read Status Register 1/2/3 commands can be used to provide status on the availability of the flash array, whether the device is written or disabled, write protection status, Quad SPI settings, security register lock status, erase/program suspend status , output driver strength, power-up and current address mode. Write Status Register instructions can be used to configure device write protection features, Quad SPI settings, security register OTP locks, hold/reset features, output driver strength and power-on address modes. Write access to the status register is controlled by the state of the nonvolatile status register protection bits (srp0, srp1), the write enable instruction, and the /WP pin during standard/dual SPI operation.

Erase/Writing (Busy) – Only Status Busy is a read-only bit in the Status Register (S0) when the device is performing Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write This bit is set to a 1 state during the Status Register or Erase/Program Security Register instructions. During this time, the device will ignore instructions other than Read Status Register and Erase/Program Suspend instructions (see tw, tpp, tse, tbe, and tce in AC Characteristics). When a program, erase or write status/secure register instruction completes, the busy bit will be cleared to the 0 state, indicating that the device is ready for further instructions. Write Enable Latch (WEL) - Status Only The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that is set to 1 after a Write Enable instruction is executed. When the device write is disabled, the WEL status bit is cleared to 0. The write disable state occurs at power-up or after any of the following commands: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register, and Program Security Register. Block Protection Bits (bp2, bp1, bp0) - Volatile/Non-volatile Writable Block Protection Bits (bp2, bp1, bp0) are in the status registers (s4, s3, and s2) that provide write protection control and status Nonvolatile read/write bits. The block protection bits can be set using the Write Status Register instruction (see TW in AC Characteristics). All, none or part of the memory array can be protected from program and erase instructions (see Status Register Memory Protection Table). The factory default setting of the block protection bit is 0, there is no protected array.

Upper/lower block protection (tb) volatile/non-volatile writable non-volatile upper/lower bit (tb) controls whether the block protection bits (bp2, bp1, bp0) are from the top of the array (tb=0) or The bottom (tb=1) is protected as shown in the Status Register Memory Protection table. The factory default setting is tb=0. Depending on the state of the SRP0, SRP1, and WEL bits, the TB bit can be set to a write status register instruction. Sector/Block Protection Bits (seconds) Volatile/Non-Volatile Writable Non-Volatile Sector/Block Protection Bits (seconds) Control Block Protection Bits (bp2, bp1, bp0) Protect Array Top (tb=0 ) or a 4kb sector (sec=1) or a 64kb block (sec=0) at the bottom (tb=1), as shown in the Status Register Memory Protection table. The default setting is sec=0. Complement Protection (CMP) is a non-volatile read/write bit in the Status Register (S14). It is used in combination with the sec, tb, bp2, bp1 and bp0 bits to provide greater flexibility for array protection. Once CMP is set to 1, the array protection previously set by SEC, TB, BP2, BP1 and BP0 will be reversed. For example, when CMP=0, the top 64KB block can be protected while the rest of the array is unprotected; when CMP=1, the top 64KB block will become unprotected and the rest of the array read-only. See the Status Register Memory Protection table for details. The default setting is cmp=0. 7.1.7 Status Register Protection (SRP1, SRP0) are non-volatile read/write bits in the Status Registers (S8 and SRP0). The srp bit controls the method of write protection: software protection, hardware protection, power lock, or one-time programmable (otp) protection.

Erase/Program Suspend Status (SUS) – Only the Status Suspend Status bit is a read-only bit in the Status Register (S15) that is set to 1 after the Erase/Program Suspend (75h) instruction is executed. The SUS status bit is cleared to 0 by the Erase/Program Resume (7AH) instruction and power down and power cycle.
Security Register Lock Bits (LB3, LB2, LB1) - Writable Volatile/Non-Volatile OTP Security Register Lock Bits (LB3, LB2, LB1) are non-volatile The one-time program (OTP) bit provides write protection control and status for the security registers. The default state of lb3-1 is 0 and the security registers are unlocked. LB3-1 can be individually set to 1 using the Write Status Register instruction. LB3-1 is one-time programmable (OTP), once set to 1, the corresponding 256-byte security register will permanently become read-only. 7.1.10 Quad Enable (Qe) - Volatile/Non-Volatile Writable The Quad Enable (QE) bit is a non-volatile read/write bit in the Status Register (S9) that enables Quad SPI and QPI operations. When the qe bit is set to the 0 state (factory default), the /wp pin and /hold are enabled. When the qe bit is set to 1, the four io2 and io3 pins are enabled and the /wp and /hold functions are disabled.
Before issuing "enter qpi(38h)" to switch the device from standard /dual/quad spi to qpi, the qe bit must be set to 1, otherwise the command will be ignored. When the device is in qpi mode, the qe bit will remain 1. The "Write Status Register" command in QPI mode cannot change the QE bit from "1" to "0".
Warning: The QE bit should not be set to 1 if the /wp or /hold pins are connected directly to power or ground during standard spi or dual spi operation.

Write Protection Select (WPS) - The volatile/non-volatile writable WPS bit is used to select which write protection scheme should be used. When wps=0, the device will use a combination of cmp, sec, tb, bp[2:0] bits to protect specific regions of the memory array. When wps=1, the device will use a single block lock to protect any single sector or block. The default value of all individual block lock bits is 1 after device power-up or reset.
Output Driver Strength (DRv1, DRv0) - The volatile/nonvolatile writable DRv1 and DRv0 bits are used to determine the output driver strength for read operations.

/hold or /reset pin function (hold/reset) – volatile/non-volatile writable hold/reset bit is used to determine if /hold or / should be implemented on hardware pins of the 8-pin package Reset the function. When HOLD/RST=0 (factory default value), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET. However, the /hold or /reset functions are only available when qe=0. If qe is set to 1, the /hold and /reset functions will be disabled and the pin will act as a dedicated data I/O pin.
Reserved Bits - Not Function - There are some reserved status register bits that can be read as "0" or "1". It is recommended to ignore the value of these bits. In the "Write Status Register" instruction, reserved bits can be written as "0", but have no effect.

Instructions The standard/dual/quad SPI instruction set of the W25Q128FV consists of 45 basic instructions, which are fully controlled through the SPI bus (see Instruction Set Table 1-2). Use the falling edge of chip select (/cs) to start the instruction. The first byte of data coming into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of the clock, most significant bit (msb) first.
The QPI instruction set of the W25Q128FV consists of 32 basic instructions, which are fully controlled through the SPI bus, using the falling edge (/cs) of the chip select to initiate the instruction. The instruction code is provided by the first byte of data clocked through the IO[3:0] pins. Data on all four IO pins is sampled on the rising edge of the clock, most significant bit (msb) first. All QPI instructions, address, data, and dummy bytes use all four IO pins to transfer each byte of data every two serial clocks (clk).
Instructions vary in length from one byte to several bytes, possibly followed by address bytes, data bytes, dummy bytes (don't care), and in some cases a combination. The description is done using the rising edge of EDGE/CS. Clock-dependent timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clock bit. However, all write, program, or erase instructions must complete on byte boundaries (/cs driven high after a full 8-bit clock), otherwise the instructions will be ignored. This feature further protects the device from accidental writes. In addition, when memory is being programmed or erased, or when the status register is written, all instructions except read status register are ignored until the program or erase cycle is complete.