The ADS7817 is a 12-bit, 200kHz sampling analog-to-digital converter with high impedance fully differential analog inputs. The reference voltage can vary from 100mV to 2.5V, with a corresponding input resolution of 49µV to 1.22mV.

Differential inputs, low power consumption, automatic power down, and small size make the ADS7817 ideal for direct connection to sensors in battery-powered systems, remote data acquisition, or multi-channel applications. The ADS7817 is available in plastic mini DIP-8, SO-8 or MSOP-8 packages.

theory of operation

The ADS7817 is a typical successive approximation register (SAR) analog-to-digital converter. The architecture is based on capacitive redistribution, which essentially includes sample/hold functionality. The converter is fabricated using a 0.6μcmos process. This architecture and process allows the ADS7817 to acquire and convert analog signals at up to 200,000 conversions per second while consuming very little power.

The ADS7817 requires an external reference, an external clock, and a +5V supply. The external reference voltage can be any voltage between 100mv and 2.5v. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the slew rate of the ADS7817.

The external clock can vary between 10kHz (625Hz throughput) and 3.2mHz (200kHz throughput). The duty cycle of the clock is basically unimportant, as long as the minimum high and low times are at least 150ns. The minimum clock frequency is set by leakage on the capacitors inside the ADS7817.

Analog input is provided to two input pins: +in and –in. When a conversion begins, the differential inputs on these pins are sampled on an internal capacitor array. During the conversion process, both inputs are disconnected from any inner functions.

The converted digital result is clocked by the dclock input and provided serially (most significant bit first) on the dout pin. The digital data provided on the dout pin is used for the conversion currently in progress, with no pipeline delay. After the conversion is complete, you can continue to clock the ads7817 and get the least significant bit of the serial data first.

analog input

The analog inputs are bipolar and fully differential. There are two general methods of driving the analog inputs of the ADS7817: single-ended or differential (see Figure 1). When the input is single-ended, the –in input is held at a fixed voltage. The + at the input swings around the same voltage with a peak-to-peak amplitude of 2 8226 ; vref. The value of VREF determines the range within which the common voltage may vary (see Figure 2).

When the input is differential, the amplitude of the input is the difference between the +in and –in inputs or +in-(–in). A voltage or signal is common to both inputs. The peak amplitude of each input is the Vref of this common voltage. However, since the inputs are 180° out of phase, the peak-to-peak amplitude of the differential voltage is 2•vref. The value of VREF also determines the voltage range that the two inputs may share (see Figure 3).

In each case, care should be taken to ensure that the output impedances of the sources driving the +input and -input are matched. If this is not observed, the two inputs may have different settling times. This can lead to offset errors, gain errors, and linearity errors that vary with temperature and input voltage. If the impedances cannot be matched, the error can be reduced by giving the ADS7817 more acquisition time.

The input current on the analog input depends on many factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS7817 charges the internal capacitor array during sampling. After the capacitor is fully charged, there is no more input current. The analog input voltage source must be able to charge the input capacitor (15pF) to 12-bit regulation within 1.5 clock cycles. When the converter enters holdover mode or is in power-down mode, the input impedance is greater than 1gΩ.

Attention must be paid to the absolute analog input voltage. The + input should always be within the range of GND – 300mV to VCC+300mV. The input should always stay within the range of GND – 300 to 4 volts. Outside these ranges, the linearity of the converter may not be within specification.

reference input

The external reference sets the analog input range. The ADS7817 will operate over a reference voltage range of 100 volts to 2.5 volts. This has several important implications.

As the reference voltage decreases, the analog voltage weight of each digital output code decreases. This is often referred to as the lsb (least significant bit) size and is equal to twice the reference voltage divided by 4096 . This means that any offset or gain error inherent in the A/D converter will increase in the magnitude of lsb as the reference voltage decreases. Typical "offset change versus reference voltage" and "gain change versus reference voltage" performance curves provide more information.

As the size of the LSB decreases, the noise inherent to the converter also increases. With a reference voltage of 2.5V, the converter's internal noise typically produces only a 0.52LSB peak-to-peak potential error on the output code. When the external reference voltage is 100mv, the potential error contribution of the internal noise will be 25 times the -13lsb. Errors caused by internal noise are Gaussian in nature and can be reduced by averaging successive conversion results.

For more information on noise, refer to the typical performance curves "Effective Bits vs. Voltage Reference" and "Peak-to-Peak Noise vs. Voltage Reference". Note that the effective number of bits (ENOB) numbers are calculated from the converter's signal (noise + distortion) and a 1kHz, 0dB input signal. The relationship between sinad and enob is as follows: sinad=6.02•enob+1.76.

In the case of low reference voltages, special care should be taken to provide a clean layout, including adequate bypassing, clean power supplies, low noise references, and low noise input signals. Due to the smaller size of the LSB, the converter will also be more sensitive to external error sources such as nearby digital signals and electromagnetic interference.

The current the external reference must supply will depend on the result of the conversion. Current is lowest at negative full scale (800h), typically 15µA at 200kHz slew rate (25°C). Under the same conditions, the current will increase as the analog input approaches positive full scale, reaching 25µA at an output result of 7ffh. The current doesn't increase linearly, but depends somewhat on the bit pattern of the digital output.

The reference current decreases with increasing slew rate and reference voltage. Since the current from the reference is drawn on every bit decision, clocking the converter faster during a given conversion does not reduce the overall current consumption from the reference. The reference current varies little with temperature. For more information, see the curves "Reference Current vs. Sample Rate" and "Reference Current vs. Temperature" in the Typical Performance Curves section.

digital interface

serial interface

The ADS7817 communicates with microprocessors and other digital systems through a synchronous 3-wire serial interface, as shown in Figure 4 and Table 1. The dclock signal synchronizes the data transfer with each bit transferred on the falling edge of the dclock. Most receiving systems will capture the bit stream on the rising edge of dclock. However, if the minimum hold time for dout is acceptable, the system can use the falling edge of dclock to capture each bit.

The falling cs signal initiates conversion and data transfer. The first 1.5 to 2.0 clock cycles of the conversion cycle are used to sample the input signal. After the second falling dclock edge, dout is enabled and outputs a low value for one clock cycle. In the next 12 dclock cycles, dout will output the conversion result (most significant bit) first. After the least significant bit (b0) is output, subsequent clocks will repeat the output of the data, but in the least significant bit first format.

After the most significant bit (b11) has been repeated, dout will be tri-stated. Subsequent clocks to the converter. A new conversion will only be started when cs is set high and returned low.

Data Format

The output data of the ADS7817 is in binary 2's complement format. This table represents the ideal output code for a given input voltage, excluding the effects of offset, gain error, or noise.

Power consumption

The converter's structure, semiconductor fabrication process, and careful design allow the ADS7817 to convert at rates up to 200kHz while requiring very little power. There are a few things to keep in mind when it comes to the absolute lowest power consumption, though.

The power dissipation of the ADS7817 is proportional to the slew rate. The first step in achieving the lowest power consumption is to find the lowest slew rate that meets the system requirements. In addition, the ADS7817 is in power-down mode under two conditions: when the conversion is complete and when Cs is high (see Figure 1). Ideally, each conversion should happen as fast as possible, preferably at a clock frequency of 3.2 MHz. In this way, the converter may spend the longest time in power-down mode. This is very important because the converter not only uses power on each dclock transition (typical for digital cmos components), but also uses some current for analog circuits such as comparators. The analog section continues to dissipate power until it enters power-down mode.

Figure 6 shows the current consumption of the ADS7817 as a function of sampling rate. For this graph, the converter is timed. At 3.2mhz, cs is high for the rest of the sampling period, regardless of the sampling rate. Figure 7 also shows the current consumption versus sampling rate. However, in this case, the dclock period is 1/16 of the sampling period, and cs is higher for every 16 dclock periods.

There is an important difference between the power-down mode entered after a transition is complete and the full power-down mode enabled when CS is high. When both the analog part and the digital part are powered off, it is only powered off when CS is high. So if cs is held low at the end of the conversion and the converter keeps clocking, the power consumption will not be as low as when cs is high. See Figure 8 for more information.

By lowering the reference voltage, the ADS7817 requires less current to fully charge the internal capacitors of the analog input and reference input. The reduction in power consumption should be carefully weighed against the increase in noise, offset, and gain error outlined in the reference section.

short cycle

Another way to save power is to use the cs signal to shorten the conversion period. Since the ADS7817 puts the latest data bit on the output line as it is being generated, the converter is prone to short cycle operation. This term means that the conversion can be terminated at any time. For example, if only 8 bits of the conversion result are needed, the conversion can be terminated (by pulling cs high) after the 8th bit is clocked.

This technique can be used to reduce power consumption in these applications until the analog signal is monitored to see a condition become true. For example, if the signal is outside a predetermined range, the full 12-bit conversion result may not be required. If so, the conversion can be terminated after the first n bits, where n can be as low as 3 or 4. This reduces power consumption in the converter and other parts of the system because they spend more time in power-down mode.

layout

For best performance, attention should be paid to the physical layout of the ADS7817 circuit. This is especially true if the reference voltage is low and/or the slew rate is high. At 200khz conversion rate, ads7817 makes a bit decision every 312ns. That is, for each subsequent bit decision, the digital output must be updated with the result of the last bit decision, the capacitor array is appropriately switched and charged, and the input of the comparator is set to a 12-bit level within one clock cycle.

The basic SAR structure is very sensitive to spikes on the power, reference, and ground connections that occur before locking onto the comparator output. Therefore, in any conversion process of the N-bit synthetic aperture radar converter, there are N "windows", in which a large external transient voltage easily affects the conversion result. These spikes can originate from switching power supplies, digital logic, and high-power devices, to name a few. If the fault is nearly in sync with the converter's dclock signal, it can be difficult to track down this particular source of error due to occasional misoperation due to the phase difference between the two changing over time and temperature.

With this in mind, the supply to the ADS7817 should be clean and well bypassed. The 0.1µf ceramic bypass capacitor should be placed as close as possible to the ADS7817 package. Additionally, 1 to 10µf capacitors and 10Ω series resistors can be used to low pass filter noise power supplies.

Again, the reference should be bypassed with a 0.1µf capacitor. Again, series resistors and bulk capacitors can be used as the reference voltage for the low pass filter. If the reference voltage is sourced from an op amp, be aware that the op amp can drive the bypass capacitor without oscillation (a series resistor can help in this case). Keep in mind that while the ADS7817 draws very little current from the reference circuit on average, it places higher instantaneous current requirements on the external reference circuit.

Also, keep in mind that the ADS7817 does not provide inherent rejection of noise or voltage variations associated with the reference input. This is especially important when the reference voltage comes from a power supply. Any noise and ripple from the power supply, if not rejected by the external reference circuit, will appear directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variations due to line frequency (50 Hz or 60 Hz) can be difficult to remove.

The ground pins on the ADS7817 should be placed at clean ground points. In many cases this will be the "analog" ground. Avoid connecting the ground pin too close to the microprocessor, microcontroller, or digital signal processor ground. If required, ground trace directly from the converter to the power connection point. The ideal layout would include analog ground planes for the converter and associated analog circuitry.

Application circuit

Figures 9, 10, and 11 show some typical application circuits for the ADS7817. Figure 9 shows a low-cost, low-power circuit for basic data acquisition. The total power dissipation of the ADS7817 and the reference circuit is less than 5mW over temperature, power supply variation, and 200kHz sampling rate.

Figure 10 is a motor control application that uses three iso130s to isolate the motor from the sensing system (three ads7817s and one dsp56004). The iso130 offers 10kv/μs (min) isolated mode rejection, 85khz large signal bandwidth and a fixed gain of 8. The reference voltage for the ADS7817 is 1.2V, derived from the REF1004-1.2. This gives the converter a full-scale input range of ±1.2v. Since the iso130 has a gain of 8, the current sense resistor should provide a volute output voltage of less than ±150mV.

Figure 11 is a similar application that isolates the three ADS7817 digital outputs from the motor rather than analog signals. Here, the reference voltage of the ADS7817 is 150mV, and the analog input of each ADS7817 is directly connected to the current sense resistor. By removing the iso130 from the signal path, a greater signal-to-noise ratio is achieved in the sensing system. However, 9 opto-isolators are required to isolate the a/d converter.