benefit

Ultra-compact 6x6mm pqfn, saving 72% space compared to traditional discrete solutions Fully optimized system efficiency Clean switching waveforms with minimal ringing High current handling

feature

Over 93% Peak Efficiency High Current Handling: 50A High Performance PQFN Copper Clip Package Tri-State 5V PWM Input Driver Skip Mode SMOD (Low Side Gate Off) Input Over Temperature Warning Flag Condition Drive Output Disable Function (Release Pin) Internally Pull and pull down to prevent smoke respectively cancel the input Fairchild Power technology mosfet clean voltage waveform and reduce ringing Fairchild synchronous FET (integrated Schottky diode) low side MOSFET technology integrated bootstrap Schottky diode adaptive emitter Gate Drive Timing Protection Under Voltage Lockout (UVLO) Optimized Switching Frequency Up to 1MHz Thin SMD Package Fairchild Green Packaging and RoHS Compliance Based on Intel 4.0 DRMOS Standard

describe

The XS 8482 ; DRMOS series is Fairchild's next generation, fully optimized, ultra-compact, integrated mosfet plus driver power stage solution for high current, high frequency, synchronous step-down DC-DC applications. The FDMF6823C integrates a driver chip, dual power mosfet and bootstrap Schottky diode thermally enhanced in an ultra-compact 6x6mm package. Through an integrated approach the power stage is based on driver and MOSFET dynamic performance, system inductance, and power MOSFET rds (on). The XS™ DRMOS uses Fairchild's high-performance PowerTrench™ MOSFET technology, which greatly reduces switch ringing and eliminates the need for snubber circuits in most buck converter applications. A driver chip delay that reduces dead time and propagation further improves performance. A hot warning function warns of potential overtemperature conditions. The FDMF6823C also includes a skip mode (SMOD) to improve light load efficiency. The FDMF6823C is also compatible with a wide range of pwm controllers.

application

High-performance gaming motherboards, compact blade servers, V-core and non-V-core DC-DC converters

Function description

The FDMF6823C is an optimized driver plus FET module for synchronous buck converter topology. All that is required for a single correct drive is a PWM input signal high-side and low-side mosfet. Each section is capable of traveling at speeds up to 1 MHz. vcin and disable (disable) the vcin pin is monitored by the under-voltage lockout (uvlo) circuit. The driver is enabled when vcin is above ~3.1v. When vcin is below ~2.7v, the driver is disabled (gh, gl=0). The driver can also hold the GL and GH input states low by pulling the DISB pin low (DISB regardless of PWM. A thermal warning flag (THWN) can be provided by the FDMF6823C by raising the DISB pin voltage high (DISB). thwn) warns of an over-temperature condition. This thermal warning flag uses an open-drain output that activates when the temperature ( 150 °C) is pulled to cgnd reached. Once the temperature drops to the reset position, the THWN output returns to a high-impedance state at temperature (135°C) When used, the thwn output requires a pull-up resistor and can be connected to VCINTHWN without disabling the DRMOS block.

Tri-state pwm input The FDMF6823C contains a tri-state 5V PWM input gate drive design. Tri-state gate driver logic high and low, and tri-state close window. When the PWM input signal enters and remains within the tri-state window for a specified wait time (td_hold-off), gl and gh are pulled low. This enables the gate driver to turn off the high-side and low-side MOSFETs down support such as phase shedding, which is the case in polyphase voltage regulators. Exiting a Tri-State Condition When exiting a valid tri-state condition, the FDMF6823C follows the PWM input command. If the PWM input goes low from three states, the low-side mosfet is turned on. If the PWM input comes from tri-state to high, the high-side mosfet is turned on in the FDMF6823C design to allow short propagation delays on exit from the tri-state window (see Electrical Characteristics). Low-Side Driver The low-side driver (GL) is designed to drive a ground referenced, low RDS(on), n-channel MOSFET. Bias because GL is at the VDRV and CGND pins. When the driver is enabled, the output is 180° out of phase with the pwm input. when? The driver is disabled (DISB=0V) and GL remains low. High-side driver The high-side driver (GH) is designed to drive floating n-channel MOSFETs. The bias driver for the high side is developed by a bootstrap power supply circuit consisting of an internal Schottky diode and an external Schottky diode to form a bootstrap capacitor (CBoot). During boot, keeping VSWH at pgnd allows cboot to pass through the internal diode. When the PWM input goes high, GH starts charging the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from the cboot and sent to the first quarter gate. When Q1 is on, vswh rises to Vin, forcing the boot pin to Vin+Vboot, which provides enough VGS boost for Q1. Complete switching cycle q1 by pulling gh to VSWH when VSWH falls to PGND. The gh output is in phase with the pwm input. This wait time, td_-hold-off, when the driver is disabled or the PWM signal is held for more than three states. DC-DC Converter Workstation High Current DC-DC Point Load Converter Network and Telecom Microprocessor Voltage Regulator Small Voltage Regulator Module Adaptive Gate Drive Circuit The advanced design of the driver chip ensures minimal mosfet dead time while eliminating potential penetration (cross-conduction) current. It senses states and adaptively adjusts the gate drives to ensure they don't happen at the same time. Provides associated timing waveforms. To prevent overlap during low-to-high transitions (Q2 off to Q1 on), the adaptive circuit monitors the voltage at the GL pin. High when the PWM signal disappears, Q2 starts to turn off after the propagation delay (tpd_phgll). Once the GL pin discharges below 1.0V, q1 starts to turn on after the adaptive delay td_deadon. To prevent overlap during high-low transitions (Q1 off to Q2 on), the adaptive circuit monitors the GH to phase pin pair voltage. When the PWM signal goes low, Q1 has a propagation delay (tpd_plghl). Once the voltage passes GH to phase below 2.2V, Q2 starts to turn on after the adaptive delay td_dead time.

Supply Capacitor Selection For the supply input (vcin), a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1µf x7r or x5r capacitors. Place this capacitor near the vcin pin to connect to the GND plane with vias. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (cboot), a bootstrap capacitor of 100nF X7R or X5R capacitors are usually sufficient. An application that may require a series bootstrap resistor to improve switching noise immunity. This when operating above may require a start-up resistor of 15vin to effectively control the high side mosfet switching slew rate and vshw overshoot. Startup values from 0.5 to 3.0Ω typically reduce VSWH overshoot. VCIN filter VDRV pin for high side and low side power mosfet. In most cases it can be connected directly to vcin to provide power to the logic part of the driver. For additional noise immunity, an RC filter can be inserted between the vdrv and vcin pins. Recommended values should be 10Ω and 1µF. Power Loss and Efficiency Measurement and Calculation Power Loss Test Method Power Loss is calculated as follows: pin = (VIN x IIN) + (V5V x I5V) (W) (1) psw = vsw x iout(w) (2) pout =vout x iout(width)(3) ploss-u module=pins-psw(w)(4) ploss-u board=pin pout(width)(5)effmodule=100 x psw/pin(6)effboard= 100 x pout/pin %

Printed circuit board layout guidelines for the FDMF6823C and the layout of key components. All high current paths like vin, vswh, vout, copper to ground, should be short and wide inductors and resistors. This helps to achieve a more stable and evenly distributed current with enhanced thermal radiation and system performance. PCB Designer's Recommendations 1. Input ceramic bypass capacitors must be placed close to the vin and pgnd pins. This helps reduce the current ripple caused by high current power loop inductance and input power MOSFET switching operations. 2.vswh copper track has two uses. In addition to the high frequency current path from the drmos package to the output inductor the drmos package acts as a heat sink for the low side mosfet. The traces should be short and wide enough to present a low impedance path across the drmos and inductance. Short, wide traces minimize electrical losses and drmos temperature rise. Note that the vswh node is a high voltage high frequency switching node noise potential. Care should be taken to minimize coupling into adjacent traces. Because this copper trace acts as a heat sink for the lower mosfet, the balance is to utilize maximum area to improve drmos cooling while maintaining acceptable noise emissions. 3. The output inductor is close to the FDMF6823C to connect the VSWH copper traces. It should also be noted that inductive dissipation does not heat the drmos. 4. The PowerTrench® mosfet used in the output can effectively reduce due to fast switching. In most cases, no VSWH buffer is required. If using a shock absorber, place the shock absorber close to the VSWH and PGND pins. The selected resistors and capacitors must be sized for the power dissipation. 5. vcin, vdrv and boot capacitors should be placed as close as possible to vcin and cgnd, vdrv to cgnd, boot to phase pin pair to ensure clean and stable power supply. Trace width and length should also be considered. 6. Include trace from phase pin to vswh pin to improve noise margin. Keep this trace where possible. 7. The layout should consist of a small value series start resistor inserted between the start capacitor and the guard pin. Boot loop sizes, including rboot and cboot, should be as small as possible. When operating above 15vin, the control effective high-side mosfet switching slew rate exceeds vshw. RBOOT Improves Noise Operation Synchronous buck designs may have noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting the boot resistor reduces the efficiency of the drmos. Efficiency must be considered a trade-off with noise. Turning on values from 0.5Ω to 3.0Ω typically reduces VSWH overshoot. 8. The vin and pgnd pins handle high current frequency components greater than 100MHz, if possible, these pins should be connected directly to the VIN and to the ground plane. Using thermal traces in series with these pins is discouraged as this will increase the inductive path for power. This adds series inductance to the vin or pgnd pins and reduces system noise immunity by increasing positive and negative vswh ringing. 9. The ground pad and PGND pin should be connected to a multi-via stable gnd copper plane ground. Poor grounding will generate noise cgnd and PGND. This can lead to incorrect operation of gate drivers and mosfets. 10. Ringing at the pilot pin is most effectively controlled by the tight placement of the pilot capacitor. Do not add extra boot capacitors to pgnd. This can cause excessive current to flow through the boot diode. 11. The internal weakness of the SMOD and DISB pins are the pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not float these pins unless absolutely necessary.