The ADT7473/ADT7473-1 controllers are a thermal monitor and multiple PWM fan controllers for noise-sensitive or power-sensitive applications that require active system cooling. The ADT7473/ADT7473-1 can drive fans with a low frequency or high frequency drive signal, monitor the temperature of up to two remote sensing diodes plus its own internal temperature, and measure and control the speed of up to four fans at the lowest possible speed speed to keep noise to a minimum. An automatic fan speed control loop optimizes fan speed for a given temperature. The unique Dynamic T control mode enables intelligent management of the system's thermal/acoustics. Min heat input can be used. The ADT7473/ADT7473-1 also provide thermal protection of the system using a bidirectional thermal pin as the output to prevent overheating of the system or components.

Features: Control and monitor up to 4 fans; high and low frequency fan drive signals; 1 on-chip and 2 remote temperature sensors; series resistance cancellation on remote channels; extended temperature measurement range up to 191°C; dynamic T control mode intelligently optimizes system acoustics; automatic fan speed control mode controls system cooling based on measured temperature; enhanced acoustic mode significantly reduces user perception of fan speed changes; thermal output thermal protection function; monitors the performance of Intel Pentium 4 processors Performance impact; thermal control circuit via heat input; 3-wire and 4-wire fan speed measurement; limit comparison of all monitored values; compliant with SMBus 2.0 electrical specification.

Product Description

The ADT7473/ADT7473-1 is a complete thermal monitor and multi-fan controller for any system requiring thermal monitoring and cooling. Devices communicate with the system through the serial system management bus. The serial bus controller has a serial data line (pin 16) for reading and writing addresses and data and an input line (pin 1) for the serial clock. All control and programming functions of the ADT7473/ADT7473-1 are performed over the serial bus. Additionally, the pin can be reconfigured to smbalert output to signal out of limit conditions.

recommended implementation

Configuring the ADT7473 as shown in Figure 12 allows the system designer to use the following features: two PWM outputs for fan control of up to three fans (front and rear chassis fans in parallel.); three tachometer fan speed measurement inputs; V via pin 3 Internal measurement; CPU temperature measured using Remote 1 temperature channel; Ambient temperature measured by Remote 2.

temperature channel.

Two-way thermal pins. This feature allows Intelpentium 4 Prochhot monitoring and can be output as overheat heat. It can also be programmed to interrupt output for the smbalert system.

serial bus interface

On PCs and servers, the ADT7473/ADT7473-1 is controlled using SMBus. The ADT7473/ADT7473-1 connects to this bus as a slave device under the control of a master controller (usually (but not necessarily)).

The ADT7473 has a fixed 7-bit serial bus address of 0101110 or 0x2E. The read/write bits must be added to get an 8-bit address (01011100 or 0x5C). When the ADT7473-1 is powered up with pin 8 (pwm3/addren) high, the default SMBus address for the ADT7473-1 is 0101110 or 0x2e. If multiple ADT7473-1s are used in the system, each ADT7473-1 is in ADDR select mode by holding pin 8 low at power-up. Then, the logic state of pin 4 determines the smbus address of the device. The logic of these pins is sampled at power up. When the serial bus address byte matches the selected slave address, the device address is sampled at power-up and locked on the first valid smbus transaction, more precisely at the beginning of the eighth scl pulse on the low-to-high transition. Use addren pin/addr to select pin. After this, any attempt to change the address will have no effect.

Don't let addren disconnect! Can cause unpredictable addresses. Care should be taken to ensure that pin 8 (pwm3/addren) is either high or low. Leaving pin 8 floating may cause the ADT7473-1 to power up with an unexpected address.

Note that if the ADT7473-1 is put into ADDR select mode, pins 8 and 4 can be used for alternate functions (PWM3, TACH4/THERM) unless the correct circuit is mixed in at the right time or designed to handle these dual functions.

The ability to make hardwired changes to the SMBUS slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example if multiple ADT7473-1s are used in the system.

Data is sent over the serial bus in a sequence of 9 clock pulses: 8 bits of data followed by an acknowledgment bit from the slave. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition while the clock is high may be interpreted as a stop signal. The number of bytes of data that can be transferred over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle.

A stop condition is established when all data bytes are read or written. In write mode, the master asserts a stop condition by pulling the data line high during the tenth clock pulse. In read mode, the master overwrites the acknowledgment bit by pulling the data line high in the low cycle before the ninth clock pulse; this is called no acknowledgment. The master asserts the stop condition by taking the data line low during the low period before the tenth clock pulse and then high during the tenth clock pulse.

Any amount of data can be transferred over the serial bus in one operation, but reads and writes cannot be mixed in one operation because the operation type is determined at the beginning and cannot be followed without starting a new operation Change.

In the ADT7473/ADT7473-1, a write operation consists of one or two bytes, and a read operation consists of one byte. To write data to or read data from the device data registers, the address pointer register must be set up so that the correct data register can be addressed before data can be written to or read from it. The first byte of a write operation always contains the address stored in the address pointer register. If data is written to the device, the write operation consists of writing the second data byte of the register selected by the address pointer register.

This write operation is shown in Figure 17. The device address is sent over the bus, then R/W is set to 0. Followed by two data bytes. The first data byte is the address of the internal data register to be written, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two possibilities:

1. If the address point register value of the ADT7473/ADT7473-1 is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7473/ADT7473-1, but since no data is written to the register, only a data byte containing the register address is sent. As shown in Figure 18. A read operation is then performed, including the serial bus address with the r/w bit set to 1, followed by the data byte read from the data register. As shown in Figure 19.

2. If it is known that the address pointer register has been read at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 19.

If the value of the address pointer register is already correct, a data byte can be read from the data register without first writing to the address pointer register. However, it is not possible to write data to the address pointer register without writing to the address pointer register, because the first data byte written is always written to the address pointer register. In addition to supporting the Send Bytes and Receive Bytes protocols, the ADT7473/ADT7473-1 also supports the Read Bytes protocol.

If multiple read or write operations must be performed in succession, the host can send a repeated START condition instead of a STOP condition to start a new operation.

Voltage measurement input

The ADT7473/ADT7473-1 have an external voltage measurement channel and can also measure its own supply voltage, VCC. Pin 14 measures VCCP. VCC supply voltage measurement is made through the V pin (pin 3). In computer systems, the V input can be used to monitor the supply voltage of the chipset.

analog to digital converter

All analog inputs are multiplexed into on-chip, successive approximation, analog-to-digital converters. (ADC) resolution is 10 bits. The basic input range is 0 V to 2.25 V, but the input has built-in attenuators, allowing V to be measured without any external components. To allow for tolerances in supply voltages, the ADC produces an output of 3/4 full scale (768 decimal or 300 hex) for the nominal input voltage, so there is plenty of room to handle overvoltages.

input circuit

The internal structure of the V analog input is shown in Figure 23. The input circuit consists of input protection diodes, attenuators and capacitors to form a first-order low-pass filter that provides input immunity to high-frequency noise.

VCCP Limit Register

Associated with the v measurement channel is a high and low limit register. Exceeding the programmed upper or lower limit sets the corresponding status bit.

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS Many other functions are available on the ADT7473/ADT7473-1 to increase the flexibility of the system designer.

off average

For each voltage measurement read from the value register, 16 readings have actually been taken internally and the results are averaged before putting them into the value register. When faster conversions are required, setting Bit 4 (0x73) of Configuration Register 2 will turn off averaging. This effectively speeds up reads by a factor of 16 (711s), but reads can be noisier.

Bypass Voltage Input Attenuator

Setting Bit 5 of Configuration Register 2 (0x73) will remove the attenuation circuit from the V input. This allows the user to directly connect external sensors or rescale the analog voltage measurement input for other applications. The input range of the adc without the attenuator is 0v to 2.25v.

single channel adc conversion

Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7473/ADT7473-1 in single-channel ADC conversion mode. In this mode, the ADT7473/ADT7473-1 can only read a single voltage channel. If using the internal ADT7473/ADT7473-1 clock, the selected input is read every 711s. Select the appropriate ADC channel by writing to Bits<7:5> of the TACH1 Minimum High Byte register (0x55).

temperature measurement method

An easy way to measure temperature is to use the negative temperature coefficient of a diode to measure the base-emitter voltage (V) of a transistor operating at a constant current. Unfortunately, this technique requires calibration to remove the effect of the absolute value of v, which varies from device to device.

The technique used in the ADT7473/ADT7473-1 measures the change in V when the device is operated at three different currents. Previous devices only used two operating currents, but using a third current automatically removes the resistance in series with the external temperature sensor.

Figure 24 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but could also be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be connected to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased to ground by an internal diode at the D input. C1 can optionally be added as a noise filter (maximum 1000 pF recommended). However, in noisy environments, a better option is to add a filter, as described in the Noise Filtering section.

Local temperature measurement

The ADT7473/ADT7473-1 contain an on-chip bandgap temperature sensor whose output is digitized by an on-chip 10-bit ADC. The 8-bit msb temperature data is stored in the local temperature register (0x26). Since both positive and negative temperatures can be measured, temperature data is stored in offset 64 or two's complement format, as shown in Table 14 and Table 15. In theory, the temperature sensor and ADC can measure temperatures from -63°C to +127°C (or -63°C to +191°C in the extended temperature range) with +0.25°C resolution. However, this is outside the operating temperature range of the device, so local temperature measurements outside the operating temperature range of the ADT7473/ADT7473-1 are not possible.

Remote temperature measurement

The ADT7473/ADT7473-1 can measure the temperature of two remote diode sensors or diode-connected transistors connected to pins 10 and 11 or pins 12 and 13.

The forward voltage of diodes or diode-connected transistors operating at constant current shows a negative temperature coefficient of about -2 mV/°C. Unfortunately, the absolute value of V varies from device to device and requires individual calibration to remove this, so this technique is not suitable for mass production. The technique used in the ADT7473/ADT7473-1 is to measure the change in V as the device operates at three different currents. This is given by:

where: k is the Boltzmann constant. t is the absolute temperature in Kelvin; Q is the charge on the carrier; n is the ratio of the two currents.

Figure 24 shows the input signal conditioning used to measure the output of a remote temperature sensor. This image shows an external sensor as a substrate transistor used to monitor temperature on some microprocessors. It can also be discrete transistors like 2N3904/2N3906.

If a discrete transistor is used, the collector is not grounded and should be connected to the base. If using a PNP transistor, connect the base to the D- input and the transmitter to the D+ input. If using an NPN transistor, the transmitter is connected to the D- input and the base is connected to the D+ input. Figure 25 and Figure 26 show how to connect the ADT7473/ADT7473-1 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative side of the sensor is not referenced to ground, but is biased to ground by an internal diode at the D- input.

To measure the voltage, the operating current through the sensor is switched between three related currents. n1×i and n2×i are different multiples of current i, as shown in Figure 24. The current through the temperature diode switches between i and n1×i, giving v, and then switches between i and n2×i, giving v. The temperature can then be calculated using the two v measurements. This method also eliminates the effect of series resistance on temperature measurements.

The resulting v-waveform is passed through a 65khz low-pass filter to remove noise and then goes to a chopper-stabilized amplifier. This will amplify and rectify the waveform to produce a DC voltage proportional to V. The ADC digitizes this voltage and produces a temperature measurement. To reduce the effect of noise, digital filtering is performed by averaging the results over 16 measurement cycles.

As shown in Table 10, the results of the remote temperature measurement are stored in 10-bit two's complement format. Additional resolution for temperature measurements is stored in Extended Resolution Register 2 (0x77). This will give a temperature reading with a resolution of 0.25°C.

noise filtering

For temperature sensors operating in a noisy environment, it was previously practice to place a capacitor between the D+ and D- pins to help combat the effects of noise. However, large capacitance can affect the accuracy of temperature measurement, so the recommended maximum capacitance value is 1000 pf. Such capacitors reduce noise, but do not eliminate it, making the sensor difficult to use in very noisy environments.

The ADT7473/ADT7473-1 have a major advantage over other devices in eliminating the effects of noise on external sensors. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the component. The effect of any filter resistance in series with the remote sensor is automatically removed from the temperature results.

The structure of the filter allows the ADT7473/ADT7473-1 and the remote temperature sensor to operate in noisy environments. Figure 27 shows a low-pass RC filter with the following values:

This filtering reduces both common-mode noise and differential noise.

Series Resistance Elimination

The parasitic resistance (in series with the remote diode) to the ADT7473/ADT7473-1 D+ and D- inputs is caused by a variety of factors, including PCB trace resistance and trace length. This series resistance shows up as a temperature offset in the remote sensor's temperature measurement. This error typically results in a 0.5°C offset per parasitic resistance in series with the remote diode.

The ADT7473/ADT7473-1 automatically eliminates the effect of this series resistance on temperature readings, giving more accurate results without requiring the user to describe the resistance. The ADT7473/ADT7473-1 are designed to automatically eliminate resistors up to 3K typically. It is transparent to the user using advanced temperature measurement methods. This feature allows resistors to be added to the sensor path to create filters, allowing the part to be used in noisy environments. See the Noise Filtering section for details.

Factors Affecting Diode Accuracy

Remote sensing diode

The ADT7473/ADT7473-1 are designed to work with substrate transistors or discrete transistors built into processors. Substrate transistors are usually of the pnp type, with the collector connected to the substrate. The discrete type can be a PNP or NPN transistor connected as a diode (base to collector shorted). If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D-. If a PNP transistor is used, the collector and base are connected to D- and the emitter is connected to D+.

To reduce errors due to variations in substrate transistors and discrete transistors, several factors should be considered:

(1) The ideality factor n of a transistor is a measure of the thermal diode's deviation from ideal behavior. The ADT7473/ADT7473-1 are trimmed to an n value of 1.008. When using a transistor with n not equal to 1.008, use the following formula to calculate the error introduced at temperature t (°C). See the relevant CPU's datasheet for n values.

To take this into account, the user can write the t value to the offset register. The ADT7473/ADT7473-1 then automatically adds or subtracts it from the temperature measurement.

(2) Some CPU manufacturers specify high and low current levels for substrate transistors. The high current level of the ADT7473/ADT7473-1 is 96 A and the low current level, ILOW, is 6 A. If the current levels of the ADT7473/ADT7473-1 do not match the current levels specified by the CPU manufacturer, the offset may need to be removed. The CPU's datasheet suggests if this offset needs to be removed and how to calculate it. This offset can be programmed into the offset register. The caveat is that if multiple offsets must be considered, the algebraic sum of those offsets must be programmed into the offset register.

If discrete transistors are used with the ADT7473/ADT7473-1, the best accuracy can be obtained by selecting the device according to the following criteria:

(1) At the highest operating temperature, the base-emitter voltage at 6 A is greater than 0.25 V.

(2) At the lowest operating temperature, the base-emitter voltage at 100 A is less than 0.95 V.

(3), the basic resistance is less than 100

(4) Small changes in H (such as 50 to 150), indicating tight control over VBE characteristics. Iron transistors, such as the 2N3904, 2N3906, or the equivalent in the SOT-23 package, are suitable devices to use.

Eliminate temperature errors

As CPUs run faster, it becomes more difficult to avoid high frequency clocks when routing D+/D- traces around the system board. Even if the recommended layout guidelines are followed, some temperature errors can still be attributed to noise coupled onto the D+/D- lines. Constant high frequency noise usually attenuates or increases the temperature measurement by a linear constant value.

The ADT7473/ADT7473-1 have temperature offset registers for the Remote 1 and Remote 2 temperature channels at Register 0x70 and Register 0x72. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and zero it out using the offset register. The offset register automatically adds a 2's complement 8-bit readout to each temperature measurement. The LSB adds a +0.5°C offset to the temperature reading, so the 8-bit register effectively allows temperature offsets up to ±64°C with +0.5°C resolution. This ensures that the readings in the temperature measurement registers are as accurate as possible.

overtemperature event

Overtemperature events on any temperature channel can be automatically detected and handled in automatic fan speed control mode. Register 0x6a to Register 0x6c are thermally limited. When the temperature exceeds its thermal limit, all PWM outputs operate at 100% duty cycle or the maximum PWM duty cycle (Register 0x38, Register 0x39, and Register 0x3A) if Configuration Register 4 (0x7D) is set ) of bit 3. The fan runs at this speed until the temperature drops to Therm minus the hysteresis; this can be disabled by setting the boost bit in Bit 2 of Configuration Register 3 (0x78). The hysteresis value for this thermal limit is the value programmed into the hysteresis registers (Register 0x6d and Register 0x6e). The default hysteresis value is 4°C.

Interrupt Status Register

The result of the limit comparison is stored in Interrupt Status Register 1 and Interrupt Status Register 2. The status register bits for each channel reflect the status of the last measurement and limit comparison on that channel. If the measured value is within the limits, the corresponding status register bit is cleared to 0. If the measurement exceeds the limit, the corresponding status register bit is set to 1.

The status of the various measurement channels can be polled by reading the status register over the serial bus. In Interrupt Status Register 1 (REG.0x41), 1 indicates that a limit exceeded event is flagged in Interrupt Status Register 2. This means that the user only needs to read the Interrupt Status Register 2 when this bit is set. Alternatively, pin 5 or pin 9 on the ADT7473 can be configured as the smbalert output, while only pin 9 can be configured as the smbalert on the ADT7473-1. This will automatically notify the system supervisor of the limit violation. Whenever the error condition that caused the interrupt is cleared, reading the status register clears the corresponding status bit. Status register bits (except ovt) are sticky. Whenever a status bit is set, indicating that a limit condition has been exceeded, it remains set even if the event that caused it has disappeared (until read). The only way to clear the status bits is to read the status register after the event disappears. The interrupt mask registers (Register 0x74 and Register 0x75) allow masking of a single interrupt source to cause smbalert. However, if one of the masked interrupt sources exceeds the limit, its associated status bit will be set in the interrupt status register. ovt is automatically cleared.

smbalert interrupt behavior

The status of the ADT747/ADT7473-1 can be polled and an SMBAlert interrupt can be generated to prevent a limit violation. When writing interrupt handler software, it must be noted that once s exceeds the limit, the corresponding status bit will be set to 1. The interrupt status bits remain set until the error condition disappears and the interrupt status register is read. Status bits are called sticky bits because they remain set until they are read by software. This ensures that if the software periodically polls the device, events that exceed the limit are not missed. Note that the smbalert output remains low for the entire duration of the read out-of-limit until the interrupt status register is read. This has implications for how software handles interrupts. Behavior of mbalert outputs and status bits.

Note that overheat events are not sticky, reset stops immediately after an overheat condition. This also applies to smbalert if associated with an ovt event.

Handling smbalert interrupts

When preventing the system from being interrupted by bundled maintenance, it is recommended to handle the smbalert interrupt as follows:

1. Detect smbalert assertions.

2. Enter the interrupt handler.

3. Read the status register to identify the source of the interrupt.

4. Mask the interrupt source by setting the appropriate mask bits in the interrupt mask registers (Register 0x74 and Register 0x75).

5. Take the appropriate action for the given interrupt source.

6. Exit the interrupt handler.

Periodically poll the status register. If an interrupt status bit is cleared, reset the corresponding interrupt mask bit to 0. This will cause the smbalert output and status bits to behave as shown in Figure 30.

Mask interrupt sources

Register 0x74, Interrupt Mask Register 1; Register 0x75, Interrupt Mask Register 2; these registers allow masking of individual interrupt sources to prevent smbalert interrupts. Masking the interrupt source only prevents the smbalert output from being asserted; the appropriate status bits are normally set.

Assign thermal functions to pins

Pin 9 on the ADT7473/ADT7473-1 has four possible functions: smbalert, therm, gpio, and tach4. The user selects the desired function by setting Bit 0 and Bit 1 of Configuration Register 4 (0x7d). Once pin 9 is configured as THERM, it must be enabled by setting Bit 1 (0x78) of Configuration Register 3.

heat as input

The ADT7473/ADT7473-1 can time assert the THERM pin when THERM is configured as an input. This is useful for connecting to the prochot output of the cpu to measure system performance. See the Therm Timer section for more information.

The user can also program the ADT7473/ADT7473-1 so that the fan runs at 100% speed when the external drive thermal pin is too low. The fan runs at 100% for the time the hot pin is pulled low. This is done by setting the boost bit (bit 2) in configuration register 3 (0x78) to 1. This only works when the fan is already running (eg in manual mode when the current duty cycle is above 0x00), or in auto mode when the temperature is above tmin. Pulling the external low temperature has no effect if the temperature is below tmin or if the duty cycle in manual mode is set to 0x00. See Figure 31 for more information.

hot timer

The ADT7473/ADT7473-1 have an internal timer that measures the thermal assertion time. For example, the Therm input can be connected to the prochot output of a Pentium4 CPU to measure system performance. This thermal input can also be connected to the output of the trigger point temperature sensor. The timer asserts the ADT7473/ADT7473-1 heat input and the heat is released. The timer counts up therm times; that is, the timer continues to count to the next thermal assertion. The Therm timer continues to accumulate Therm assertion time until the timer is read (cleared on read) or reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. The 8-bit thermal timer status register (0x79) is designed so that bit 0 of the first therm assertion is set to 1. Once the accumulated thermal assertion time exceeds 45.52ms, bit 1 of the thermal timer is set, and bit 0 becomes the LSB of the timer with a resolution of 22.76ms.

When using the heat timer, please note the following. After hot timer read (0x79):

1. The content of the timer is cleared when it is read.

2. The F4P bit (bit 5) of the interrupt status register 2 needs to be cleared (assuming the thermal timer limit has been exceeded).

If the therm timer is read during a therm assertion, the following happens:

1. The contents of the timer are cleared.

2. Bit 0 of the Therm timer is set to 1 (because the Therm assertion is taking place).

3. The calorie timer increments from 0.

4. If Thermal Timer Limit (Register 0x7A) = 0x00, set the F4P bit.

Issue a smbalert when the programmable thermal timer limit is exceeded. This allows system designers to ignore short, uncommon therm assertions when capturing longer therm timer events. Register 0x7a is the thermal timer limit register. This 8-bit register allows to set a limit from 0 seconds (the first therm assertion) to 5.825 seconds before generating the smbalert. Compare the therm timer value with the contents of the therm timer limit register. If the thermal timer value exceeds the thermal timer limit, the F4P bit (bit 5) of the interrupt status

Register 2 is set and smbalert is generated. The F4P bit (bit 5) of the interrupt mask register 2 (0x75) masks out the smbalert if this bit is set to 1; however, if the thermal timer limit is exceeded, the f4p bit of the interrupt status register 2 is still set. Writing a value of 0x00 to the therm timer limit register (0x7a) causes a smbalert to be generated on the first therm assertion. A therm timer limit value of 0x01 will generate a smbalert once the accumulated thermal assertion exceeds 45.52 ms.

Configure thermal behavior

1. Configure pin 9 as the thermal timer input. Setting Bit 1 (Thermal Timer Enable) of Configuration Register 3 (0x78) enables the thermal timer monitoring function. This is disabled on pin 9 by default. Setting bit 0 and bit 1 (pin9func) of configuration register 4 (0x7D) to enable the thermal timer/output function on pin 9 (bit 1) must also set configuration register 3 (therm). Pin 9 can also be used as tachometer 4 . Setting Bit 5, Bit 6, and Bit 7 of Configuration Register 5 (0x7c) makes therm bidirectional. This means that if the appropriate temperature channel exceeds the thermal temperature limit, the thermal output is asserted. The Therm timer is also multiplied by the Therm assertion if the ADT7473 is not pulling the heat down, but the heat is being pulled down by an external device (such as a CPU overheat signal). Therm is only set as a timer input if Bit 5, Bit 6, and Bit 7 of Configuration Register 5 (0x7c) are set to 0.

2. Select the desired fan behavior for the thermal timer event. Assuming the fans are running, setting bit 2 (boost) of configuration register 3 (0x78) to cause all fans to run at 100% duty cycle at all times Therm is asserted. This allows for failsafe system cooling. If this bit is 0, the fan operates at its current setting and is not affected by thermal events. If the fan is not already running when therm is asserted, the fan will not run at full speed.

3. Select whether the Therm Timer event should generate a smbalert interrupt. Bit 5 (F4P) of Interrupt Mask Register 2 (0x75), when set, masks smbalert when the thermal timer limit value is exceeded. If smbalertis is based on the desired therm event.

4. Select the appropriate thermal limit value. This value determines whether the smbalert is generated on the first therm assertion, or only when the cumulative therm assertion time limit is exceeded. A value of 0x00 results in the first hot assertion.

5. Select the thermal monitoring time. This value specifies how often the operating system or BIOS-level software checks the Therm timer. For example, the bios can read the therm timer every hour to determine the accumulated therm assertion time. For example, if the total thermal assertion time is less than 22.76 ms at hour 1, greater than 182.08 ms at hour 2, and > 5.825 seconds at hour 3, this may indicate that system performance is degrading significantly because Therm asserts more frequently every hour. Alternatively, software at the operating system or BIOS level can time-stamp when the system is powered on. If a timer limit (adjust 0x7a) mbalert is generated due to exceeding the therm timer limit, another timestamp can be used. The time difference can be calculated as a fixed thermal timer limit time. For example, if it takes one week to exceed the heat timer limit of 2.914 seconds, and the next one only takes an hour, it is an indication of severe system performance degradation.

Configuring Therm Pins for Bidirectional In addition to monitoring therm as an input, the adt7473/adt7473-1 can optionally drive therm low as an output. When the prochot is bidirectional, the therm can be used to limit the processor by asserting the prochot. The user can pre-program critical system thermal limits. Therm asserts low if the temperature exceeds the thermal limit by 0.25°C. If the temperature is still above the thermal limit for the next monitoring cycle, therm remains low. The heat is kept low until the temperature is at or below the thermal limit. Because the temperature of the channel is only measured once per monitoring cycle after Therm is asserted, it is guaranteed to remain low for at least one monitoring cycle.

If the thermal temperature limit for Remote 1, Local or Remote 2 exceeds 0.25°C. The thermal temperature limit registers are located in Register 0x6a, Register 0x6b, and Register 0x6c. Setting bits 5, 6 and 7 of configuration register 5 (0x7c) makes the therm bidirectional for the remote 1, local and remote 2 temperature channels, respectively. Figure 34 shows the Therm Pin setting low output to low output during critical overtemperature conditions.

Another way to disable therm is to program the therm temperature limit to -64°C or lower in offset 64 mode, or -128°C or lower in two's complement mode; that is, for Below the therm temperature limit of -63°C or lower – 128°C respectively, thermal is disabled. Therm (0x78) can also be disabled by setting Bit 1 of Configuration Register 3 to 0.

Fan drive with pwm control

The ADT7473/ADT7473-1 use pulse width modulation (PWM) to control fan speed. This relies on changing the duty cycle (or on/off ratio) of the square wave applied to the fan to change the fan speed. Using pwm to control the external circuitry needed to drive the fan is very simple. For 4-wire fans, the pwm driver may only need a pull-up resistor. In many cases, the 4-wire fan pwm input has a built-in pull-up resistor. The PWM frequency of the ADT7473/ADT7473-1 can be set to select a low frequency or a single high PWM frequency. The low frequency option is typically used for 3-wire fans, while the high frequency option is typically used for 4-wire fans.

Note that care must be taken to ensure that the tachometer pin is not connected to a pull-up supply greater than 3.6 V. Many fans have internal pull-ups connected to the RPM/PWM pins with supply voltages greater than 3.6V. If necessary, the voltage on these pins must be clamped or reduced. Clamping these pins with Zener diodes also helps prevent back-EMF related noise from coupling into the system.

For a 3-wire fan, only one n-channel mosfet driver is required. The specification of the mosfet depends on the maximum current required to drive the fan. A typical laptop fan is rated at 170mA; therefore, SOT devices can be used where board space is a concern. In desktops, the fan can usually draw between 250mA and 300mA. If driving multiple fans in parallel or driving larger server fans from a single pwm output, the mosfet must handle higher current requirements. The only other stipulation is that the mosfet has gate voltage drive, v<3.3v, for direct connection to the pwm output. The mosfet should also have low on-resistance to ensure that there is no significant voltage drop across the fet, which will reduce the voltage applied to the fan and thus reduce the maximum operating speed of the fan. Figure 35 shows how to drive a 3-wire fan using PWM control.

Figure 35 uses a 10k pull-up resistor as the tach signal. This assumes the tach signal is an open collector from the fan. In all cases, the speed signal from the fan must be kept below 3.6 V maximum to prevent damage to the ADT7473/ADT7473-1. If you are not sure if the fan you are using has an open collector or totem pole tachometer output, use one of the input signal conditioning circuits shown in the "Fan Speed Measurement" section.

Figure 36 shows a fan drive circuit using npn transistors such as the generic mmbt2222. While these devices are inexpensive, they tend to have lower current handling capabilities and higher on-resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the current requirements of the fan. Make sure the base resistor is chosen so that the transistor saturates when the fan is powered up.

Since the 4-wire fan is powered continuously, the fan speed doesn't turn on or off like previous pwm driven/powered fans. This makes it better than 3-wire fans, especially in high frequency applications.

Figure 37 shows a typical drive circuit for a 4-wire fan. Since the PWM input on 4-wire fans is typically pulled internally to a voltage greater than 3.6 V (the maximum voltage allowed on the PWM output of the ADT7473/ADT7473-1), a Zener diode should be used to switch the PWM output Clamped to 3.3 V.

Drive two fans from PWM3

The ADT7473/ADT7473-1 have four tachometer inputs for fan speed measurement, but only three PWM drive outputs. If a fourth fan is used in the system, it should be paralleled with the third fan, driven from the PWM3 output. Figure 38 shows how to drive two fans in parallel using low-cost NPN transistors. Figure 39 shows the equivalent circuit using a mosfet.

Because the mosfet can handle up to 3.5A, just put another fan directly in parallel with the first fan. When designing driver circuits with transistors and FETs, care should be taken to ensure that the pwm pins are not required to source current and that their current sink is less than the 8mA maximum current specified in the datasheet.

Drive up to three fans from PWM3

The fan's RPM measurement is synchronized to a specific PWM channel; for example, RPM1 is synchronized to PWM1. Both TACH3 and TACH4 are synchronized with PWM3, so PWM3 can drive both fans. Alternatively, PWM3 can be programmed to synchronize Tach 2, Tach 3, and Tach 4 to the PWM3 output. This allows the PWM3 to drive two or three fans. In this case, the driver circuit looks the same, as shown in Figure 38 and Figure 39. The sync bit in Register 0x62 enables this feature.

When used with 4-wire fans, no synchronization is required in high frequency mode.

Speed up input

Pin 4, Pin 6, Pin 7, and Pin 9 (when configured as tachometer inputs) are open-drain tachometer inputs for fan speed measurement. Signal conditioning in the ADT7473/ADT7473-1 adjusts the slow rise and fall times of the typical output of a fan tachometer. The maximum input signal range is 0 V to 3.6 V. If these inputs are provided by fan outputs in excess of 0 V to 3.6 V, resistive attenuation or diode clamping of the fan signal must be included to keep the inputs within acceptable limits. If the resistance of the fan speed output rises to V, it can be connected directly to the fan input, as shown in Figure 40.

If the resistance of the fan output rises to 12 V (or other voltages greater than 3.6 V), the fan output can be clamped with a Zener diode, as shown in Figure 41. The Zener diode voltage should be chosen so that it is greater than the V of the tachometer input, but less than 3.6 V, allowing a voltage tolerance for the Zener. A value between 3.0 V and 3.6 V is suitable.

If the fan has a strong pull-up (less than 1K) to 12V or a totem pole output, a series resistor can be added to limit the zener current as shown in Figure 42.

Rise to >VCC or totem pole output, attenuated with R1/R2, or a resistive attenuator can be used as shown in Figure 43.

Fan speed measurement

The fan counter does not directly count the output pulses of the fan tachometer because the fan speed may be less than 1000 rpm and it will take several seconds to accumulate a fairly large and accurate count. Instead, the period of the fan speed is measured by gating a 90 kHz on-chip oscillator to the input of a 16-bit counter for n cycles of the fan speed output (see Figure 44), so the accumulated count is actually the same as the fan speed The period is proportional to the fan speed and inversely proportional. n, the number of pulses counted is determined by the setting of the tachometer pulses per revolution register (register 0x7b). This register contains two bits per fan, allowing one, two (default), three or four tach pulses to be counted.