The AD9215 is a family of monolithic, single 3V supply, 10-bit, 65/80/105MSPS analog-to-digital converters (ADCs). This series features high performance sample and hold amplifiers (sha) and voltage references. The AD9215 uses a multi-stage differential pipeline structure with output error correction logic to provide 10-bit accuracy at a data rate of 105 msps and guarantees no code loss over the entire operating temperature range.

The wide bandwidth, true differential sample-and-hold amplifier (SHA) allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in continuous channels, as well as sampling single-channel inputs at frequencies well beyond the Nyquist rate. Not only does the AD9215 save power and cost compared to previously available ADCs, it is also suitable for applications in communications, imaging, and medical ultrasound.

A single-ended clock input controls all internal conversion cycles. The duty cycle stabilizer compensates for large changes in the clock duty cycle while maintaining good performance. Digital output data is displayed in binary or two's complement format. The out-of-range signal indicates an overflow condition and can be used with the msb to determine low overflow or high overflow.

Manufactured on an advanced CMOS process, the AD9215 is available in 28-lead surface mount plastic and 32-lead chip scale packages and is specified over the industrial temperature range of -40°C to +85°C.

Product Highlights

1. The AD9215 is powered by a 3V power supply and has a separate digital output driver power supply that accommodates both 2.5V and 3.3V logic families.

2. The core adc of ad9215 works at 105msps, with a low power consumption of 120mw; at 80msps, the power consumption is 104mw; at 65msps, the power consumption is 96mw.

3. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be configured for single-ended or differential operation.

4. The AD9215 is part of several pin-compatible 10-, 12-, and 14-bit low-power ADCs. This allows for simplified upgrades from 10-bit to 12-bit with systems up to 80 msps.

5. The clock duty cycle stabilizer maintains converter performance over a wide range of clock pulse widths.

6. The out-of-range (OR) output bit indicates when the signal is outside the selected input range.

Normative Definition:

Aperture delay

Aperture delay is a measure of the performance of a sample-and-hold amplifier (SHA), measured from the rising edge of the clock input to the time it takes for the hold input signal to transition.

Aperture jitter

Aperture jitter is the variation in aperture delay of successive samples, which can appear as frequency-dependent noise input to the ADC.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that a clock pulse remains in a logic 1 state to achieve rated performance. Pulse width low is the minimum time a clock pulse should remain low. These specifications define acceptable clock duty cycles for a given clock rate.

Differential Nonlinearity (DNL, no missing code)

The ideal adc shows transcoding at exactly 1 lsb intervals. dnl is the deviation from this ideal value. Guaranteed to have no missing codes at 10-bit resolution means that all 1024 codes must be present separately in all working ranges.

Effective Number of Bits (ENOB)

For a sine wave, sinad can be represented in bits. Using the following formula, a performance measure denoted as n, the number of effective bits, can be obtained

Therefore, at a given input frequency, the effective number of bits of a device for a sine wave input can be calculated directly from its measured sinad.

gain error

The first code transition should occur at 1/2 lsb of the analog value above negative full scale. The last conversion should occur at 1 1/2 lsb of the analog value below positive full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

Integral Nonlinearity (inl)

inl refers to the deviation of each individual code in the line drawn from "negative full scale" to "positive full scale". Points used as negative full scale occur 1/2 lsb before the first code transition. Positive full scale is defined as 1 1/2 LSB level beyond the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

Maximum conversion rate

The clock frequency at which the parametric test is performed.

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit by no more than 3 dB of the clock rate.

offset error

When the analog value is 1/2 lsb below vin+=vin-, a major carry transition should occur. Zero error is defined as the deviation of the actual transition point from this point.

Out of range recovery time

The out-of-range recovery time is the time it takes for the ADC to regain the analog input after transitioning from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

output propagation delay

The delay between the clock logic threshold and the time when all bits are within a valid logic level.

Power supply rejection

The specification shows the full-scale maximum change from the value at which supply is at its minimum limit to the value at which supply is at its maximum limit.

signal to noise ratio

sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC. The value of sinad is expressed in decibels.

snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and DC. The signal-to-noise ratio is expressed in decibels.

Spurious Free Dynamic Range (SFDR)

sfdr is the decibel difference between the rms amplitude of the input signal and the peak spurious signal.

temperature drift

The temperature drift of zero error and gain error is specified from the initial (25°C) value to tmin or tmax.

Total Harmonic Distortion (THD)

thd is the ratio of the rms value of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be imd products. It can be reported in dbc (that is, decreasing as signal level decreases) or dbfs (always relative to converter full scale).

Applying AD9215 Theory of Operation

The AD9215 architecture consists of a front-end SHA and a pipelined switched capacitor ADC. Each stage provides enough overlap to correct flash errors in previous stages. In the digital correction logic, the quantized outputs from each stage are combined into a final 10-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the clock.

The input stage contains a differential SHA, which can be configured as ac-coupled or dc-coupled in differential or single-ended mode. Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched capacitor DAC and an interstage residual amplifier (MDAC). The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. Redundancy is used in each stage to facilitate digital correction of flash errors.

The output scratch block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

Overview of Analog Inputs and References

The analog input to the AD9215 is a differential switched capacitor SHA that is designed for optimum performance when processing differential input signals. The SHA input can support a wide common-mode range and maintain good performance, as shown in Figure 31. The input common-mode voltage of the intermediate supply minimizes signal-dependent errors and provides optimum performance. The clock signal alternately switches sha between sample mode and hold mode (see Figure 30). When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. Additionally, a small shunt capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the input of the ADC; therefore, the exact value depends on the application. In undersampling applications, any parallel capacitors should be removed. Combined with the driving source impedance, they will limit the input bandwidth.

The analog inputs of the AD9215 have no internal dc bias. In AC-coupled applications, the user must provide this bias externally. V=AVDD/2 is recommended for best performance, but the device has a wider range of functions and reasonable performance (see Figure 31).

For best dynamic performance, the source impedances driving vin+ and vin- should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the ADC's common mode rejection.

Internal differential reference buffers generate positive and negative reference voltages reft and refb, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, while the reft and reference voltage and span are defined as:

As can be seen from the equation above, the reft and refb voltages are symmetrical around the mid-supply voltage, and by definition the input span is twice the value of the vref voltage.

The internal voltage reference can be pinned to a fixed value of 0.5 V or 1.0 V, or it can be adjusted within the same range discussed in the Internal Reference Connections section. Set the ad9215 to a maximum input range of 2v pp for maximum signal-to-noise performance. When switching from 2vp-p mode to 1vp-p mode, the relative signal-to-noise ratio decreases by 3db.

The sha can be driven from a source that keeps the signal peaks within the allowable range of the selected reference voltage. The minimum and maximum common-mode input levels are defined as:

The minimum common-mode input level allows the AD9215 to accommodate ground-referenced inputs.

Although the best performance is obtained with differential inputs, single-ended supplies may be driven to VIN+ or VIN-. In this configuration, one input accepts a signal, while the other input should be set to midscale by connecting it to the appropriate reference. For example, a 2 volt PP signal can be applied to VIN+, while a 1 volt reference voltage can be applied to VIN-. The ad9215 then receives a signal that varies between 2v and 0v. In a single-ended configuration, the distortion performance can be significantly reduced compared to the differential case. However, this effect is less pronounced at lower input frequencies.

Differential Input Configuration

As previously mentioned, the best performance is achieved when driving the AD9215 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and flexible interface to ADCs. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the 2nd Nyquist zone and above, the performance of most amplifiers is insufficient to achieve the true performance of the AD9215. This is especially true if sampling undersampling applications with frequencies in the 70 MHz to 200 MHz range. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor depends on the input frequency and source impedance and should be reduced or removed. As shown in Figure 33.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz, and excessive signal power can also cause the core to saturate, resulting in distortion.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, the sfdr and distortion performance is degraded due to large input common mode oscillation. However, if the source impedances at each input are kept matched, there should be little impact on the signal-to-noise performance. Figure 34 details a typical single-ended input configuration.

Clock Inputs and Considerations

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9215 includes a clock duty cycle stabilizer that retimes non-sampling edges to provide an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9215. As shown in Figure 25, the noise and distortion performance is nearly flat over a 50% duty cycle range. For best AC performance, it is recommended to enable the duty cycle stabilizer for all applications.

The duty cycle stabilizer uses a delay locked loop (DLL) to create non-sampling edges. Therefore, any change in sampling frequency requires about 100 clock cycles to allow high-speed, high-resolution ADCs to be very sensitive to the quality of the clock input. At a given full-scale input frequency (finput), the SNR degradation due to aperture jitter (ta) can be calculated as:

In the equation, the rms aperture jitter, t, represents the root sum squared of all jitter sources, including the clock input, the analog input signal, and the ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

In cases where aperture jitter may affect the dynamic range of the AD9215, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Consumption and Standby Modes

As shown in Figure 35, the power consumption of the AD9215 is proportional to its sampling rate. Digital power consumption does not vary substantially between the three speed grades, as it is primarily determined by the strength of the digital driver and the load on each output bit. The maximum drvdd current can be calculated as:

where n is the number of output bits, which is 10 for the ad9215. This maximum current is generated with each output bit turned on every clock cycle, which can only occur with a full-scale square wave at the Nyquist frequency f/2. In practical applications, the drvdd current is determined by the average number of switching bits of the output bits, which is determined by the encoding rate and the characteristics of the analog input signal.

Digital power consumption can be minimized by reducing the capacitive loading of the output driver. The data in Figure 35 was acquired with 5 pf loaded on each output driver.

The analog circuits are optimally biased, so each speed grade provides excellent performance while reducing power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with clock frequency.

By asserting the PDWN pin high, the AD9215 is placed in standby mode. In this state, the adc typically consumes 1 mw if the clk and analog inputs are static. During standby, the output drivers are in a high impedance state. Reinserting the PDWN pin low will return the AD9215 to normal operating mode.

In standby mode, low power consumption is achieved by turning off the reference, reference buffer, and bias network. The decoupling capacitors on this REFT and REFB are discharged when entering standby mode and must then be recharged when normal operation resumes. Therefore, the wake-up time is related to the time spent in standby mode, and a shorter standby period reduces the wake-up time accordingly. With the recommended 0.1µf and 10µf decoupling capacitors on reft and refb, it takes about 1 second to fully discharge the reference snubber decoupling capacitor and 7ms to return to full operation.

digital output

The AD9215 output driver can be configured to interface with 2.5V or 3.3V logic families by matching DRVDD to the digital supply of the interface logic. The output drivers are sized to provide enough output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

timing

The AD9215 provides a latched data output with a pipeline delay of 5 clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal. The length of the outer diameter output data lines and load should be minimized to reduce transients within the AD9215; these transients can degrade the dynamic performance of the converter. The minimum typical conversion rate of the AD9215 is 5 msps. Dynamic performance may degrade when clock rates are below 5ms/sec.

The AD9215 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9215 using the internal reference voltage or an externally applied reference voltage. The input range of the adc tracks the linear variation of the reference voltage. Maximum SNR and DNL performance were achieved by setting the AD9215 to a maximum input span of 2v pp.

Internal reference connection

The comparator in the AD9215 senses the potential at the sense pin and configures the reference into four possible states, as shown in Table 1. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 36), setting VREF to 1V. Connect the sensor pin to the VREF pin, switch the amplifier output to the sensor pin, configure the internal op-amp circuit as a voltage follower, and provide a 0.5V reference output. If an external resistor divider is connected as shown in Figure 37, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

In all reference configurations, reft and refb drive the ADC conversion core and determine its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

If the AD9215's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts the effect of the load on the internal reference voltage.

Xref Operations

It may be necessary to use an external reference to improve the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs are tracking each other, a single reference (internal or external) may be required to reduce gain matching errors to acceptable levels. A high-accuracy external reference can also be selected to provide lower gain and offset temperature drift. Figure 39 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes.

When the detect pin is bound to avdd, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (reft and refb) for the ADC core. The input range is always twice the value of the reference voltage; therefore, the maximum value of the external reference voltage must be limited to 1V.

Operation mode selection

As mentioned earlier, the AD9215 can output data in offset binary or two's complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (dcs). The mode pins are multi-level inputs that control the data format and dcs status. For best AC performance, it is recommended to enable the duty cycle stabilizer for all applications.

Evaluation Committee

The AD9215 evaluation board has been discontinued. The following evaluation committee documents are for informational purposes only.

The AD9215 evaluation board provides all the support circuitry required to operate the ADC in various modes and configurations. The converter can be driven by the AD8351 driver, transformer, or single-ended differential. A separate power supply pin is provided to isolate the device under test from supporting circuitry. Each input configuration can be selected by the correct connection of various jumpers (see schematic). Figure 40 shows a typical bench characterization setup used to evaluate the ac performance of the AD9215. Using a signal source with very low phase noise (<1ps rms jitter) is key to achieving the ultimate converter performance. Appropriate filtering of the input signal to remove harmonics and reduce the overall noise at the input is also a necessary condition to achieve the specified noise performance.