General Description Features These devices are low cost, high speed, dual JFET input OP-N Internally trimmed bias voltage: 15 mV op amp, internally trimmed input bias N Low input bias current: 50 Pa voltage (BI-FET II 8482 ;technology). They require low power supply n low input noise voltage: 16nv/√hz current, while maintaining a large gain bandwidth product and fast low input noise current: 0.01pa/√hz slew rate. In addition, well-matched high voltage JFET input wide gain bandwidth: 4MHz Nn
The device provides very low input bias and bias current. n High conversion rate: 13v/microsecond
The TL082 is pin-compatible with the standard LM1558 , allowing designers to instantly upgrade n low supply current: 3.6 mA for existing LM1558 and most LM358 designs. n High input impedance: 1012Ω
These amplifiers can be used in applications such as high n low total harmonic distortion av=10,:<0.02%.
Speed integrators, fast D/A converters, sample and hold circuits bw=20hz-20khz circuits and many other circuits that require low input bias voltage - low input bias current, high input impedance, high slew rate and wide frequency band. The device also exhibits low noise with a fast settling time of 0.01%:2µs and bias voltage drift. n Low 1/f noise angle: 50 Hz

Typical Wiring Diagram

Absolute Maximum Ratings (Note 1) Input Voltage Range (Note 3) ±15V
If military/aerospace equipment is required, output short circuit duration - please contact National Semiconductor Sales Office/Distributor for storage temperature range -65°C to +150°C for availability and specifications. lead temperature. (soldering, 10 seconds) 260°C supply voltage ±18V ESD rating to be determined.
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage may cause power consumption to the device (Note 2). Operational ratings indicate an operating temperature range of 0°C to +70°C for normal operation of the device, but specific performance limits are not guaranteed.
The program hints that these devices are op amps with internally trimmed input bias voltages and JFET input devices (BI-FET II). These JFETs have a large reverse breakdown voltage from gate to source and drain, eliminating the need for clamps at the input. Therefore, larger differential input voltages can be easily regulated without increasing the input current. The maximum differential input voltage is independent of the supply voltage. However, neither input voltage should exceed the negative supply, as this will cause large currents to flow, causing damage to the unit

Exceeding the negative common-mode limit at either input will cause a phase reversal at the output and force the amplifier output to a corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output into a high state. Latch-up does not occur in either case, as raising the input into the common-mode range again puts the input stage, thus putting the amplifier in normal operating mode.
Exceeding the positive common-mode limit of one input will not change the phase of the output; however, if both inputs exceed the limit, the amplifier's output will be forced into a high state.
The amplifier will operate with a common-mode input voltage equal to the positive supply; however, gain bandwidth and slew rate may be reduced in this case. The input bias voltage may increase when the negative common mode voltage fluctuates within 3v of the negative supply.
Each amplifier is individually biased by a Zener reference, allowing normal circuit operation on ±6V supplies. Supply voltages lower than these may result in lower gain bandwidth and slew rate.
DS08357-10
The amplifier will drive a 2 kΩ load resistor to ±10 V over the full temperature range of 0 303 C to +70 303 C. However, if the amplifier is forced to drive heavier load currents, there may be an increase in the input offset voltage on the negative voltage swing and eventually reach the effective current limit on the positive and negative swings.
Precautions should be taken to ensure that the power supply to the IC is never reversed in polarity, or that the device is not inadvertently installed backwards in the socket due to an infinite current surge through forward diodes generated within the IC May cause internal conductors to fuse and cause damage to the unit.
Because these amps are jfet and not mosfet input op amps, no special handling is required.
As with most amplifiers, care should be taken with leads, component placement, and power supply decoupling to ensure stability. For example, the resistor from the output to the input should be placed close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. A parallel resistor and capacitor from the device input (usually the inverting input) to AC ground sets the frequency of the magnetic pole. In many cases, the frequency of this pole is much larger than the expected 3db frequency of the closed loop gain, so the effect on the stability margin is negligible. However, if the feedback is extremely less than about 6 times the expected 3db frequency, a lead capacitor should be placed from the op amp's output to the input. The value of the additional capacitor should be such that the rc time constant of this capacitor and its parallel resistance is greater than or equal to the original feedback pole time constant.

C is independent independent ground er2, r4 and r5 control the matching of common mode rejection ratio A = 1400, resistance matching = 0.01%: cmrr = 136 dB Vermont very high input impedance Ultra high CMRR
Typical Applications (continued)

Typical Applications (continued)
All potentiometers are linear cones • Use the LF347 quad for stereo applications Note 8: All controls are flat.
Note 9: Bass and treble boosted, medium flat.
Note 10: Bass and treble, medium flat.
Note 11: Mid-boost, flat bass and treble.
Note 12: Midrange, Bass and Treble levels.