The ADC08831/ADC08832 are 8-bit serial approximate analog-to-digital converters with a 3-wire serial interface and a configurable input multiplexer for two channels. Serial I/O will be connected to a police series microcontroller, PLD, microprocessor, digital signal processor or shift register. Serial I/O is configured to conform to the Microwire serial data exchange standard.

To minimize total power consumption, the ADC08831/ADC08832 automatically enter low-power power mode transitions when they are not executing. The track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion. The analog inputs can be configured in single-ended, differential or pseudo-differential mode. The voltage reference input can be adjusted to allow encoding of small analog voltage ranges with 8-bit resolution.

Function description

Multiplexer addressing

These converters are designed with a built-in sample-and-hold comparator structure that provides a differential analog input for conversion through a successive approximation procedure. The actual converted voltage is always the difference between the specified "+" input terminal and "-" input terminal. The polarity of each pair of input terminals represents the most positive line expected by the converter. If the specified "+" input voltage is less than the "-" input voltage, the converter will respond with an all-zero output code.

A unique input multiplexing scheme has been used to provide multiple analog channels with software configurable single-ended or differential operation. This input flexibility greatly simplifies the analog signal conditioning required for sensor-based data acquisition systems. A single converter package can now handle ground-referenced inputs, differential inputs, and signals with arbitrary reference voltages. A specific input configuration is assigned during the mux addressing sequence before starting a conversion. The MUX address selects which analog input to enable, and whether that input is single-ended or differential. In addition to selecting differential mode, polarity can also be selected. Channel 0 can be selected as a positive input, channel 1 can be selected as a negative input, and vice versa. The MUX addressing code of the ADC08832 illustrates this programmability.

The mux address is transferred into the converter via the di line. Since the ADC08831 contains only one differential input channel with fixed polarity assignment, addressing is not required. Since the input configuration is software controlled, it can be modified as needed before each conversion. One channel can be treated as a single-ended ground-referenced input for one conversion; it can then be reconfigured to be part of another converted differential channel. The analog input voltage of each channel can go from 50mV below ground to 50mV above VCC (typically 5V) without degrading conversion accuracy.

digital interface

One of the most important features of these converters is their serial data link to the control processor. Using the serial communication format provides two very important system improvements. It allows many functions to be contained in a small package, which eliminates the transmission of low-level analog signals by positioning the converter on the analog sensor to transmit high-noise-immune digital data back to the main processor.

To understand the operation of these converters, it is best to refer to the timing diagram and ADC08832 functional block diagram and follow the complete conversion sequence. For clarity, separate timing diagrams are shown for each device.

1. Start a conversion by pulling the CS (chip select) line low. This line must remain low throughout the conversion process. The converter is now waiting for the start bit and its mux assignment word (if applicable).

2. On each rising edge of the clock, the state of the data in (di) row is clocked into the mux address shift register. The start bit is the first logical "1" that occurs on this line (all leading zeros are ignored). After the start bit, the converter expects the next 2 bits to be the mux assignment word.

3. The conversion is about to start when the start bit is moved to the start of the mux register and the input channel is assigned. An interval of 1/2 clock cycle is automatically inserted (if nothing happens) to allow the selected mux channel to settle to the final analog input value. The DI line is disabled at this time. It no longer accepts data.

4. The data out (do) line is now out of tri-state and provides leading zeros for this one clock cycle of the mux.

5. During the conversion process, the output of the sar comparator indicates whether the analog input is greater than

(high) or less than (low) a series of continuous voltages generated from inside the rated capacitor array (first 5 bits) and resistor ladder (last 3 bits). After each comparison, the output of the comparator is sent to the do line on the falling edge of clk. This data is the result of the conversion being shifted out (msb first) and can be read immediately by the processor.

6. After 8 clock cycles, the conversion is complete.

7. The data stored in the successive approximation register is loaded into the internal shift register. Data lsb first is automatically shifted out of do rows after msb first data stream. Then the do line goes low and stays low until cs returns high. The ADC08831 is an exception because its data is output only in msb first format.

8. The di and do wires can be tied together and controlled by the bidirectional processor I/O bits of one wire. This is possible because the di input is only "observed" during the mux addressing interval, while the do line is still in a high impedance state.

Reduce power consumption

The ADC08831 operates up to 2 MHz at about 181 ksps. With a 5V supply, when CS is logic low, it dissipates approximately 1.7 mA or 8.5 mW. The ADC08831 features a low-power mode that minimizes total power consumption. When chip select asserts logic high, some analog circuits and digital logic are pulled into a static, low-power condition. Also, doout, the output driver goes into tri-state mode. To optimize static power consumption, special attention needs to be paid to the digital input logic signals: clk, cs, di. Each digital input has a large CMOS buffer between VCC and GND. A traditional TTL level high (2.4V) is sufficient for each input to read a logic "1". However, there may be a large VIH to VCC voltage difference at each input. Such a voltage difference can cause static power dissipation even when the chip select pin is high and the part is in a low power mode. Therefore, to minimize static power dissipation, it is recommended that all digital input logic levels should be equal to the converter's power supply. Various cmos logic is especially suitable for this application.

The reference pins on the ADC08831 are not affected by power down mode. To reduce the quiescent reference current during non-converting periods, there are two options. First, a low voltage external reference (ie, 2.5V can be used). A shunt reference, such as the LM385-2.5, can be powered by a logic gate that is the inverse of the signal on CS. When cs is high, the reference is closed. As a second option, an external low pass resistance switch can be used.

The ADC08832 is similar to the ADC08831 except that its reference source is VCC. When CS is logic high, the ADC08832 does go into low power mode because the analog and digital logic goes into quiescent current mode. However, the power dissipation from the reference ladder occurs regardless of the signal on CS

reference factor

The voltage vref applied to the reference input of these converters defines the voltage range of the analog input (the difference between vin(max) and vin(min) for the 256 possible output codes). This device can be used in both ratiometric measurement applications and systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving a reference input resistance as low as 2.8kΩ. This pin is the top of the resistor divider string and capacitor array used for successive approximation conversion.

In a ratiometric measurement system, the analog input voltage is proportional to the A/D reference voltage. This voltage is usually the system power supply, so the VREF pin can be tied to VCC (done inside the ADC08832). This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, maintaining the same output code for a given input condition.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between very specific voltage limits. The LM385, LM336 and LM4040 reference diodes are good low current devices for use with these converters.

The maximum value of the reference voltage is limited to the VCC supply voltage. However, the minimum value can be very small (see Typical Performance Characteristics) to allow direct conversion of the sensor output, providing an output span of less than 5V. Due to the increased sensitivity of the converter (1lsb equals vref/256), special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span.

analog input

The most important feature of these converters is that they can be located at an analog signal source and communicate with a control processor with a high noise immunity serial bit stream over a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy at the beginning, or possibly on a large common-mode voltage, there are several words in sequence.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is 1/2 the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

where: where fcm is the frequency of the common mode signal; Vpeak is its peak voltage value; fclk is the A/D clock frequency (1)

In order for a 60Hz common mode signal to produce a 1/4 LSB error (5mV) when the converter is running at 250kHz, it must peak at 6.63V, which will be larger than allowed when it exceeds the maximum analog input limit.

The source resistance limit is important for the DC leakage current into the multiplexer. Bypass capacitors should not be used if the supply resistance is greater than 1kΩ. Worst-case leakage current ±1µA over temperature will result in a 1MV input error with a 1KΩ source resistance. If a high impedance signal source is required, an op amp rc active low pass filter can provide impedance buffering and noise filtering.

sample and hold

The ADC08831/2 provide built-in sample and hold to acquire the input signal. Sample-and-hold can sample the input signal in single-ended or pseudo-differential mode.

Input op amp

When driving an analog input with an op amp, the op amp must settle within the time allowed. To achieve full sample rate, the analog input should be driven with a low impedance source (100Ω) or a high speed op amp such as the LM6142. Higher impedance sources or slower op amps can be easily accommodated, allowing more time for the analog input to settle.

source resistance

The analog input of the ADC08831/2 looks like a 13pF capacitor (CIN) in series with a 300Ω resistor (RON). During each conversion cycle, CIN toggles between the selected "+" and "-" inputs. A large external source resistance will slow down the settling of the input. It is important that the overall RC time constant is short enough to allow the analog input to settle completely.

Board Layout Considerations, Grounding, and Bypassing:

The ADC08831/2 are easy to use with some board layout considerations. They should be used with analog ground planes and single-point ground techniques. The ground pins should be tied directly to the ground plane.

Power pins should bypass the ground plane with surface mount or ceramic capacitors (leads as short as possible). All analog inputs should be directly referenced to a single point ground. Digital inputs and outputs should be shielded and kept away from reference and analog circuits.

optional adjustment

zero error

The offset of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value vin(min) is not grounded. By biasing any VIN (negative) input at that VIN (min) value, the converter can output a 0000 0000 numeric code for this min input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (vin) input. Zero error is the difference between the actual DC input voltage and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.0 0VDC) required to just convert the output digital code from 0000 to 0000 0001 .

full scale

Full-scale adjustment can be done by applying a differential input voltage (1.5 lsb lower from the desired analog full-scale voltage range) and then adjusting the size of the vref input (or vcc for adc08832) of the digital output codes from 1111110 to 1111111.

Adjustment of any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. Apply a vin(+) equal to the desired zero reference voltage plus 1/2 LSB (where 1 LSB = analog span / 256 is used to calculate the LSB of the desired analog span) at the selected "+" input voltage, the zero reference voltage at the corresponding "-" input should then be adjusted to obtain a 00hex to 01hex code transition.

A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by:

where: vmax = high end of analog input range; vmin = low end of analog range (offset zero); (both are ground referenced.)

The vrefin (or vcc) voltage is then adjusted to provide a code change from fhex to ffhex. This completes the adjustment process.

Dynamic performance

Dynamic performance specifications are often useful in applications that require waveform sampling and digitization. Typically, a memory buffer is used to capture a continuous stream of digital output for post-processing. Capturing multiple samples at power 2 (i.e. 102420484096) allows digital analysis of the frequency content of the signal using the Fast Fourier Transform (fft). Depending on the application, further digital filtering, windowing or processing can be applied.

sampling rate

The sampling rate, sometimes called the throughput rate, is the time between repeated samples by the analog-to-digital converter. The sample rate includes conversion time as well as other factors such as mux setup time, acquisition time and interface time delay. Typically, the sample rate is specified in the number of samples taken per second at the maximum analog-to-digital converter clock frequency. Signals with frequencies above the Nyquist frequency (1/2 the sampling rate) will be aliased to frequencies below the Nyquist frequency. To prevent signal degradation, sample at twice (or more) higher than the input signal and/or use a low-pass (anti-aliasing) filter in the front end. Sampling at a much higher rate than the input signal will reduce the antialiasing filter requirements. Some applications require undersampling of the input signal. In this case, one would expect the fundamental to be aliased into the frequency range below the Nyquist frequency. To ensure that the frequency response accurately represents the harmonics of the fundamental, a bandpass filter should be used over the input range of interest.

signal to noise ratio

The signal-to-noise ratio (SNR) is the ratio of the rms value of the fundamental to the sum of the rms values of all non-fundamental signals (excluding harmonics), up to 1/2 the sampling frequency (Nyquist).

total harmonic distortion

Total Harmonic Distortion is the ratio of the root mean square sum of harmonic amplitudes to the fundamental input frequency.

where v1 is the rms amplitude of the fundamental; v2, v3, v4, v5, v6 are the rms amplitudes of the individual harmonics.

In theory, all harmonics are included in the thd calculation, but in practice only the first 6 harmonics make a significant contribution and need to be measured.

For undersampling applications, the input signal should be bandpass filtered (bpf) to prevent out-of-band signals or their harmonics from appearing in the spectral response.

The DC linear transfer function of an analog-to-digital converter tends to affect the main harmonic. Parabolic linear curves tend to produce second-order (even) harmonics, while s-curves tend to produce third-order (odd) harmonics. The magnitude of the DC linearity error is related to the magnitude of the harmonics.

Signal to Noise Ratio and Distortion

The signal-to-noise ratio and distortion ratio (sinad) are the ratios of the rms value of all non-fundamental signals (including noise and harmonics) to the sum of the rms value, up to 1/2 of the sampling frequency (nyquist), not Including direct current.

sinad also depends on the number of quantization levels in the a/d converter used in the waveform sampling process. The higher the quantization level, the lower the quantization noise and theoretical noise performance. The theoretical sinad of the n-bit analog-to-digital converter is: sinad=(6.02n+1.76)db. So for an 8-bit converter, ideal sinad = 49.92 db

significant digits

Effective number of bits (enob) is another specification for quantifying dynamic performance. The equation for enob is as follows:

The effective number of bits describes the cumulative effect of several errors, including quantization, nonlinearity, noise, and distortion.

Spurious free dynamic range

Spurious-free dynamic range (sfdr) is the ratio of the signal amplitude to the amplitude of the highest harmonic or spurious noise component. If the amplitude is full scale, the specification is simply the inverse of the peak harmonic or spurious noise.

application