General Instructions

The AD7893 is a fast 12-bit ADC that operates from a +5V supply and is housed in a small 8-pin Micro DIP and 8-pin SOIC. This section includes a 6μs successive approximation a/d converter, on-chip track/hold amplifier, on-chip clock and high-speed serial interface.

The output data of the AD7893 is provided through the high-speed serial interface port. This two-wire serial interface has a serial clock input and a serial data output, and the external serial clock accesses the serial data of the part.

In addition to traditional dc accuracy specifications such as linearity, full scale, and offset error, the AD7893 specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio. The part accepts an analog input range of ±10 V (AD7893-10), ±2.5 V (AD7893-3), 0 V to +5 V (AD7893-5), or 0 V to +2.5 V (AD7893-2) and operates from a single Operating from a +5 V supply, the typical consumption is only 25 mW.

The AD7893 is fabricated using the Analog Devices Linear Compatible CMOS (LC2MOS) process, a hybrid process that combines precision bipolar circuitry with low-power CMOS logic. The part is available in an 8-pin 0.3-inch wide miniature plastic or hermetic dual-in-line package (mini-dip) and an 8-pin small outline integrated circuit (soic).

Product Highlights

1. Fast 12-bit ADC in 8-pin package

The AD7893 contains a 6μS ADC, a track/hold amplifier, control logic, and a high-speed serial interface, all in an 8-pin package. This saves a lot of space over other solutions.

2. Low power, single power supply operation

The AD7893 is powered by a +5 V supply and consumes only 25 megawatts. This low-power, single-supply operation makes it ideal for battery-powered or portable applications.

3. High-speed serial interface

This section provides high-speed serial data and serial clock lines, allowing a simple two-wire serial interface arrangement.

Term: Signal to Noise Ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fs/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical SNR of an ideal n-bit converter with a sine wave input is: SNR(Noise + Distortion) = (6.02n + 1.76) db, so for a 12-bit converter this is 74 db.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7893, the definitions are as follows:

where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5 and v6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7893 is tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental in dbs.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation of a straight line through the endpoints of the adc transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7893-10)

This is the deviation of the last code transition (01). … 110 to 01. …111) After adjusting for bipolar zero error, start with an ideal 4 × ref in – 1 lsb (AD7893 - 10 ± 10 V range).

Positive Full-Scale Error (AD7893-3)

This is the deviation of the last code transition (01). …110 to 01. …111) After adjusting the bipolar zero error, start with the ideal value (ref in – 1 lsb).

Positive Full-Scale Error (AD7893-5)

This is the deviation of the last code transition (11). …110 to 11. …111) After adjusting for the unipolar offset error, start with the ideal value (2 × ref in – 1 lsb).

Positive Full-Scale Error (AD7893-2)

This is the deviation of the last code transition (11). …110 to 11. …111) After adjusting for the unipolar offset error, start with the ideal value (ref in – 1 lsb).

Bipolar Zero Error (AD7893-10, 10 V; AD7893-3, 2.5 V)

This is the deviation of the mesoscale transition (from 0 to 1) from the ideal 0v (agnd).

Unipolar Offset Error (AD7893-2, AD7893-5)

This is the deviation of the first code transition (00). …000 to 00. ...001) from an ideal 1 LSB.

Negative Full-Scale Error (AD7893-10)

This is the deviation of the first code transition (10). …000 to 10. …001) After adjusting for bipolar zero error, from ideal –4 × reference input +1 LSB (AD7893-10±10 V range).

Negative Full-Scale Error (AD7893-3)

This is the deviation of the first code transition (10). …000 to 10. ...001) After adjusting for bipolar zero error, from ideal (–ref in +1 lsb).

Track/Hold Acquisition Time

Track/Hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 lsb) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a step input change in the input voltage on the VIN input of the AD7893. This means that the user must wait for the duration of the track/hold acquisition time after the transition ends or after the step input is changed to vin before starting another transition to ensure the part is running to specification.

Converter Details

The AD7893 is a fast 12-bit single-supply A/D converter. It provides the user with signal scaling (ad7893-10), track/hold, a/d converter and serial interface logic functions on a microcontroller. The A/D converter portion of the AD7893 consists of a traditional successive approximation converter based on an R-2R ladder structure. The signal scaling on the AD7893-10, AD7893-5, and AD7893-3 allows the part to handle ±10 V, 0 V to +5 V, and ±2.5 V input signals, respectively, while operating from a single +5 V supply. The AD7893-2 accepts an analog input range of 0 V to +2.5 V. This part requires an external +2.5 V reference. The reference input to the part is buffered on-chip.

A major advantage of the AD7893 is that it provides all of the above features in an 8-pin package, which can be an 8-pin mini-dip or SOIC. This offers the user a considerable space saving advantage compared to other solutions. The AD7893 typically consumes only 25 megawatts, making it ideal for battery powered applications.

The conversion input is initiated by a pulse converter on the AD7893. On the rising edge of convst, the on-chip track/hold switches from track to hold mode, starting the conversion sequence. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. The AD7893 has a conversion time of 6 microseconds and a track/hold capture time of 1.5 microseconds. For best performance from the part, read operations should not be performed during a conversion or during the 600 ns period before the next conversion. This allows the part to operate at throughputs up to 117 kHz and meet data sheet specifications. The part can operate at higher throughput rates (up to 133kHz) with slightly reduced performance (see Timing and Control section).

Circuit Description Analog Input Section

The AD7893 is divided into four types: AD7893-10, which handles an input voltage range of ±10 V; AD7893-3, which handles an input voltage range of ±2.5 V; AD7893-5, which handles an input voltage range of 0 V to +5 V; AD7893-2, which handles an input voltage range of ±2.5 V 0 V to +2.5 V input voltage range.

Figure 2 shows the analog input section of the AD7893-10, AD7893-5, and AD7893-3. The analog input range of the AD7893-10 is ±10 V, and the input resistance is typically 33 kΩ. The analog input range of the AD7893-3 is ±2.5 V, and the input resistance is typically 12 kΩ. The input range on the AD7893-5 is 0 V to +5 V, and the input resistance is typically 11 kΩ. This input is benign with no dynamic charging current because the resistor stage is followed by a high input impedance stage amplifier for rail/hold. For the AD7893-10, r1=30 kΩ; r2=7.5 kΩ, r3=10 kΩ. For AD7893-3, r1=r2=6.5 kΩ, r3 is open. For the AD7893-5, r1 and r3 = 5 kΩ, and r2 is open.

For the AD7893-10 and AD7893-3, the designed transcoding occurs on consecutive integer lsb values (ie, 1 lsb, 2 lsb, 3 lsb). ..) The output encoding is two complementary binary, lsb=fs/ 4096 . The ideal input/output transfer functions for the AD7893-10 and AD7893-3 are shown in Table 1.

1FSR is the full-scale range of 20 V (AD7893-10) and =5 V (AD7893-3) with a reference voltage of +2.5 V; 21 LSB = FSR/4096 = 4.883 mV (AD7893-10) and 1.22 mV (AD7893-3) with a reference voltage of +2.5 V; for the AD7893-5, the designed code transitions occur again on consecutive integer lsb values. The output encoding is straight (natural) binary, 1 lsb=fs/4096=5v/4096=1.22mv. The ideal input/output transfer function of the AD7893-5 is shown in Table 2.

The analog input section of the AD7893-2 contains no bias resistors, and the VIN pin drives the input directly to the track/hold amplifier. The analog input range is 0 V to +2.5 V into a high impedance stage with an input current of less than 500 Na. This input is benign and has no dynamic charging current. Again, the designed transcoding happens on consecutive integer lsb values. The output encoding is straight (natural) binary, 1 lsb=fs/4096=2.5v/4096=0.61mv. Table 2 also shows the ideal input/output transfer function of the AD7893-2.

1FSR is full-scale range, AD7893-5 is 5 V, AD7893-2 is 2.5 V, reference is +2.5 V; 21 LSB = FSR/4096, AD7893-5 is 1.22 mV, AD7893-2 is 0.61 mV; reference The voltage is +2.5 V.

track/hold segment

The track/hold amplifier on the analog input of the AD7893 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even though the ADC is at its maximum throughput rate of 117 kHz (ie, the track/hold can handle input frequencies in excess of 58 kHz).

The track/hold amplifier acquires a 12-bit precision input signal in less than 1.5 microseconds. The operation of tracking/holding is basically transparent to the user. At the beginning of a conversion, the track/hold amplifier goes from its track mode to its hold mode (ie, the rising edge of the const). Aperture time track/hold (ie, the delay time between the external convst signal and the track/hold actually entering the hold) is typically 15ns. At the end of the conversion (in convst) the widget returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point.

reference input

The reference input of the AD7893 is a buffered on-chip input with a maximum reference input current of 1µA. The part is specified with a +2.5V reference input voltage. Errors in the reference source will cause gain errors in the AD7893 transfer function and will add to the full-scale errors specified on the part. On the AD7893-10, it will also cause offset errors to be injected in the attenuator stage. Suitable reference sources for the AD7893 include the AD780 and AD680 precision +2.5V references.

Timing and Control Section

Figure 3 shows the timing and control sequence required to obtain optimum performance from the AD7893. Sequentially as shown, a conversion starts on the rising edge of convst and new data from that conversion is available later in the AD7893 6µs output register. Once a read operation has taken place, an additional 600 ns should be allowed to read before the next read, and the rising edge of convst optimizes the track/hold amplifier settings before starting the next conversion. At a serial clock frequency of up to 8.33 MHz, the achievable throughput of this part is 6 microseconds (conversion time) plus 1.92 microseconds (read time) plus 0.6 microseconds (acquisition time). This results in a minimum throughput time of 8.52 microseconds (equivalent to a throughput rate of 117 kHz).

The read operation consists of 16 serial clock pulses to the output shift register of the AD7893. After 16 serial clock pulses, the shift register is reset and the sdata line is asserted three times. If there are more serial clock pulses after the sixteenth clock, the shift register will move after its reset state; however, the shift register will reset again on the falling edge

to ensure that each conversion cycle the part returns to a known state. Therefore, the read operation of the output register should not cross the edge of falling convst as the output shift register will be reset in the middle of the read operation and the data read back to the microprocessor will appear invalid.

The throughput of the component can be improved by reading data during conversion. If data is read during conversion, a throughput time of 6 microseconds (conversion time) plus 1.5 microseconds is achieved. This minimum throughput time of 7.5 microseconds is slightly degraded compared to the AD7893. When the code flicker from the part will also increase (see AD7893 performance section), the signal count to (noise + distortion) may decrease by about 1.5dB.

Because the AD7893 is offered in an 8-pin package to minimize board space, the number of pins available for the interface is very limited. As a result, no status signal is provided from the AD7893 to indicate when the conversion is complete. In many applications this will not be an issue as data can be read from the ad7893 during or after the transition; however, applications that want to get the best performance from the ad7893 must ensure that the 600 ns during transition or before the rise No data reads will occur during this time. the edges of the convs. This can be achieved in two ways. The first is to ensure that in software, the read operation does not begin until 6 microseconds after the rising edge of convst. This can only be done if the software knows when to issue the convst command. The second scheme is to use the convst signal as the conversion start signal and interrupt signal. The easiest way to do this is to generate a square wave signal for the convst with high and low multiples of 6 microseconds (see Figure 4). Conversions are initiated on the rising edge of convst. The falling edge of convst occurs 6 microseconds later and can be used as an active low or falling edge triggered interrupt to tell the processor to read data from the AD7893. If the read operation completes the converter edge 600 ns before the rise, the AD7893 will operate within specification.

This scheme limits throughput to a minimum of 12 microseconds; however, depending on the microprocessor's response time to interrupts and the time the processor takes to read data, this may be the fastest the system can run. Anyway, the convst signal doesn't have to have a 50:50 duty cycle. This can be tailored to optimize component throughput for a given system. Alternatively, the convst signal can be used as a normal narrow pulse width. The rising edge of convst can be used as an active high or rising edge triggered interrupt. Then, a software delay of 6 microseconds can be implemented before reading data from the part.

serial interface

The serial interface of the AD7893 consists of only two wires, the serial clock input (SCLK) and the serial data output (SData). This enables an easy-to-use interface to most microcontrollers, DSPs and shift registers.

Figure 5 shows the timing diagram of the AD7893 read operation. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked from the SData line on the rising edge of this clock and is valid on the falling edge of SCLK. 16 clock pulses must be given to the part to get the full conversion result. The AD7893 provides four leading zeros followed by a 12-bit conversion result starting with msb (db11). The last data bit clocked on the last rising clock edge is lsb (db0). On the sixteenth falling edge of SCLK, the SData line is disabled (three states). After the last bit has been clocked, the SCLK input should return low and remain low until the next serial data read operation. If there is an additional clock pulse after the sixteenth clock, the AD7893 will start over from its output register outputting data, and the data bus is no longer three-state even if the clocks are stopped. If the serial clock is stopped before the next falling edge of convst, the AD7893 will continue to operate normally and the output shift register will reset on the falling edge of convst; however, the SCLK line must be low when convst goes low so that Correctly reset the output shift register.

The serial clock input does not have to be continuous during serial read operations. Sixteen bits of data (four leading zeros and a 12-bit conversion result) can be read several bytes from the AD7893; however, the SCLR input must be held low between two bytes.

Typically, the output registers are updated at the end of the conversion. If a serial read from the output register is in progress when the conversion is complete, the update of the output register is delayed. In this case, the output registers are updated when the serial read is complete. If the serial read does not complete before the next falling edge of convst, the output register is updated on the falling edge of convst and the output shift register count is reset. In the application, the data read has started but not completed before the drop. At the edge of the convst, the user must provide a convst pulse width greater than 1.5 microseconds to ensure that the AD7893 is properly set before starting the next conversion. A normal pulse width of minimum 50 ns applies to convst in applications where the output is updated at the end of a conversion or at the end of a serial read completed 1.5 µs before the rising edge of convst.

The AD7893 counts the serial clock edges to know which bit in the output register should be placed on the SData output. To make sure the part doesn't get out of sync, reset the serial clock counter on the falling edge of the convst input, provided the sclr line is low. The user should ensure that there is no falling edge on the convst input during serial data read operations.

Microprocessor/Microcontroller Interface

The AD7893 provides a two-wire serial interface that can be used to connect to the serial ports of DSP processors and microcontrollers. Figures 6 through 9 show the AD7893 interfacing with many different microcontrollers and digital signal processors. The AD7893 accepts an external serial clock, so in all the interfaces shown here, the processor/controller is configured as the master, providing the serial clock, and the AD7893 is configured as the slave in the system.

AD7893-8051 interface

Figure 6 shows the AD7893 and 8XC51 microcontrollers. The 8XC51 is configured in its Mode 0 serial interface mode. The figure shows the simplest form of the interface, where the AD7893 is the only part connected to the serial port of the 8XC51, so serial read operations do not need to be decoded. It also does not specify monitoring when a conversion is complete on the AD7893.

Either of these two tasks can be easily accomplished with minor modifications to the interface. To chip select the AD7893 in a system where multiple devices are connected to the 8XC51 serial port, a port bit configured as an output of one of the 8XC51 parallel ports can be used to turn the AD7893's serial clock on or off. A simple sum function on this port bit and the 8XC51's serial clock will provide this functionality. The port bit should be high to select the AD7893, and low if not selected.

To monitor conversion times on the ad7893, one such scheme, as described earlier, can use convst. This can be achieved in two ways. One is to connect the convst line to another parallel port bit that is configured as an input. This port bit can then be polled to determine when the conversion is complete. Another way is to use an interrupt driven system, in which case the convst line should be connected to the int1 input of the 8xc51.

The serial clock frequency from the 8XC51 is limited to significantly lower than the allowable input serial clock frequency at which the AD7893 can operate. So the transition from this part is actually longer than this part. This means that the AD7893 cannot run at its maximum throughput when used with the 8XC51.

AD7893-68 HC11 interface

The interface circuit between AD7893 and 68HC11 microcontroller is shown in Figure 7. For the interface shown, the 68HC11 SPI port is used and the 68HC11 is configured in its microcontroller mode. The 68HC11 is configured in master mode with its cpol bit set to logic zero and its cpha bit set to logic one. As with the previous interface, this diagram shows the simplest form of the interface, where the AD7893 is the only part connected to the serial port of the 68hc11, so serial read operations do not need to be decoded. It also does not specify monitoring when a conversion is complete on the AD7893.

Again, either of these two tasks can be easily accomplished with minor modifications to the interface. To chip select the AD7893 in a system where multiple devices are connected to the 68HC11 serial port, a port bit configured as an output of one of the 68HC11 parallel ports can be used to turn the AD7893's serial clock on or off. A simple function on this port bit and the 68HC11's serial clock will provide this function. The port bit should be high to select the AD7893, and low if not selected.

In order to monitor the transition time on the ad7893, one such scheme. Can be used as described in the previous convst interface. This can be achieved in two ways. One is a convst line linked to another parallel port bit configured as an input. This port bit can then be polled to determine when the conversion is complete. Another way is to use an interrupt driven system, in which case the transition line should be connected to the IRQ input of the 68HC11.

The serial clock rate of the 68HC11 is limited to significantly less than the allowable input serial clock frequency at which the AD7893 can operate. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that when the AD7893 is used with the 68HC11, it cannot operate at maximum throughput.

AD7893–ADSP-2105 interface

The interface circuit digital signal processor of ad7893 and adsp-2105 is shown as in Fig. 8. In the interface shown, the RFS1 output from the ADSP-2105's SPORT1 serial port is used to gate the ADSP-2105's serial clock (SCLK1) before it is applied to the AD7893's SCLK input. The RFS1 output is configured to run high. The interface ensures that the clock to the AD7893's serial clock input is discontinuous, only 16 serial clock pulses are provided, and that the AD7893's serial clock line remains low between data transfers. The SData line from the AD7893 is connected to the DR1 line of the ADSP-2105 serial port.

The timing relationship between the sclk1 and rfs1 outputs of the adsp-2105 results in a delay of up to 25ns between the rising edge of sclk1 and the rising edge of active high RFs1. It is also required that the data be set 10 ns before the falling edge of SCLK1 for the ADSP-2105 to read correctly. The data access time of the AD7893 is 50ns from the rising edge of its SCLK input. Assuming a propagation delay of 10ns through the external and gate, the high time of the sclk1 output of the adsp-2105 must be ≥(50+25+10+10)ns, which is ≥95ns. This means that the serial clock frequency that can be used by the interface of Figure 13 is limited to 5.26mhz.

Another option is to configure the adsp-2105 to accept an external serial clock. In this case, provide an external discontinuous serial clock that drives the serial clock input of the adsp2105 and ad7893. In this scheme, the adsp-2105 limits the serial clock frequency to 5mhz. To monitor conversion times on the AD7893, the scheme outlined in the previous interface to convst can be used. This can be achieved by connecting the convst line directly to the IRQ2 input of the ADSP-2105.

AD7893–DSP56000 interface

Figure 9 shows the interface circuit between the AD7893 and the DSP56000 DSP processor. The DSP5600 is configured for normal mode asynchronous operation with gated clocks. It is also set to a 16-bit word and the gated serial clock is generated by the DSP56000 and displayed on the SC0 pin. The sc0 pin should be configured as an output by setting bit scd0 to 1. In this mode, the DSP56000 provides 16 serial clock pulses to the AD7893 in a serial read operation. The DSP56000 assumes that there is valid data on the first falling edge of SCK, so the interface is only two-wire, as shown in Figure 9.

To monitor conversion times on the AD7893, a scheme as outlined in the previous example of the convst interface can be used. This can be achieved by connecting the convst directly to the IRQA input of the DSP56000.

AD7893 performance linearity

The linearity of the AD7893 is determined by the on-chip 12-bit D/A converter. This is a piecewise DAC that is laser trimmed to 12-bit integral linear and differential linear. Typical relative numbers for parts are ±1/4 LSB, while typical DNL errors are ±1/2 LSB.

noise

In a/d converters, noise appears as code uncertainty in DC applications and as a noise floor (eg in fft) in AC applications. In a sampling A/D converter like the AD7893, from dc to 1/2 the sampling frequency, all information about the analog input is present in baseband. The input bandwidth of the track/hold exceeds the Nyquist bandwidth; therefore, in applications where such signals are present, an antialiasing filter should be used to remove unwanted signals above fs/2 from the input signal.

Figure 10 shows a histogram of 8192 DC input conversions using the AD7893. The analog input is set at the center of the transcoding. The timing and control sequence used is shown in Figure 3, where the performance of the ADC is maximized. As can be seen, almost all the codes appear in one output bin, which shows that the ADC has very good noise performance. The rms noise performance of the AD7893-2 in the figure above is 87µV. Since the analog input range and LSB size on the AD7893-10 is eight times that of the AD7893-2, the same output code distribution results in an output rms noise of 700 μV for the AD7893-10.

The data shown in Figure 11 is the same as the data shown in Figure 10, except in this case, the output data read for the device occurs during the conversion. This injects noise into the die when making bit decisions; this increases the noise produced by the AD7893. The histogram plot of 8192 transitions of the same dc input now shows a larger spread of the code as the rms noise of the AD7893-2 increases to 210µV. This effect will vary depending on where the serial clock edge of the bit trial of the conversion process occurs. Depending on the relationship between the serial pedestal edge and the bit trial point, it is possible to achieve the same level of performance when reading during conversion as when reading after conversion.

Dynamic performance

With a conversion and acquisition time of 7.5 microseconds, the AD7893 is ideal for wideband signal processing applications. These applications require information about the effect of the ADC on the spectral content of the input signal. Signal-to-noise ratio, total harmonic distortion, peak harmonic or spurious noise, intermodulation distortion are specified. Figure 12 shows a typical FFT plot of a 10 kHz, 0 V to +2.5 V input operating at a 102.4 kHz sample rate after being digitized by the AD7893-2. The signal-to-noise ratio is 71.5db, and the total harmonic distortion is -83db.

significant digits

The formula for signal-to-noise ratio (noise + distortion) (see the Terminology section) is related to the resolution or number of bits of the converter. The rewritten formula gives a measure of performance in significant digits (n): n = (signal-to-noise ratio-1.76)/6.02; where snr is the signal-to-noise ratio.

The effective number of bits of a device can be calculated from the ratio of its measured signal to (noise + distortion). Figure 13 shows a typical plot of effective bits versus frequency for the AD7893-2 from DC to F samples/2. The sampling frequency is 102.4khz. The figure shows that the ad7893 converts an input sine wave of 51.2khz to an effective number of digits of 11, which corresponds to a signal with a (noise + distortion) level of 68 dB.