Z8018X Microprocessor Operation Describes the features, general description, pin description, block diagram, registers, and details of operating modes of the Z8018X microprocessor.
The software architecture provides the instruction set and CPU registers for the Z8018X microprocessor.
DC Characteristics shows the DC parameters and absolute maximum ratings for the Z8x180 MPU.
AC Characteristics shows the AC parameters of the Z8018X microprocessor.
Timing Diagrams contains timing diagrams and standard test conditions for the Z8018X microprocessor.

Z80180, Z8S180, Z8L180 MPU operating characteristics Operating frequency of 33 MH On-chip MMU supports extended address space Two DMA channels On-chip wait state generator Two Universal Asynchronous Receiver/Transmitter (UART) channels Two 16-bit timer channels On-chip interrupts Controller On-Chip Clock Oscillator/GE Generator Clock Serial I/O Port Zilog Z80 CPU Compatible Code Extension Instructions General Description
Z80180, Z8S180, Z8L180 (Z8X180) is an 8-bit microprocessor based on microcode execution unit and advanced CMOS manufacturing technology, which has the advantages of reduced system cost and low-power operation, while having higher performance, and is compatible with Extensive industry standard software written around the Zilog Z8X CPU. Through increased operating frequency, reduced instruction execution time, enhanced instruction set and on-chip memory management unit (MMU), can address up to 1MB of memory.
System cost is reduced by combining several key system functions on the chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Various glue functions such as dynamic ram refresh control, wait state generator, clock oscillator and interrupt controller are also included on the chip.
Not only does the Z8X180 consume low power during normal operation, but processors equipped with the Z8S180 and Z8L180 class of processors also offer two operating modes designed to further reduce power consumption significantly. Sleep mode reduces power consumption by putting the CPU in a stopped state, which consumes less current while the on-chip I/O devices are still working. System Stop mode puts both the CPU and on-chip peripherals in a stopped state, further reducing power consumption.
When combined with other cmos vlsi devices and memories, the z8x180 provides an excellent solution for system applications requiring high performance and low power operation.
Pin-out package descriptions for other Z8x180-based products are included in their respective product specifications.
Block diagram shared across all configurations of the Z8x180.

Pin Description
A0- A19 address bus (output, high level, 3 states). a0-a19 form a 20-bit address bus. The address bus provides addresses for memory data bus exchanges up to 1 MB, and I/O data bus exchanges up to 64 K. The address bus enters a high impedance state during reset and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (TOUT, selected as address output at reset), address line A19 is not available in the DIP version of the Z8x180.
Elf. Bus ack (output, active low). busack indicates that the requesting device, the mpu address and data bus, and some control signals have entered a high impedance state.
Blake bus request (input, active low). External devices such as DMA controllers use this input to request access to the system bus. This request has higher priority than NMI and is always recognized at the end of the current machine cycle. This signal prevents the CPU from executing further instructions and places the address and data buses and other control signals in a high impedance state.
Elf. Asynchronous clocks 0 and 1 (bidirectional, active high). These pins are the transmit and receive clocks for the asci channel. cka0 is multiplexed with dreq0, and cka1 is multiplexed with tend0.
CKS! Serial clock (bidirectional, high). This line is the clock for the CSIO channel.
clock (φ) system clock (output, high). The output is used as a reference clock for microprocessors and external systems. The frequency of this output is equal to half the frequency of the crystal or input clock.
CTS0.CTS1. Clear to send 0 and 1 (input, active low). These lines are the modem control signals for the ASCI channel. CTS1 is multiplexed with RX.

D0-D7. Data bus (bidirectional, high, tri-state). d0-d7 form an 8-bit bidirectional data bus for transferring information between input/output and memory devices. The data bus enters a high impedance state during reset and external bus acknowledge cycles. DCD0. Data carrier detect 0 (input, active low). This input is the programmable modem control signal for ASCI channel 0. Drake, Drake. DMA requests 0 and 1 (input, low). dreq is used to request a DMA transfer from an on-chip DMA channel. The dma channel monitors these inputs to determine when the external device is ready for a read or write operation. These inputs can be programmed for level or edge sensing. dreq0 is multiplexed with cka0. e. Enable clock (output, active high). Synchronizer cycle clock output during bus transactions. Exstar external clock/crystal (input, high). Crystal oscillator connection. When not using a crystal, an external clock can be input to the Z8x180 on this pin. This input is Schmitt triggered. stop. stop/sleep state (output, low). This output is asserted after the CPU executes a HALT or SLP instruction and waits for a non-maskable or maskable interrupt before operation resumes. halt is also used with the m1 and st signals to decode the state of the cpu machine cycle. In 0. Mask interrupt request 0 (input, low). This signal is generated by an external I/O device. The CPU executes this request at the end of the current instruction cycle as long as the NMI and BUSREQ signals are inactive. The CPU acknowledges the interrupt request through an interrupt acknowledgement cycle. During this cycle, both the m1 and iorq signals become active. It1, It2. Masks interrupt requests 1 and 2 (input, low). This signal is generated by an external I/O device. The CPU accepts these requests at the end of the current instruction cycle, as long as the NMI,

BUSREQ and INT0 signals are not active. The CPU acknowledges these interrupt requests with interrupt acknowledgement cycles. Unlike the acknowledgement of int0, neither the m1 nor the iorq signal will become active during this cycle. Elf. I/O request (output, active low, 3 states). IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. The IORQ is also generated along with M1 during the acknowledgement of the INT0 input signal to indicate that the interrupt response vector can be placed on the data bus. This signal is similar to the IOE signal of the Z64180. M1. Machine cycle 1 (output, active low). m1 together with mreq indicates that the current cycle is the opcode fetch cycle of instruction execution. m1 together with iorq indicates that the current cycle is used for interrupt acknowledgment. It is also used in conjunction with the halt and st signals to decode the state of the CPU machine cycle. This signal is similar to the LIR signal of the Z64180. MReq memory request (output, active low, 3 states). mreq indicates that the address bus reserves effective addresses for memory read or memory write operations. This signal is similar to the ME signal of the Z64180. NMI. Non-maskable interrupt (input, negative edge triggered). nmi has higher priority than int and is always recognized at the end of the instruction, regardless of the state of the interrupt enable flip-flop. This signal forces the CPU to continue execution at position 0066H.RD.READ (output active low, 3 state). rd indicates that the cpu wants to read data from memory or an i/o device. Addressing I/O or memory devices must use this signal to transfer data onto the CPU data bus. rFSH. refresh(output, activity low). rfsh together with mreq indicates that the current cpu machine cycle and the contents of the address bus must be used for the refresh of dynamic memory. The lower 8 bits of the address bus (A7–a0) contain the refresh address. This signal is similar to the reference signal of the Z64180.

Programmable reload timer (PRT, 2 channels) Clock serial I/O (CSIO) channel.
Other Z8x180 family members (such as Z80183, Z80S183, Z80185/ 195 ) include other peripherals in addition to these modules and are included in the relevant product specification Clock Generator This logic generates the system clock from an external crystal or clock input. The external clock is split by two and provided to internal and external devices.
Bus Status Controller This logic performs all status and bus control activities related to the CPU and some on-chip peripherals. This includes wait state timing, reset cycles, DRAM refreshes, and DMA bus swaps.
Interrupt Controller This block monitors and prioritizes various internal and external interrupts and traps to provide proper responses from the CPU. To maintain compatibility with the Z80 CPU, three different interrupt modes are supported.
memory management unit
The MMU allows the user to map the memory used by the CPU (logically only 64K) into the 1MB addressing range supported by the Z8x180. MMU object code is organized for compatibility with z80 CPUs while providing access to extended memory spaces. This capability is achieved through the use of an efficient common area library.

CPU
The CPU is microcoded to provide object code cores compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many instructions to execute in fewer clock cycles.
DMA controller
The dma controller provides high-speed transfers between memory and i/o devices. Supported transfer operations are memory to memory, memory to/from I/O, and I/O to I/O. The supported transfer modes are Request, Burst, and Loop Steal. DMA transfers can access the full 1MB addressing range, block lengths up to 64KB, and can span 64K boundaries.
Asynchronous serial communication interface
asci logic provides two independent full duplex uarts. Each channel includes a programmable baud rate generator and modem control signals. asci channels can also support multiprocessor communication formats.
Programmable Reload Timer (PRT)
This logic consists of two independent channels, each containing a 16-bit counter (timer) and count reload register. The time base of the counter is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides optional output to allow waveform generation.
Clocked Serial I/O (CSIO) The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for a simple high-speed data connection to another microprocessor or microcomputer.