General Instructions

The AD7862 is a high speed, low power, dual 12-bit A/D converter powered by a +5V supply. This section contains two 4µs successive approximation ADCs, two track/hold amplifiers, an internal +2.5v reference, and a high-speed parallel interface. There are four analog inputs grouped into two channels (a and b) selected by the a0 input. Each channel has two inputs (V&VOR V&V) that can be sampled and converted at the same time, thereby preserving the relative phase information of the signals on the two analog inputs. The part accepts analog input ranges of ±10 V (AD7862-10), ±2.5 V (AD7862-3), and 0–2.5 V (AD7862-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage.

A single conversion start signal (convst) puts both tracks/holds on hold simultaneously and initiates conversion on both inputs. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The first read after the conversion accesses the result from either va1 or vb1, while the second read accesses the result from either va2 or vb2, depending on whether the muxer selects a0 to be low or high, respectively. Data goes through a 12-bit parallel data bus with standard CS and RD signals. In addition to traditional DC accuracy specifications such as linearity, full scale, and offset error, this section specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

The AD7862 is fabricated using the Analog Devices Linear Compatible CMOS (LC2MOS) process, a hybrid process that combines precision bipolar circuitry with low-power CMOS logic. Available in 28 lead SSOP, SOIC and DIP.

Product Highlights

1. The AD7862 has two complete ADC functions, allowing simultaneous sampling and conversion of two channels. Each adc has a 2 channel input mux. After the conversion is initiated, the conversion result for both channels is 3.6 microseconds.

2. The AD7862 is powered by a +5 V power supply with a typical power consumption of 60 mW. An automatic power-down mode, where the part goes into a power-down state after a conversion is complete, and "wakes up" before the next conversion cycle, makes the AD7862 ideal for battery-powered or portable applications.

3. This part provides a high-speed parallel interface for easy connection with microprocessors, microcontrollers and digital signal processors.

4. There are three versions of this part with different analog input ranges. The AD7862-10 provides a standard industrial input range of ±10 V; the AD7862-3 provides a common signal processing input range of ±2.5 V; and the AD7862-2 can be used in unipolar 0 V–+2.5 V applications.

5. This section features a very tight aperture delay match between the two input sample-and-hold amplifiers.

Term: Signal to Noise Ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the sum of the rms of all non-fundamental signals up to half the sampling frequency (f/2), excluding DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio (noise + distortion) of an ideal N-bit converter with a sine wave input is given by:

So for a 12-bit converter, that's 74 dB.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7862, the definitions are as follows:

where v is the rms amplitude of the fundamental and v1, v2, v3, v4 and v5 are the rms amplitudes of the second to fifth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7862 is tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs.

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. It is measured by applying a full-scale 100 kHz sine wave signal to each of the four inputs separately. These, in turn, reference each of the other three channels whose inputs are grounded, and measure the adc outputs to determine the level of crosstalk from the other channels. The numbers given are the worst case for all four channels.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation of a straight line through the endpoints of the adc transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive full-scale error

This is the deviation of the last code transition (01). …110 to 01. …111) After adjusting for bipolar offset error, from ideal 4 × VREF – 3/2 LSB (AD7862-10 ±10 V range) or VREF – 3/2 LSB (AD7862-3, ±2.5 V range).

Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V)

This is the deviation of the last code transition (01). …110 to 01. …111) After adjusting for unipolar offset error, start with ideal VREF – 3/2 LSB.

Bipolar Zero Error (AD7862-10, 10 V, AD7862-3, 2.5 V)

This is the deviation of mesoscale transitions (all 1s to all 0s) from ideal agnd – 1/2 lsb.

Unipolar Offset Error (AD7862-2, 0 V to 2.5 V)

This is the deviation of the first code transition (00). …000 to 00. ...001) from ideal agnd + 1/2 lsb.

Negative full-scale error (AD7862-1610V; AD7862-3, 62.5V)

This is the deviation of the first code transition (10). …000 to 10. …001) After adjusting for bipolar zero error, start from ideal –4 × VREF+1/2 LSB (AD7862-10 ±10 V range) or –VREF+1/2 LSB (AD7862-3, ±2.5 V range) .

Track/Hold Acquisition Time

The track/hold acquisition time is the time it takes for the track/hold amplifier output to reach its final value, ±1/2 LSB after the end of the conversion (the point at which the track/hold returns to track mode). It is also suitable for cases where there is a change in the selected input channel, or where there is a step input change in the input voltage applied to the selected vax/bx input of the AD7862. This means that the user must wait for the duration of the track/hold acquisition time before starting another conversion after the conversion ends or after the channel change/step input changes to vax/bx to ensure the part is operating to specification.

Converter Details

The AD7862 is a high speed, low power, dual 12-bit A/D converter powered by a +5V supply. This section contains two 4µs successive approximation ADCs, two track/hold amplifiers, an internal +2.5v reference, and a high-speed parallel interface. There are four analog inputs grouped into two channels (a and b) selected by the a0 input. Each channel has two inputs (va1 & va2 or vb1 & vb2) that can be sampled and converted at the same time, thereby preserving the relative phase information of the signals on the two analog inputs. The part accepts analog input ranges of ±10 V (AD7862-10), ±2.5 V (AD7862-3), and 0 V–2.5 V (AD7862-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage. AD7862 has two working modes, high sampling mode and automatic sleep mode. After the conversion is completed, the part automatically enters the sleep state. These modes are discussed in detail in the Timing and Control section.

The conversion input is initiated by a pulse converter on the AD7862. On the falling edge of convst, both on-chip tracks/holds are held simultaneously and the conversion sequence begins on both channels. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The first read after the conversion accesses the result from either va1 or vb1, while the second read accesses the result from either va2 or vb2, depending on whether the muxer selects a0 to be low or high, respectively. Read data goes through a 12-bit parallel data bus with standard CS and rd signals.

In high sampling mode, the AD7862 has a conversion time of 3.6 microseconds (6 microseconds in auto-sleep mode) and a track/hold acquisition time of 0.3 microseconds. For best performance from the part, read operations should not occur during a conversion or during the 300 ns before the next conversion. This allows the part to operate at throughputs up to 250 kHz and meet data sheet specifications.

track/hold segment

The track/hold amplifier on the AD7862 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even though the ADC is operating at its maximum throughput rate of 250 kHz (ie, the track/hold can handle input frequencies in excess of 125 kHz).

The track/hold amplifier acquires the input signal to 12-bit accuracy in less than 400 ns. The operation of tracking/holding is basically transparent to the user. Dual Rail/Hold Amplifier on const falling edge. Track/Hold Aperture Time

(ie, the delay time between the external convst signal and the track/hold that actually goes into the hold) is typically 15ns, and more importantly, is a good match between the two tracks/holds on one device, and on the device are also well matched. This allows relative phase information between different input channels to be accurately preserved. It also allows multiple ad7862s to sample more than two channels simultaneously. At the end of the conversion, the part returns to its tracking mode. The acquisition time for the track/hold amplifier begins at this point.

Reference chapter

The AD7862 includes a single reference pin, labeled VREF, which provides access to the part's own +2.5 V reference voltage, and can also be connected to an external +2.5 V reference to provide a reference voltage source for the part. This part is specified as a +2.5 V reference. Errors in the reference source will cause gain errors in the AD7862 transfer function and will add to the full-scale errors specified on the part. On the AD7862-10 and AD7862-3, it will also cause offset errors to be injected in the attenuator stage.

The AD7862 includes an on-chip +2.5V reference. To use this reference as a reference source for the AD7862, simply connect a 0.1µf disc ceramic capacitor from the VREF pin to AGND. The voltage appearing on this pin is buffered internally before being applied to the ADC. If the reference needs to be used external to the AD7862, it should be buffered because the part has a FET switch in series with the reference output, resulting in a nominal 3 kΩ source impedance for this output. At 25°C, the internal reference has a tolerance of ±10 mV, a typical temperature coefficient of 25 ppm/°C, and a maximum temperature error of ±25 mV.

If the application requires a reference with tighter tolerances or the AD7862 needs to be used with a system reference, the user can choose to connect an external reference to this VREF pin. The external reference will effectively drive the internal reference and provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with a maximum input current of ±100µA. Suitable references for the AD7862 include the AD680, AD780, and the REF43 precision +2.5 V reference.

Circuit Description Analog Input Section

The AD7862 is divided into three types: AD7862-10, which handles an input voltage range of ±10 V; AD7862-3, which handles an input voltage range of ±2.5 V; and AD7862-2, which handles an input voltage range of 0 V to +2.5 V.

Figure 3 shows the analog input section of the AD7862-10 and AD7862-3. The analog input range of the AD7862-10 is ±10 V, and the input resistance is typically 33 kΩ. The analog input range of the AD7862-3 is ±2.5 V, and the input resistance is typically 12 kΩ. This input is benign with no dynamic charging current because the resistive stage is followed by the high input impedance stage of the track/hold amplifier. For the AD7862-10, r1 = 30 kΩ, r2 = 7.5 kΩ, and r3 = 10 kΩ. For AD7862-3, r1=r2=6.5 kΩ, r3 is open.

For the AD7862-10 and AD7862-3, the designed transcoding occurs on consecutive integer lsb values (ie, 1 lsb, 2 lsb, 3 lsb). ..) The output encoding is two complementary binary, lsb=fs/4096. The ideal input/output transfer functions for the AD7862-10 and AD7862-3 are shown in Table 1.

1FSR full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with a reference voltage of +2.5 V.

21 LSB=FSR/4096=4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with a reference voltage of +2.5 V.

The analog input section of the AD7862-2 contains no bias resistors, and the VAX/BX pins directly drive the inputs of the multiplexer and track/hold amplifier circuits. The analog input range is 0v to +2.5v in a high impedance stage with an input current of less than 500nA. This input is benign and has no dynamic charging current. Again, the designed transcoding happens on consecutive integer lsb values. The output encoding is straight (natural) binary, 1 lsb=fs/4096=2.5v/4096=0.61mv. Table II shows the ideal input/output transfer function for the AD7862-2.

1FSR is the full-scale range, 2.5 V for the AD7862-2 with VREF=+2.5 V; 21 LSB=FSR/4096, 0.61 mV for the AD7862-2, VREF=+2.5 V.

Offset and full scale adjustment

In most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. With AC coupling, offset errors in the analog domain can be eliminated. The full-scale error effect is linear and should not cause a problem as long as the input signal is within the full dynamic range of the ADC. Some applications always require the input signal to span the entire analog input dynamic range. In this application, the offset and full-scale errors must be adjusted to zero.

Figure 4 shows a circuit that can be used to adjust the offset and full-scale error on the AD7862 (VA1 on the AD7862-10 version is for example purposes only). When adjustment is required, the offset error must be adjusted before the full-scale error. This is achieved by trimming the offset of the op amp driving the AD7862's analog input when the input voltage is below 1/2 lsb of analog ground. The trimming procedure is as follows: Apply a voltage of -2.44 mV (–1/2 lsb) at VA1 (see Figure 4) and adjust the op amp offset voltage until the ADC output code flashes between 1111 1111 1111 and 0000 0000 0000 0000 .

Gain error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure in both cases is as follows:

Positive full scale adjustment

A voltage of +9.9927 V (fs/2–3/2 lsbs) was applied at VA1. Adjust r2 until the adc output code flashes between 0111111111110 and 0111111111.

Negative full scale adjustment

Apply a voltage of -9.9976 V (–fs + 1/2 lsb) at VA1 and adjust R2 until the ADC output code flashes between 1000 0000 and 1000 0000 0001.

An alternative to adjusting the full-scale error in systems using an external reference is to adjust the voltage at the vref pin until the full-scale error of any channel is adjusted. Good full-scale matching of the channels will ensure small full-scale errors for the other channels.

time and control

Figure 5a shows the timing and control sequence required to obtain optimum performance (mode 1) from the AD7862. In the sequence shown, starting the transition on the falling edge of the first will put both tracks/holds in hold simultaneously, and new data from this transition is available in the output register of the ad7862 3.6µs following. The busy signal indicates the end of the conversion, at which point the conversion results of both inputs can be read. Then start the second conversion. If the multiplexer selects a0 low, the first converted first and second read pulses access the results from channel a (va1 and va2, respectively). The third and fourth read pulses access the results from channel b (vb1 and vb2 respectively) after the second transition and a0 high. The A0 state can change anytime after convst rises, that is, at the edge of convs 400 ns before the next fall. Reading data from the part via a 12-bit parallel data bus with standard CS and RD signals, i.e., a read operation consists of a negative-going pulse on the CS pin and two negative-going pulses on the RD pin (while CS is low) , to access the two 12-bit results. Once the read operation is performed, an additional 300 ns should be allowed to optimize the track/hold amplifier settings before starting the next conversion on the next falling edge of convst. When the internal clock frequency is at its maximum (3.7 MHz not accessible externally), the achievable throughput of the part is 3.6 µs (conversion time) plus 100 ns (read time) plus 0.3 µs (acquisition time). This results in a minimum throughput time of 4 microseconds (equivalent to a throughput rate of 250 kHz).

Read options, in addition to the read operations described above and shown in Figure 5a, other combinations of cs and rd can result in different channels/inputs being read in different combinations. Appropriate combinations are shown in Figures 5b to 5d.

Operating mode

Mode 1 Operation (High Sampling Performance) The timing diagram in Figure 5a is used to run Mode 1, with the falling edge of convst starting the conversion and placing the track/hold amplifier in its hold position mode. This falling edge of convst also causes the busy signal to go high to indicate that a conversion is in progress. When the conversion is complete, the busy tone signal goes low for a maximum of 3.6µs after the falling edge of convst, and new data from this conversion is available in the output latch of the AD7862. Read operations access this data. If the multiplexer selects a0 low, the first converted first and second read pulses access the results from channel a (va1 and va2, respectively). The third and fourth read pulses, transitioning and a0 high after the second, access the results of channel B (vb1 and vb2 respectively). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. These data read operations consist of a negative-going pulse on the CS pin and a negative-going pulse on the RD pin; repeated twice will access two 12-bit results. For the fastest throughput rate (with an internal clock of 3.7 MHz), a read operation takes 100 nanoseconds. The read operation must complete at least 300 ns before the falling edge of the next convst, which gives a total of 4 microseconds for the entire throughput time (equivalent to 250 kHz). This mode of operation should be used for high sampling applications.

Mode 2 operation (automatic sleep after transition)

The timing diagram in Figure 6 is for optimal performance in operating mode 2, after a transition, once busy goes low, the part automatically goes into sleep mode and "wakes up" before the next transition. This is done by holding the transition low at the end of the second conversion and high at the end of the second conversion for Mode 1 operation. The operation shown in Figure 6 shows how to access data from channels A and B, followed by automatic sleep mode. It is also possible to set the timing so that data is only accessed from either channel A or channel B (see the "Read Options" section on the previous page) and then enter auto-sleep mode. The rising edge const "wakes up" the character. When using the external reference, the wake-up time is 2.5 microseconds; when using the internal reference, the wake-up time is 5 milliseconds, at which point the track/hold amplifiers go into their hold mode, provided that convst has gone low. It takes 3.6 microseconds after conversion, a total of 6 microseconds from rising edge (external reference, internal reference 5.0035ms) from convst to conversion completion, which is represented by busy going low. Note that the time since wake-up from the rising edge of convs is 2.5µs, if the convst pulse width is greater than 2.5µs, the conversion time will be greater than 6µs (2.5µs wake-up time + 3.6µs conversion time) as shown, from the rise of convs along the start. This is because the track/hold amplifier enters its hold mode on the falling edge of convst, and the conversion does not complete within 3.6 microseconds. In this case, busy would be the best indicator when the conversion is complete. Although the part is in sleep mode, data can still be read from the part. The read operation is the same as the mode 1 operation and must allow sufficient time for the track/hold amplifier to settle on the next convst. This mode is useful when switching parts - at a slow rate, since power consumption will be greatly reduced from mode 1 operation.

Dynamic Specifications

The AD7862 is specified, 100% tested to dynamic performance specifications as well as traditional DC specifications such as integral and differential nonlinearity. These AC specifications are required for signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the AD7862 include snr, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in detail in the following sections.

signal to noise ratio

snr is the analog to digital converter. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding DC, and has a maximum value of half the sampling frequency (fs/2). The signal-to-noise ratio depends - the number of quantization levels used in the digitization process is reduced; the more levels, the less quantization noise. Theoretical signal-to-noise ratio of a sine wave

input by

Signal-to-noise ratio = (6.02N + 1.76) dB(1), where N is the number of bits. So for an ideal 12-bit converter, the signal-to-noise ratio is 74 dB.

2.5µs*/5ms** wake up

Figure 7 shows the histogram of 8192 conversions of the dc input using the AD7862 from a 5 V supply. The analog input is set at the center of the transcoding. As can be seen, all codes appear in one output bin, which shows that the ADC has very good noise performance.

The data shown in Figure 8 is the same as the data shown in Figure 7, except in this case, the output data read for the device appears during the conversion process. This injects noise into the die when making bit decisions, increasing the noise produced by the AD7862. The histogram of 8192 conversions of the same DC input now shows a larger distribution of codes. This effect will depend on where the serial clock edge occurs relative to the bit trial of the conversion process. Depending on the serial clock edge versus the bit trial point, it is possible to achieve the same level of performance when reading during a conversion as when reading after a conversion.

The output spectrum of the ADC is evaluated by applying a very low distortion sine wave signal to the vax/bx input sampled at 245.76khz. Generates a Fast Fourier Transform (fft) plot from which SNR data can be obtained. Figure 9 shows a typical 2048-point FFT plot of the AD7862 with an input signal of 10 kHz and a sampling frequency of 245.76 kHz. The signal-to-noise ratio obtained from this figure is 72.95db. Harmonics should be considered when calculating the signal-to-noise ratio.

Figure 8. Histogram of 8192 Read Conversions - During Conversion

significant digits

The formula given in Equation 1 relates the signal-to-noise ratio to the number of bits. Rewriting the formula, as in Equation 2, yields a performance metric expressed in effective bits (n).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio.

Figure 10 shows a typical plot of effective bits versus frequency for the AD7862BN sampled at 245.76 kHz. Significant digits are typically between 11.6 and 10.6 corresponding to SNR figures of 71.59 dB and 65.57 dB.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (thd) is the ratio of the rms value of the harmonics to the rms value of the fundamental. For the AD7862, THD is defined as

where v1 is the rms amplitude of the fundamental and v2, v3, v4 and v5 are the rms amplitudes of the second to sixth harmonics. The thd is also derived from the fft plot of the adc output spectrum.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3. ……Wait. The intermodulation term refers to the intermodulation term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

Using the ccif standard, where two input frequencies near the top of the input bandwidth are used, the second and third order terms have different importance. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs. In this case, the input consists of two equal amplitude low distortion sine waves. Figure 11 shows a typical IMD diagram for the AD7862.

Peak harmonics or spurious noise

Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts of the harmonic buried in the noise floor, the peak will be the noise peak.

AC Linear Graph

When a sine wave of a specified frequency is applied to the vin input of the AD7862, and millions of samples are taken, a histogram showing the frequency of occurrence of each code in the 4096 ADC code can be generated. From this histogram data, a linear plot of the ac integral as shown in Figure 12 can be generated. This shows the very good integral linearity performance of the AD7862 at an input frequency of 10 kHz. The absence of large peaks in the graph shows good differential linearity. A simplified version of the formula used is outlined below.

where inl(i) is the integral linearity at code i. v(fs) and v(o) are the estimated full-scale and offset transitions, and v(i) is the estimated transition for the ith code. The estimated transcoding points for V(i) are derived as follows:

where a is the peak signal amplitude and n is the number of histogram samples:

Power Factor

In auto power-down mode, the part can operate at sample rates well below 200 kHz. In this case the power consumption will be reduced and depends on the sampling rate. Figure 13 shows a plot of power consumption versus sampling rate from 100 Hz to 90 kHz in auto power-down mode. Condition is 5 V supply 25°C, data read after conversion.

Microprocessor interface

The AD7862 high-speed bus timing allows direct connection to DSP processors as well as modern 16-bit microprocessors. A suitable microprocessor interface is shown in Figures 14 to 18.

AD7862–ADSP-2100 interface, Figure 14 shows the AD7862 and ADSP-2100. The convst signal can be provided by the adsp-2100 or an external power supply. The AD7862 is busy providing an interrupt to the adsp-2100 when the conversion is complete on all four channels. Four conversion results can then be read from the ad7862 using four consecutive reads to the same memory address. The following instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence):

Where mr0 is the adsp-2100 mr0 register and adc is the ad7862 address.

AD7862–ADSP-2101/ADSP-2102 Interface

The interface outlined in Figure 14 also forms the basis for the interface between the AD7862 and the ADSP-2101/ADSP-2102. The read line for the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the processor's rd pulse width can be programmed using the data memory wait state control register. The ADSP-2100 outlines the instructions for reading one of four results.

AD7862–tms32010 Interface The interface between the AD7862 and the tms32010 is shown in Figure 15. Again, the convst signal can be provided from the tms32010 or an external source, and the tms32010 is interrupted when both conversions are complete. The following instructions are used to read the conversion result from the AD7862: in D, ADC where d is the data memory address and adc is the ad7862 address.

AD7862–tms320c25 interface

Figure 16 shows the interface between the AD7862 and the tms320c25. As with the previous two interfaces, conversions can be initiated from the tms320c25 or an external source, and the processor is interrupted when the conversion sequence is complete. The tms320c25 does not have a separate rd output to directly drive the ad7862rd input. This has to be generated by the processor strb and r/w output, with some logic gates added. The rd signal is strobed with the msc signal to provide one wait state during the read cycle required for correct interface timing. Use the following command to read the conversion result from the AD7862: in D, ADC where d is the data memory address and adc is the ad7862 address.

Some applications may require conversions to be initiated by a microprocessor rather than an external timer. One option is to decode the AD7862 converter from the address bus so that a write operation starts the conversion. Data is read at the end of the transformation sequence as before. Figure 18 shows an example of initiating a conversion using this method. Note that for all interfaces it is best not to attempt read operations during conversion.

AD7862–MC68000 interface

The interface between the AD7862 and the MC68000 is shown in Figure 17. As before, conversions can be provided from the MC68000 or from an external source. The AD7862 busy can be used to interrupt the processor, or a software delay can ensure that a conversion has completed before attempting to read the AD7862. Due to its interrupting nature, the 68000 requires additional logic (not shown in Figure 18) to allow it to be interrupted properly.

The MC68000 AS and R/W outputs are used to generate the RD input signal of the split AD7862. cs is used to drive the 68000 dtack input to allow the processor to perform normal read operations on the AD7862. Use the following 68000 instructions to read the conversion result: move adc, d0. where d0 is the 68000 d0 register and adc is the ad7862 address.

AD7862–80C196 interface

Figure 18 shows the interface between the AD7862 and the 80C196 microprocessor. Here, the microprocessor initiates the conversion. This is accomplished by gating the 80C196 wr signal with the decoded address output (different from the AD7862 CS address). The AD7862 busy is used to interrupt the microprocessor when the conversion sequence is complete.

Vector Motor Control

The electric current of the motor can be divided into two parts: one part produces the torque, and the other part produces the magnetic flux. For optimum motor performance, these two components should be controlled independently. In traditional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the fundamental control variables; however, both torque and flux are functions of current (or voltage) and frequency. This coupling effect can degrade the performance of the motor because if torque is increased by increasing the frequency, for example, the flux tends to decrease.

Vector control of an AC motor involves controlling the phase in addition to the drive and current frequency. Controlling the phase of the motor requires feedback from the position of the rotor relative to the rotating magnetic field within the motor. Using this information, the vector controller mathematically converts the three-phase drive currents into individual torque and flux components. The AD7862 has four channels of simultaneous sampling capability, making it ideal for vector motor control applications.

A block diagram of a vector motor control application using the AD7862 is shown in Figure 19. The position of the magnetic field is determined by determining the current in each phase of the motor. Only two phase currents need to be measured, because if two phases are known, a third current can be calculated. VA1 and VA2 of the AD7862 are used to digitize this information.

Simultaneous sampling is essential to maintain relative phase information between the two channels. A current-sensing isolation amplifier, transformer, or Hall-effect sensor is used between the motor and the AD7862. The rotor information is obtained by measuring the voltages at the two inputs of the motor. VB1 and VB2 of the AD7862 are used to obtain this information. Also, the relative phase of the two channels is important. Use dsp microprocessor to carry out mathematical transformation and control loop calculation to the information fed back by ad7862.

Multiple AD7862S

Figure 20 shows a system in which multiple AD7862S can be configured to handle multiple input channels. This structure is common in applications such as sonar, radar, etc. The AD7862 has typical aperture delay limitations. This means that the user knows the difference in sampling instants between all channels. This allows the user to maintain relative phase information between different channels.

The common read signal from the microprocessor drives the rd input of all AD7862s. Each AD7862 is assigned a unique address selected by the address decoder. The reference output of digital 1 of the AD7862 is used to drive the reference input of all other AD7862s in the circuit shown in Figure 20. A single VREF pin can drive multiple AD7862 reference input pins. Alternatively, an external or system reference can be used to drive all VREF inputs. A common reference ensures good full-scale tracking between all channels.