feature

High-resolution analog-to-digital converter; 24-bit no missing codes; 0.0015% nonlinearity; optimized for fast channel switching; 18-bit pp resolution (21-bit valid) at 500Hz; 16-bit pp resolution (19-bit valid) at 8.5 kHz ); 15-bit pp resolution at 15 kHz (18-bit valid); on-chip per-channel system calibration; configurable inputs; 8 single-ended or 4 fully differential; input ranges; +625mV, +1.25V, +2.5V, 625mV, 1.25V, 2.5V; three-wire serial interface; SPI™, QSPI™, MICROWIRE™ and DSP compatible; logic input Schmitt trigger; single supply operation; 5 V analog supply; 3 V or 5 V digital Power supply; Packaging: 28 lead TSSOP.

application

Programmable logic controllers/distributed control systems; multiplexing applications; process control; industrial instrumentation.

General Instructions

The AD7738 is a high precision, high throughput analog front end. True 16-bit pp resolution is achievable with a total conversion time of 117 µs (8.5 kHz channel switching), making it ideal for high-resolution multiplexing applications. The part is configurable through a simple digital interface allowing users to balance noise performance and data throughput up to 15.4 kHz.

The analog front end has eight single-ended or four full-ended unipolar or bipolar 625 mV differential input channels, 1.25 V and 2.5 V input ranges and accepts common-mode input voltages from 200 mV above AGND to AVDD–300 mV. The multiplexer output is fixed externally, allowing the user to implement programmable gain or signal conditioning before applying the input to the ADC. The differential reference input has "no reference" detection capability. The ADC also supports per-channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt-triggered. The part is specified for operation in the extended industrial temperature range of -40 degrees Celsius to +105 degrees Celsius. Other members of the AD7738 family are AD7734 and AD7732.

The AD7734 analog front end features four single-ended input channels with a unipolar or true bipolar input range of ±10 V when operating on a 5V analog supply. The AD7734 accepts analog input overvoltages to ±16.5 V without degrading adjacent channel performance.

The AD7732 is similar to the AD7734, but its analog front end has two fully differential input channels.

Output Noise and Resolution Specifications

The AD7738 can operate with chopping enabled or disabled, allowing the ADC to be programmed to optimize throughput and channel switching time, or to optimize offset drift performance. Listed below are noise tables for the two main operating modes used to select the output rate and settling time.

Chopping enabled

The first mode, where the AD7738 is configured with chopping enabled (chopping=1), provides very low noise figures at lower output rates. Tables 1 to 3 show the -3db frequency and typical performance versus channel transition time or equivalent output data rate, respectively. Table 1 shows typical output rms noise. Table 2 shows typical effective resolutions based on rms noise. Table 3 shows typical output peak-to-peak resolution, representing values that do not experience code flicker within Six Sigma limits. Peak-to-peak resolution is not calculated based on rms noise, but rather based on peak-to-peak noise.

These typical numbers are generated from 4096 data samples collected in continuous conversion mode with the analog input voltage set to 0V and MCLK=6.144MHz. The conversion time is selected by the channel conversion time register.

cutoff disabled

The second mode, where the AD7738 is configured with chopping disabled (chopping = 0), provides faster conversion times while maintaining high resolution. Tables 4 to 6 show the -3db frequency and typical performance versus channel transition time or equivalent output data rate, respectively. Table IV shows typical output rms noise. Table V shows typical effective resolutions based on rms noise. Table 6 shows typical output peak-to-peak resolution, representing values that do not experience code flicker within Six Sigma limits. Peak-to-peak resolution is not calculated based on rms noise, but rather based on peak-to-peak noise.

These typical numbers are generated from 4096 data samples collected in continuous conversion mode with the analog input voltage set to 0V and MCLK=6.144MHz. The conversion time is selected by the channel conversion time register.

Typical Performance Characteristics - AD7738

register description

The AD7738 is configurable through a series of registers. Some of these configure and control general AD7738 functions, others are per channel. The register data width varies from 8 bits to 24 bits. All registers are accessed through communication registers, that is, any communication with the AD7738 must begin with a write to the communication register, specifying which register will be read or written subsequently.

communication register

8-bit, write-only register, address 00h

All communications with the part must begin with a write to the communications register. The data written to the communication register determines whether the subsequent operation is a read or a write, and which register this operation will be placed directly into. The digital interface by default expects a write to the communications register after power-up, after reset, or after a subsequent read or write to the selected register is complete. If the interface sequence is lost, the section can be reset by writing at least 32 serial clock cycles (DIN high and CS low) (note that in this case the modulator, filter, interface and all registers are included all parts will be reset). Remember to keep data low when reading 32 or more bits when in continuous read mode or when setting the dump bits and "24/16" bits in the mode register.

I/O port registers

8 bits, read/write register, address 01h, default value 30h + digital input value 40h

The bits in this register are used to configure and access the digital I/O pins on the AD7738.

test register

24-bit, read/write register, address 03h

This register is used to test parts in the manufacturing process. The user must not change the default configuration of this register.

ADC Status Register

8-bit, read-only register, address 04h, default 00h

In conversion mode, the register bits reflect the state of a single channel. When the conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. This bit is also reset to 0 when no read operation occurs and the result of the next conversion is updated to the channel data register. Writing to the mode register resets all bits to 0.

In calibration mode, all register bits are reset to 0 when calibration is in progress and set to 1 when calibration is complete.

The RDY pin output is related to the contents of the ADC status register defined by the RDY function bits in the I/O port register.

checksum register

16-bit, read/write register, address 05h

This register is described in the "AD7732/34/38 Checksum Registers" technical note.

ADC Zero Scale Calibration Register

24-bit, read/write register, address 06h, default 800000h

The registers hold the ADC zero-scale calibration coefficients. The value in this register is used in conjunction with the ADC full-scale calibration register and the corresponding channel zero-scale and channel full-scale calibration registers to digitally scale the conversion results for all channels. The value in this register is automatically updated after the ADC zero-scale ADC self-calibration is performed. This register can only be written to in idle mode. See Calibration Instructions for details.

ADC full scale register

24-bit, read/write register, address 07h, default 800000h

The registers hold the ADC full-scale coefficients. Users are advised not to change the default configuration of this register.

channel data register

16/24-bit, read-only register, address 08h–0Fh, default width 16 bits, default value 8000h

These registers contain the most recent conversion results for each analog input channel. 16-bit or 24-bit data width can be configured by setting the "16/24" bits in the mode register. When the result is updated, the associated RDY bit in the channel status register goes high. Once the data register is read, the RDY bit will return low. The RDY pin can be configured to indicate when any channel has unread data, or to wait for all enabled channels to have unread data. If any channel data register reads are in progress while the new result is being updated, the data registers will not be updated. This is to avoid getting corrupted data. Reading the status register can be associated with reading the data register in dump mode. Reading the status register is always associated with reading the data register in continuous read mode. See the digital interface description for details.

Channel Zero Scale Calibration Register

24-bit, read/write register, address 10h–17h, default 800000h

These registers hold specific channel zero-scale calibration coefficients. The values in these registers are used in conjunction with the values in the corresponding channel full-scale calibration register, ADC zero-scale calibration register, and ADC full-scale calibration register to digitally scale conversion results for a specific channel. The value in this register is automatically updated after performing a channel zero-scale system calibration.

The format of the channel zero-scale calibration register is a signed bit and a 22-bit unsigned value.

This register can only be written to in idle mode. See Calibration Instructions for details.

Channel Full-Scale Calibration Register

24-bit, read/write register, address 18h–1Fh, default 200000h

These registers hold specific channel full-scale calibration coefficients. The values in these registers are used in conjunction with the values in the corresponding channel zero-scale calibration register, ADC zero-scale calibration register, and ADC full-scale calibration register to digitally scale the conversion results for a specific channel. The value in this register is automatically updated after a channel full-scale system calibration is performed. This register can only be written to in idle mode. See Calibration Instructions for details.

channel status register

8-bit, read-only register, address 20h–27h, default 20h channel number

These registers contain individual channel status information and some general AD7738 status information. Reading the status register can be associated with reading the data register in dump mode. Reading the status register is always associated with reading the data register in continuous read mode. See the Digital Interface Description section for details.

Channel Switch Time Register

8-bit, read/write register, address 30h–37h, default 91h

The transition time registers enable or disable chopping and configure digital filters for specific channels. This register value affects the conversion time, frequency response, and noise performance of the ADC.

mode register

8-bit read/write register, address 38h–3Fh, default 00h

The mode register configures the part and determines the part's operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to logic high, exits all current operations, and initiates the mode specified by the mode bits.

The AD7738 contains only one mode register. The three lsb of the address used to write to the mode register specify the channel selected for the operation as determined by the MD2 to MD0 bits. Address 38h can only be used to read the mode register.

Digital Interface Description Hardware

The AD7738 serial interface can be connected to a host device through the serial interface in several different ways.

The CS pin can be used to select the AD7738 as one of several circuits connected to the host serial interface. When CS is high, the AD7738 ignores the SCLK and DIN signals and the DOUT pin enters a high impedance state. When not using the CS signal, connect the CS pin to DGND.

The RDY pin can be polled for a high-to-low transition, or it can drive a host device interrupt input to indicate that the AD7738 has completed the selected operation and/or that new data from the AD7738 is available. The host system can also wait a specified amount of time after a given command writes to the device before proceeding with a read. Alternatively, the AD7738 status can be polled. When the RDY pin is not used in the system, it should be left open. (Note that the RDY pin is always an active digital output, i.e. never goes into a high impedance state).

The reset pin can be used to reset the AD7738. When not in use, connect this pin to the DVD.

The AD7738 interface can be simplified to two wires, connecting DIN and bi-pin to one bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction with reference to the AD7738 timing specification (see Bus Abandon Time in Timing Characteristics). In a 2-wire serial interface configuration, the AD7738 cannot operate in continuous read mode.

All digital interface inputs are Schmitt-triggered. Therefore, the AD7738 interface has higher noise immunity, and the AD7738 can be easily isolated from the host system by an optocoupler.

Figure 5 outlines some possible host device interfaces: (a), SPI without CS signal, (b), DSP interface, and (c), 2-wire configuration.

reset

The AD7738 can be reset through the reset pin or by writing a reset sequence to the AD7738 serial interface. The reset sequence is N "0" + 32 "1", possibly the data sequence 00h+FFh+FFh+FFh+FFh+FFh in the byte-oriented interface. The AD7738 also has a power-on reset function with a trip point of 2V and a defined default state after power-up.

The first step in system configuration is a reset event or a reset sequence of 32 ones.

Access to AD7738 registers All communication with the part is to read or write the address register followed by the communication register.

In a simultaneous read and write interface (such as SPI), writing a "0" to read data is sent to the AD7738. Figure 6 shows the ADC status register.

Convert and read data in a single pass

When the mode register is written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When a single conversion command is written to the mode register, the ADC initiates a conversion on the channel selected by the address of the mode register. After the conversion is complete, update the data register, change the mode register to idle mode, set the relevant RDY bit, and the RDY pin goes low. When the associated channel data register is read, the RDY bit is reset and the RDY pin returns high.

Figure 7 shows the digital interface signal performing a single conversion on channel 0, waiting for the RDY pin to be low, and reading the channel 0 data register.

dump mode

When the dump bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or data register has been addressed by the communication register. When reading 24-bit data in dump mode, the DIN pin should not be too high. Otherwise the AD7738 will be reset.

Figure 8 shows the digital interface signal performing a single conversion on channel 0, waiting for the RDY pin to be low, and in dump mode.

Continuous conversion mode

When the mode register is written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When a continuous conversion command is written to the mode register, the ADC starts converting on the channel selected by the address of the mode register.

After the conversion is complete, the associated channel data register and channel status register are updated, the associated RDY bit in the ADC status register is set, and the AD7738 continues the conversion on the next enabled channel. The AD7738 will cycle through all enabled channels until another mode is entered or reset. The period will be the sum of the transition times for all enabled channels, set by the corresponding channel transition time registers.

The RDY bit is reset when the associated channel data register is read. The behavior of the RDY pin depends on the RDYFN bit in the I/O port register. When the RDYFN bit is 0, the RDY pin goes low when any channel has unread data.

Setting this bit to 1 will only drive the RDY pin low if all enabled channels have unread data.

If the ADC conversion result has not been read before the new ADC conversion is complete, the new result will overwrite the previous one. The associated RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating when the data register is updated and previous conversion data is lost.

If the data register is read while the ADC conversion is complete, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data will be lost.

Figure 9 shows the digital interface signal sequence for continuous conversion mode with channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the data register is read after each conversion. Figure 10 shows a similar sequence, but with the RDYFN bit set to 1. The RDY pin goes low to read the data register after all conversions are complete. Figure 11 shows the RDY pin when no data is being read from the AD7738.

Continuous Read (Continuous Conversion) Mode

The first write of "48h" to the communication register starts continuous read mode when the continuous RD bit in the mode register is set. As shown in Figure 12, subsequent accesses to the component sequentially read the channel status and data registers of the last completed conversion without further configuration of the communication registers.

Note that the continuous conversion bit in the mode register should be set when entering continuous read mode.

Note that continuous read mode is a "dump mode" read of the channel status and data registers, regardless of the dump bit value. Use the channel bits in the channel status register to check/identify which channel data is actually being shifted out.

Note that the last completed conversion result is being read. Therefore, the RDYFN bit in the I/O port register should be 0 and the read result should always start before the next conversion is complete.

The AD7738 will remain in continuous read mode as long as the DIN pin is low and the CS pin is low. Therefore, when reading in continuous read mode, 0 is written to the AD7738. To exit continuous read mode, hold the DIN pin up for at least 100 ns after the read is complete. (Write "80h" to AD77 38 to exit continuous read.)

Consecutive RD bits in the mode register do not change with DIN pin high. Therefore, the next write "48h" starts the continuous read mode again. To stop continuous read mode completely, write to the mode register to clear the continuous RD bit.

Circuit Description

The AD7738 is a sigma-delta a/D converter for measuring wide dynamic range, low frequency signals in industrial process control, instrumentation, PLCs, and differential scanning calorimeters.

It contains multiplexers, input buffers, sigma-delta (or charge balance) ADCs, digital filters, clock oscillators, digital I/O ports, and serial communication interfaces.

Analog front end

The AD7738 has nine analog input pins connected to the ADC through an internal multiplexer. The analog front end can be configured with 8 single-ended inputs, 4 differential inputs, or any combination of them. The selection of the ADC input is determined by the COM0 and COM1 bits in the channel setup register.

The AD7738 contains a wideband, fast settling time differential input buffer capable of driving dynamic loads of high speed sigma-delta modulators. With the internal buffer enabled, the analog input has a relatively high input impedance. However, if chopping is enabled and/or when switching between channels, there is dynamic current that charges the capacitance of the multiplexer, the capacitance of the pins, and any additional capacitance connected to MUXOUT. In a typical configuration where MUXOUT is directly connected to ADCIN, this capacitance can be about 20 pF. The AD7738 is designed to provide sufficient settling time after the multiplexer switch and before the actual sampling begins, provided that the source impedance of the analog input resistance does not exceed 10 kΩ.

An RC connected to the analog input can convert the dynamic charging current to a DC voltage and cause additional gain or offset errors. The recommended low-pass RC filter on the AD7738 analog input is 20Ω and 100 nF.

The multiplexer output and ADC input are fixed externally. This facilitates shared signal conditioning between the multiplexer and ADC. Note that any circuitry connected between MUXOUT and ADCIN should fully settle within the settling time provided by the AD7738 if chop is enabled and/or when switching between channels. See the Multiplexer, Conversion, and Data Output Timing sections.

- A/D converter

The AD7738 core consists of a charge-balanced sigma-delta modulator and a digital filter. The architecture is optimized for fast fully pinned transitions. This allows fast inter-channel switching while maintaining inherently good linearity, high resolution and low noise.

chopped

With chopping enabled, the multiplexer repeatedly inverts the ADC input. Each output data result is then calculated as the average of two transformations, the first transformed to a positive and the second a negative offset term. This effectively removes any offset errors from the input buffer and sigma-delta modulator, resulting in good DC offset and offset drift specifications. Figure 13 shows the channel signal chain with chopping enabled.

The "conversion time" specified by the multiplexer, conversion and data output timing consists of one or two "sink" and "sampling" periods and a "scaling" time.

With chopping enabled (Figure 14), the conversion cycle begins with a "settling" time of 43 or 44 MCLK cycles (~7 microseconds for 6.144 MHz MCLK) to allow the circuit after the multiplexer to settle. The analog signal is then sampled by a sigma-delta modulator, and the digital data stream is processed by a digital filter. The "sampling" time depends on FW, the channel switching time register content. After another 42 MCLK cycles (~6.8 µs) of "settling", the "sampling" time is repeated using an inverted (chopped) analog input signal. The two results from the digital filter are then averaged, scaled using the calibration register, and written to the channel data register for a "scaled" time of 163 MCLK cycles (~26.5 microseconds).

With chopping disabled (Figure 15), there is only one "sampling" time, preceded by a "settling" time of 43 or 44 MCLK cycles, followed by a "scaling" time of 163 MCLK cycles.

The RDY pin goes high during the "zoom time" regardless of its previous state. The relevant RDY bit is set in the ADC status register, in the channel status register, when the channel data register is updated and the channel conversion cycle ends, the RDY pin goes low. If in continuous conversion mode, the part will automatically continue the conversion cycle on the next enabled channel.

Note that the conversion time and chop mode can be configured independently for each channel. The effective data rate for the entire cycle and each channel depends on all enabled channel settings.

Frequency response

The sigma-delta modulator operates at 1/2 the MCLK frequency, which is the effective sampling frequency. Therefore, the Nyquist frequency is 1/4 of the MCLK frequency. The digital filter combined with the modulator has the frequency response of a first-order low-pass filter. The -3db point is close to the frequency of 1/channel transition time. The roll-off is -20db/dec up to the Nyquist frequency. If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response characteristic is close to frequency 1/channel transition time. The envelope at the top is also the ADC response –20 dB/dec.

Analog input voltage range

The absolute input voltage range of the enabled buffer input is limited from AGND+200 mV to AVDD–300 mV, which also limits the common-mode range. Care must be taken when setting the common-mode voltage and input voltage range so as not to exceed these limits, which will result in degraded linearity performance.

The analog inputs on the AD7738 can accept unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can handle negative voltages on its analog inputs related to system ground. Unipolar and bipolar signals on the AIN+ input are related to the voltage on the corresponding AIN(–) input.

For example, if AINCOM is 2.5 V and CH0 is configured to measure AIN0–AINCOM, 0 V to 1.25 V, the input voltage range on the AIN0 input is 2.5 V to 3.75 V. If CH0 is configured to measure AIN0–AINCOM, ±1.25 V, the input voltage range on the AIN0 input is 1.25 V to 3.75 V.

Analog input extended voltage range

The AD7738 output data code range corresponds to the nominal input voltage range. However, correct operation of the ADC is guaranteed within the min/max input voltage range.

When the mode register's clamp is set to 1, the channel data register will be digitally clamped to all zeros or all zeros when the analog input voltage exceeds the nominal input voltage range.

As shown in Tables XIII and XIV, when clamp = 0, the data reflects the analog input voltage outside the nominal voltage range. In this case, the sign and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result.

Voltage reference input

The reference inputs REFIN(+) and REFIN(–) of the AD7738 provide differential reference input capability. The common-mode range of these differential inputs is from AGND to AVDD. The nominal reference voltage for specified operation is 2.5 V.

Both reference inputs have high impedance, dynamic loads. Since the input impedance on each reference input is dynamic, external resistor/capacitor combinations can cause gain errors on the part.

The output noise performance listed in Tables 1 through 6 applies to an analog input of 0 V and is not affected by noise on the reference. To obtain the same noise performance as shown in the noise table over the entire input range, the AD7738 requires a low noise reference source. Excessive reference noise in the bandwidth of interest can degrade the performance of the AD7738.

Recommended voltage references for the AD7738 include the ADR421, AD780, REF43, and REF192. Decoupling the output of these reference signals is generally recommended to further reduce noise levels.

Reference detection

The AD7738 includes on-chip circuitry to detect whether the part has a valid conversion reference.

If the voltage between the REFIN(+) and REFIN(–) pins is below the NOREF trigger voltage (0.5 V typical) and the AD7738 is performing a conversion, set the NOREF bit in the channel status register.

I/O ports

The AD7738 pin SYNC/P1 can be used as a general purpose digital I/O pin or to synchronize the AD7738 with other devices in the system. When the sync bit in the I/O port register is set and the sync pin is low, the AD7738 does not process any conversions. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7738 will wait for the sync pin to go high before starting operation. This allows the user to start conversions from a known point in time, i.e. the rising edge of the synchronous pin.

calibration

The AD7738 features zero-scale self-calibration, zero-scale, and full-system calibration capabilities, effectively reducing offset and gain errors to noise levels. After each conversion, the ADC conversion result is scaled using the ADC calibration register and the associated channel calibration register before writing it to the data register. See equation below.

For unipolar range:

Data = ((ADC Result – ADC ZS Cal. Reg.) ADC FS Reg./200000 Hours - Ch.ZS Cal. Reg.) Ch.FS Cal. Registration time: 200,000 hours

For bipolar range:

Data = ((ADC Result – ADC ZS Cal. Reg.) ADC FS Reg./400,000 Hours + 800,000 Hours – Ch.ZS Cal. Reg.) Ch.FS Cal. Registers/200000 hours where ADC results are in the range 0 to ffffffh.

Note that the format of the channel ZS calibration register is sign bit + 22-bit channel offset value. The user is strongly advised not to change the ADC FS register.

To begin any calibration, write the relevant mode bits to the AD7738 mode register. After the calibration is completed, update the content of the corresponding calibration register, set all RDY bits in the ADC status register, the RDY pin goes low, and the AD7738 returns to idle mode.

The calibration duration is the same as the conversion time configured on the selected channel. The longer the conversion time, the less noise and the more accurate the calibration. Therefore, use at least the default conversion time to initiate any calibration.

ADC zero-scale self-calibration

ADC zero-scale self-calibration can effectively eliminate offset errors in chop-disabled mode. It also eliminates offset drift errors in chopper disabled mode if repeated after a temperature change.

A zero-scale self-calibration is performed on the internally shorted ADC input. The negative analog input on the selected channel is used to set the ADC ZS calibration common mode. Therefore, the negative terminal on the selected differential pair or AINCOM on a single-ended channel configuration should be driven to the appropriate commwon mode voltage.

It is strongly recommended that the ADC ZS calibration registers be updated only as part of a zero-scale self-calibration.

System calibration per channel

If using per-channel system calibration, start in the following order: first channel ZS system calibration, then channel FS system calibration.

System calibration is affected by the ADC ZS and FS calibration registers; therefore, if both self-calibration and system calibration are used in the system, the ADC self-calibration cycle should be performed before the system calibration cycle.

When performing a system calibration, a fully fixed system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog input.

Each channel calibration register can be read, stored or modified and written back to the AD7738. Note that the AD7738 must be in idle mode when writing to the calibration registers. Note that outside the specified calibration range, calibration is possible, but performance may be degraded. (See the System Calibration section on the Specifications page of this data sheet.)

Dimensions

28 Lead Thin Shrink Small Outline Package (TSSOP) (RU-28)