The UC3842A , UC3843A series of high-performance fixed-frequency current-mode controllers are designed for offline and DC-to-DC converter applications, providing designers with a cost-effective solution with minimal external components. These ICs feature trimmed oscillators for precise duty cycle control, temperature compensated references, high gain error amplifiers, current sense comparators, and high current totem pole outputs ideal for driving power mosfets.
Protection features are also included, including input and reference undervoltage lockouts, each with hysteresis, cycle-by-cycle current limit, programmable output deadtime, and latches for single-pulse metering.
These devices are available in an 8-pin dual-in-line plastic package and a 14-pin plastic surface mount (SO-14). The SO-14 package has separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), making it ideal for off-line converters. Designed for low voltage applications, the UCX843A has UV thresholds of 8.5 V (on) and 7.6 V (off). 8226 ; trimming oscillator discharge current for precise duty cycle control current mode operation up to 500 kHz
Automatic feed-forward compensation Latching PWM with cycle-by-cycle current limit Internal trimming with undervoltage lockout High current totem pole output undervoltage lockout with hysteresis

Instructions
The UC3842A and UC3843A series are high performance, fixed frequency, current mode controllers. They are designed for off-line and DC-DC converter applications, providing designers with a cost-effective solution that requires minimal external components.

Oscillator The oscillator frequency is programmed by the values selected for the timing components rt and ct. Capacitor CT is charged from the 5.0V reference voltage to about 2.8V through resistor RT and discharged to 1.2V through the internal current sink. During CT discharge, the oscillator generates an internal blanking pulse that keeps the center input of the nor gate high. This causes the output to be in a low state, resulting in a controlled amount of output dead time. Figure 1 shows RT versus oscillator frequency for a given CT value, and Figure 2 shows output dead time versus frequency. Note that many values of rt and ct will give the same oscillator frequency, but only one combination will produce a specific output dead time at a given frequency. Oscillator thresholds are temperature compensated, and discharge current is trimmed and guaranteed to within ±10% at Tj=25°C. These internal circuit improvements minimize changes in oscillator frequency and maximum output duty cycle. The results are shown in Figures 3 and 4.
In many noise sensitive applications it may be necessary to frequency lock the converter to an external system clock. This can be achieved by applying a clock signal to the circuit shown in Figure 20. For reliable locking, the free-running oscillator frequency should be set about 10% lower than the clock frequency. The method of multi-unit synchronization is shown in Figure 21. By adjusting the clock waveform, accurate output duty cycle clamping can be achieved.
Error Amplifier The present invention provides a fully compensated error amplifier with access to inverting inputs and outputs. It features a typical DC voltage gain of 90 dB, a unity gain bandwidth of 1.0 MHz, and a phase margin of 57 degrees. Non-vertical inputs are internally biased at 2.5 V and are not fixed. The converter output voltage is normally distributed down and monitored by the inverter input. The maximum input bias current is –2.0µA, which can cause an output voltage error equal to the product of the input bias current and the equivalent input divider source resistance.
The error amplifier output (pin 1) is used for external loop compensation, the output voltage is offset by two diode drops (≈1.4V) and divided by three, then connected to the inverting input of the current sense comparator. This guarantees that no drive pulses will appear on the output (pin 6) when pin 1 is in its lowest state (vol). This occurs when the power supply is operating and the load is removed, or at the beginning of the soft-start interval, the error amplifier minimum feedback resistance is limited by the amplifier source current (0.5mA) and the desired output voltage (VOH) to The 1.0 volt clamp level of the comparator is reached

Current sense comparator and pwm latch
The uc3842a, uc3843a act as current mode controllers whereby the output switch conduction is initiated and terminated by the oscillator when the peak inductor current reaches a threshold level established by the error amplifier output/compensation (pin1). Therefore, the error signal controls the peak inductor current on a cycle-by-cycle basis. The current sense comparator pwm latching configuration used ensures that only one pulse appears at the output during any given oscillator cycle. The inductor current is converted to a voltage by inserting a ground referenced sense resistor rs in series with the source of the output switch q1. This voltage is monitored by the current sense input (pin 3) and compared to the level derived from the error amplifier output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1, where:

Abnormal operating conditions occur when the power supply output is overloaded or when output voltage sensing is lost. Under these conditions, the current sense comparator threshold will be internally clamped to 1.0V. Therefore, the maximum peak switch current is:

When designing high power switching regulators, in order to keep the power dissipation of the switching regulator at a reasonable level, it is necessary to reduce the internal clamping voltage. A simple way to adjust this voltage is shown in Figure 22. Two external diodes are used to compensate the internal diode to produce a constant clamping voltage. If the IPK (max) clamp voltage is lowered too much, unstable operation may occur due to noise pickup.
Narrow spikes on the leading edge of the current waveform are often observed and can cause power supply instability when the output is lightly loaded. This spike is due to the power transformer inter-winding capacitance and output rectifier recovery time. Adding an RC filter to the current sense input with a time constant close to the spike duration can often remove the instability

Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to ensure that the IC is fully operational before the output stage is enabled. The positive supply terminal (VCC) and the reference output (VREF) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The upper and lower limits of the VCC comparator are 16 V/10 V and 8.4 V/7.6 V, respectively. The upper and lower limits of the VREF comparator are 3.6 V/3.4 V, respectively. The large hysteresis and low start-up current of the UCX842A make it ideal for offline converter applications requiring efficient boot-start techniques. ED (Figure 33). The UCX843A is suitable for low voltage DC-DC converter applications. A 36V zener acts as a shunt regulator from VCC to ground. Its purpose is to protect the integrated circuit from overvoltages that may occur during system startup. The minimum operating voltage is 11 V for the UCX842A and 8.2 V for the UCX843A.
Yields These devices contain a totem pole output stage specifically designed to directly drive power MOSFETs. It has a peak drive current of ±1.0A, typical rise and fall times of 50ns, and a load of 1.0nF. Added additional internal circuitry to keep the output in sink mode when undervoltage lockout is active. This feature does not require an external pull-down resistor.
The SO–14 surface mount assembly provides separate pins for VC (output power) and power ground. Proper implementation will significantly reduce switching transient noise levels imposed on the control circuit. This is especially useful when reducing the IPK (max) clamp level. The independent VC supply input allows designers to add flexibility when customizing the drive voltage independent of VCC. Zener clamps are usually connected to this input when driving power mosfets in systems with VCC greater than 20V . Figure 25 shows the correct power and control ground connections in a current sensing power mosfet application.
The 5.0V bandgap reference is trimmed to ±1.0% tolerance at Tj=25°C on the UC284KA and ±2.0% on the UC384KA. Its main purpose is to provide charging current for the oscillator timing capacitor. The reference is short-circuit protected and capable of supplying more than 20 mA of additional control system circuitry.