The ADC08038 is an 8-bit successive approximation A/D converter with serial I/O and a configurable input multiplexer for up to 8 channels. Serial I/Os are configured to comply with the NSC Microwire serial data exchange standard for easy interfacing with COPS series controllers and with standard shift registers or microprocessors. The track/hold function allows the analog voltage to be positive and the input to change during the actual A/D conversion. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. Also, input voltage spans as small as 1V can be accommodated.

ADC08038 functional description

1.0 Multiplexer Addressing

These converters are designed with a built-in sample-and-hold comparator structure that provides a differential analog input that is converted by a successful approximation procedure.

The actual converted voltage is always the difference between the specified "+" input terminal and "-" input terminal. The polarity of each pair of input terminals represents the most positive line expected by the converter. If the specified "+" input voltage is less than the "-" input voltage, the converter will respond with an all-zero output code.

A unique input multiplexing scheme is used to provide software-configurable single-ended, differential or pseudo-differential operation for multiple analog channels (it will convert the voltage difference between any analog input and the common terminal). This input flexibility greatly simplifies the analog signal conditioning required for sensor-based data acquisition systems. One converter package can now handle ground-referenced and true differential inputs as well as signals with arbitrary reference voltages.

A specific input configuration is assigned during the mux addressing sequence before starting a conversion. The MUX address selects the analog input, and since the input configuration is software controlled, it can be modified as needed before each conversion. One channel can be treated as a single-ended ground-referenced input for one conversion; it can then be reconfigured to be part of another converted differential channel. Figure 1 illustrates the input flexibility that can be achieved. The analog input voltage of each channel can go from 50mV below ground to 50mV above VCC (typically 5V) without degrading conversion accuracy.

2.0 digital interface

One of the most important features of these converters is their serial data link to the control processor. Using the serial communication format provides two very important system improvements; it allows many functions to be contained in a small package, and it eliminates the transmission of low-level analog signals by positioning the converter on the analog sensor; the transmission of high Noise and jamming return the gital data to the host processor.

To understand the operation of these converters, it is best to refer to the timing and functional block diagrams and follow the complete conversion sequence. For clarity, separate timing diagrams are shown for each device.

(1) The conversion is started by pulling the CS (chip select) line low. This line must remain low throughout the conversion process. The converter is now waiting for the start bit and its mux assignment word.

(2) On each rising edge of the clock, the state of the data in the (DI) row is clocked into the MUX address shift register. The start bit is the first logical "1" that occurs on this line (all leading zeros are ignored). After the start bit, the converter expects the next 2 to 4 bits to be the mux assignment word.

(3) When the starting position is shifted to the starting position of the MUX register, the input channel has been allocated and the conversion is about to start. An interval of 1/2 clock cycle is automatically inserted (if nothing happens) to allow the selected mux channel to stabilize. At this point, the sars line goes high, indicating that a conversion is in progress, and the di line is disabled (no longer accepting data).

(4) The data output (do) line is now out of tri-state and provides leading zeros for this one clock cycle of the mux.

(5) During the conversion process, the output of the sar comparator indicates whether the analog input is greater (high) or less than (low) a series of continuous Voltage. After each comparison, the output of the comparator is sent to the do line on the falling edge of clk. This data is the result of the conversion being shifted out (msb first) and can be read immediately by the processor.

(6) After 8 clock cycles, the conversion is completed. The sars line returns low to indicate a later /[2][3] clock cycle.

(7) The data stored in the successive approximation register is loaded into the internal shift register. If the programmer wishes, the data can be provided in lsb first format [this utilizes the Shift Enable (SE) control line]. Regarding the ADC08038 SE line lead, if it is kept high, the LSB value remains valid on the DO line. when? SE is forced to turn down the data and is first clocked by LSB. For devices where de does not include the SE control line, the data, LSB first, is automatically shifted out of the do line after the msb first data stream. Then the do line goes low and stays low until cs returns high. The ADC08031 is an exception because its data is output only in msb first format.

(8) When the CS line is high and the Tselect requirement is met, all internal registers are cleared. See "Data Input Timing" under "Timing Diagram". If another transition is de-sired cs must do a high-to-low transition followed by the address information. The di and do wires can be tied together and controlled via the bidirectional processor I/O bits of one wire. This is possible because the di input is only "observed" during the mux addressing interval, while the do line is still in a high impedance state.

3.0 Reference Factors

The voltage vrefin applied to the reference input of these converters defines the voltage range of the analog input (the difference between VIN (max) and VIN (min) over which 256 possible output codes apply . This device can be used for both ratiometric measurement applications and systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance (as low as 1.3KΩ). This pin is used for successive approximation conversion on top of the resistor divider string and capacitor array.

In a ratiometric measurement system, the analog input voltage is proportional to the A/D reference voltage. This voltage is usually the system power supply, so the VREFin pin can be connected to VCC. This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, maintaining the same output code for a given input condition.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between very specific voltage limits. For the ADC08034 and ADC08038, a bandgap reference of 2.6V (Note 8) is connected to VREFOUT. This can be bound to vrefin. A 100µF capacitor is recommended to bypass Vrefout. The LM385 and LM336 reference diodes are good low current devices to use with these converters.

The maximum value of the reference voltage is limited to the VCC supply voltage. However, the minimum value can be very small (see Typical Performance Characteristics) to allow direct conversion of the sensor output, providing an output span of less than 5V. Due to the increased sensitivity of the converter (1lsb equals vref/256), special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span.

4.0 Analog Input

The most important feature of these converters is that they can be located at an analog signal source and communicate with a control processor with a high noise immunity serial bit stream over a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy or likely to be noisy at first, a few words are right to ride on a large common-mode voltage.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is /2 of the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

where fcm is the frequency of the common-mode signal, Vpeak is its peak voltage value, and Fclk is the A/D clock frequency.

In order for a 60Hz common-mode signal to produce a /4 LSB error (≈5mV) when the converter is running at 250kHz, it must peak at 6.63V, which will be greater than the allowable value when it exceeds the maximum analog input limit.

The source resistance limit is important for the DC leakage current into the multiplexer. Bypass capacitors should not be used if the supply resistance is greater than 1kΩ. Worst-case leakage currents over ±1µA over temperature will produce a 1MV input error with a 1kΩ source resistance. If a high impedance signal source is required, an op amp rc active low pass filter can provide impedance buffering and noise filtering.

5.0 Optional Adjustments

5.1 Zero error

The zero point of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value vin(min) is not grounded. By biasing any VIN (negative) input at that VIN (min) value, the converter can output a 0000 0000 numeric code for this min input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (vin) input. Zero error is only the difference between the actual DC input voltage required to convert the output digital code from 0000 to 0000 0001 and the ideal /2 LSB value (/2 LSB = 9.8MV at 11 VREF = 5.000VDC).

5.2 Full scale

The full-scale adjustment can be done by applying a differential input voltage (1/2 lsb lower from the desired analog full-scale voltage range) and then adjusting the size of the vrefin input of the digital output code just changed from 1111110 to 1111111. 1

5.3 Adjust any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. Apply a VIN (+) voltage equal to the desired zero reference voltage plus /2 LSB (where 1 LSB=analog span/256 is used to calculate the LSB of the desired analog span) to the selected "+" input, The zero reference voltage at the corresponding "-" input should then be adjusted to obtain a 00Hex to 01Hex code transition. A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by: