General Instructions

The AOZ1021 is a synchronous high-efficiency, simple-to-use, 3-buck regulator. The AOZ1021 operates from an input voltage range of 4.5V to 16V, providing up to 3A with continuous output current adjustable down to 0.8V. The AOZ1021 is available in an SO-8 package and is rated over an ambient temperature range of -40°C to +85°C.

Features: (1), 4.5V to 16V working input voltage range; (2), synchronous rectification: 100MΩ internal high voltage side.

Switch and 20MΩ internal low side switch: (1), high efficiency: up to 95%; (2), internal soft start; (3), 1.5% initial output accuracy.

The output voltage can be adjusted to 0.8V: (1), 3A continuous output current.

Fixed 500kHz pulse width modulation operation: (1), cycle-by-cycle current limit.

Pre-bias start: (1), short circuit protection; (2), thermal shutdown; (3), small SO-8 package.

Applications: (1), point-of-load DC/DC conversion; (2), PCIE graphics cards; (3), set-top boxes; (4), DVD drives and hard drives; (5), LCD panels; (6), cable modems ; (7), telecommunication/network/data communication equipment.

Detailed description

The AOZ1021 is a current-mode buck regulator with integrated high-side PMOS switches and low-side NMOS switches. It operates from an input voltage range of 4.5V to 16V and provides up to 3A of load current. The duty cycle can be adjusted from 6% to 100%, allowing a wide output voltage range. Features include enable control, power-on reset, input undervoltage lockout, output overvoltage protection, active high power good state, fixed internal soft-start, and thermal shutdown.

Enable and Soft Start

The AOZ1021 has an internal soft-start function to limit the inrush current and ensure that the output voltage rises smoothly to the regulated voltage. The soft-start process begins when the input voltage rises to 4.1V and the voltage on the en pin is high. During the soft-start process, the output voltage usually gradually changes to the regulated voltage within 4ms, and the 4ms soft-start time is set internally.

The EN pin of the AOZ1021 is active high. If not used, connect a 10KΩ resistor between this pin and the VIN. Grounding EN will disable the AOZ1021. Don't leave it on. The voltage on the EN pin must be higher than 2V to enable the AOZ1021. When the voltage on the EN pin falls below 0.6V, the AOZ1021 is disabled. If the application circuit requires that the AOZ1021 be disabled, an open drain or open collector circuit should be used to connect to the EN pin.

steady state operation

Under steady-state conditions, the converter operates at a fixed frequency and in continuous conduction mode (ccm).

aoz1021 integrates an internal p-mosfet as a high side switch. The inductor current is sensed by amplifying the voltage drop from the drain to the source of the high side power mosfet. The output voltage is reduced by an external voltage divider at the FB pin. The difference between the FB pin voltage and the reference voltage is amplified by an internal transconductance error amplifier. Compare the error voltage displayed on the comp pin with the current signal at the input of the pwm comparator (that is, the sum of the inductor current signal and the slope compensation signal). If the current signal is less than the error voltage, the internal high side switch is turned on. Inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high side switch is turned off. The inductor current is freewheeling for output through an internal low-side n-mosfet switch. Internal adaptive FET drivers ensure that neither high-side nor low-side switches turn on overlap. Compared to regulators that use free-spinning Schottky diodes, the aoz1021 uses free-spinning nmosfets for synchronous rectification. It greatly improves the efficiency of the converter and reduces the power loss of the low-voltage side switch tube.

aoz1021 uses p-channel mosfet as high side switch. It saves the bootstrap capacitance typically seen in circuits using nmos switches. Allows 100% turn-on of the high-side switch for linear regulation operation. The minimum voltage drop from v to v is the load current of the mosfet x the dc resistance + the dc resistance of the buck inductor. It can be calculated by the following formula:

where; vou max is the maximum output voltage; vin is the input voltage between 4.5v to 16v; IO is the output current from 0A to 3A, and rds(on) is the on-resistance of the internal mosfet, based on the input voltage and junction temperature , the value is between 97mΩ and 200mΩ.

On-off level

The AOZ1021 switching frequency is fixed and set by the internal oscillator. Due to device variations, the actual switching frequency can be from 350khz to 600khz.

Output voltage programming

The output voltage can be set by feeding the output back to the FB pin using a resistor divider network. See the application circuit shown in Figure 1. The resistor divider network consists of R and R. Typically, a design is started by picking a fixed value of R and calculating the required R with the following formula:

Protection features

The AOZ1021 has multiple protection functions to prevent damage to the system circuit under abnormal conditions.

Over Current Protection (OCP)

The sensed inductor current signal is also used for overcurrent protection. Since the aoz1021 uses peak current mode control, the comp pin voltage is proportional to the peak inductor current. The comp pin voltage is internally limited between 0.4v and 2.5v. The peak current of the inductor is the automatic limit cycle.

When the output is shorted to ground under fault conditions, the inductor current decays very slowly over the switching cycle due to V=0V. To prevent catastrophic failure, a secondary current limit is designed inside the AOZ1021. Compare the measured inductor current to a preset voltage representing the current limit, which is between 3.5A and 5.0A. When the output current is greater than the current limit, the high side switch will turn off. Once the overcurrent condition is resolved, the converter will initiate a soft start.

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.1V, the inverter starts to work. When the input voltage falls below 3.7V, the converter shuts down.

Thermal Protection

An internal temperature sensor monitors the connector temperature. When the junction temperature exceeds 150°C, the internal control circuit and the high-side PMOS are turned off. When the junction temperature drops to 100°C, the regulator will automatically restart under the control of the soft-start circuit.

application information

The basic AOZ1021 application circuit is shown in Figure 1. Component selection is described below.

input capacitor

The input capacitor must be connected to the V pin and PGND pin of the AOZ1021 to maintain a stable input voltage and filter out pulsed input current. The voltage rating of the input capacitor must be greater than the maximum input voltage plus the ripple voltage. The input ripple voltage can be approximated by the following equation:

Since the input current of a buck converter is discontinuous, the current stress on the input capacitor is another consideration when choosing capacitors. For a buck circuit, the rms value of the input capacitor current can be calculated by the following formula:

If we let m equal the conversion ratio:

The relationship between input capacitor rms current and voltage slew rate is shown in Figure 2 below. It can be seen that the current stress of c is the largest when v is half of v. The worst current stress on c is 0.5xi.

For reliable operation and optimum performance, the input capacitor must have a current rating higher than I under worst-case operating conditions. Ceramic capacitors are the preferred input capacitors because of their low esr and high current rating. Other low ESR tantalum capacitors can also be used depending on the application circuit. When choosing ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for better temperature and voltage characteristics. Note that capacitor manufacturers' ripple current ratings are based on a certain lifetime. Actual designs may require further derating.

Inductor

The inductor is used to provide a constant current output when it is driven by a switching voltage. For a given input and output voltage, the inductor and switching frequency together determine the inductor ripple current, which is:

The peak inductor current is:

High inductance provides low inductor ripple current, but requires larger size inductors to avoid saturation. Low ripple current reduces inductor core losses. It also reduces the rms current through the inductor and switch, thereby reducing conduction losses. Typically, the peak-to-peak ripple current on the inductor is designed to be 20% to 30% of the output current.

When choosing an inductor, make sure it can handle peak currents without saturation even at the highest operating temperature. The inductor accepts the highest current in the buck circuit. Conduction losses on inductors need to be checked for compliance with thermal efficiency requirements. Coilcraft, elytone and murata offer surface mount inductors in different shapes and styles. The shielding inductance is small in size, and the radiated electromagnetic interference is small. But they are more expensive than unshielded inductors. The choice depends on EMI requirements, price and size.

output capacitor

Select the output capacitor based on the DC output voltage rating, output ripple voltage specification, and ripple current rating. The voltage rating of the selected output capacitor must be higher than the maximum expected output voltage (including ripple). Long-term reliability requires consideration of degradation. The output ripple voltage specification is another important factor in selecting an output capacitor. In a buck converter circuit, the output ripple voltage is determined by the inductor value, switching frequency, output capacitor value, and esr. It can be calculated by the following formula:

where: co is the output capacitor value and esrco is the equivalent series resistance of the output capacitor.

When using a low esr ceramic capacitor as the output capacitor, the impedance of the capacitor at the switching frequency dominates. The output ripple is mainly caused by the capacitor value and the inductor ripple current. The output ripple voltage calculation can be simplified as:

When the esr impedance of the switching frequency dominates, the output ripple voltage is mainly determined by the capacitor esr and the inductor ripple current. The output ripple voltage calculation can be further simplified as:

To reduce the output ripple voltage over the entire operating temperature range, it is recommended to use X5R or X7R dielectric ceramic or other low ESR tantalum as the output capacitor.

In a buck converter, the output capacitor current is continuous. The rms current of the output capacitor is determined by the peak-to-peak ripple current of the inductor. The calculation method is as follows:

Usually, the ripple current rating of the output capacitor is a lesser concern due to the low current stress. When the buck inductor is chosen to be small and the inductor ripple current is large, the output capacitor will be overstressed.

loop compensation

AOZ1021 adopts peak current mode control, which is easy to use and has fast transient response. Peak current mode control eliminates the bipolar effect of the output L&C filter. This greatly simplifies the design of the compensation loop.

With peak current mode control, the buck power stage can be simplified as a one-pole-one-zero system in the frequency domain. The pole is the dominant pole and can be calculated by the following formula:

Because of the output capacitance and its esr, the zero is the esr zero. Its calculation method is as follows:

where;co is the output filter capacitor, rl is the load resistance value, and esrco is the equivalent series resistance of the output capacitor.

The compensation design actually obtains the desired gain and phase by changing the transfer function of the converter control loop. Several different types of compensation networks can be used with the AOZ1021. In most cases, a series capacitor and resistor network connected to the comp pin sets the pole zero and is sufficient for a stable high bandwidth control loop.

In the AOZ1021, the FB pin and the COMP pin are the inverting input and output of the internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The poles are:

where: gea is the error amplifier transconductance, which is 200×10-6A/V, gvea is the error amplifier voltage; and C2 is the compensation capacitor in Figure 1.

The zero given by the external compensation network capacitor C and resistor R is located at:

In order to design the compensation circuit, the target crossover frequency f must be chosen as the closed loop. The system crossover frequency is where the control loop has unity gain. Crossover is also known as converter bandwidth. Generally, higher bandwidth means faster response to load transients. However, considering the stability of the system, the bandwidth should not be too high. When designing the compensation loop, the stability of the converter under all line and load conditions must be considered. In general, it is recommended to set the bandwidth equal to or less than 1/10 of the switching frequency. The AOZ1021 operates in the frequency range of 350kHz to 600kHz. It is recommended to choose a crossover frequency less than or equal to 40kHz.

The strategy for choosing r and c is to use r to set the crossover frequency and c to set the compensator zero. Compute r with the chosen crossover frequency f:

where: where fc is the desired crossover frequency. For best performance, set fc to be around 1/10 of the switching frequency, VFB to be 0.8V, gea is the error amplifier transconductance, which is 200×10-6a/v, and gcs is the transconductance of the current sense circuit, which is 6.68a/v.

Compensation capacitor C and resistor R together form zero. This zero is placed close to the dominant pole f, but below 1/5 of the chosen crossover frequency. C can be selected by:

The above equation can be simplified to:

Thermal Management and Layout Considerations

In the AOZ1021 buck regulator circuit, high pulse current flows through two circuit loops. The first loop starts with the input capacitor, V pin, LX pin, filter inductor, output capacitor, and load, and returns to the input capacitor through ground. When the high-side switch is turned on, current flows in the first loop. The second loop starts from the inductor, to the output capacitor and load, to the low-side nmosfet. When the low-side nmosfet is turned on, current flows in the second loop. In the pcb layout, minimizing the area of the two loops can reduce the noise of the circuit and improve the efficiency. It is strongly recommended to use a ground plane to connect the input capacitors, output capacitors and PGND pins of the AOZ1021.

In the AOZ1021 buck regulator circuit, the main power dissipation components are the AOZ1021 and the output inductor. The total power consumption of the converter circuit can be measured by subtracting the output power from the input power.

The power loss of the inductor can be approximated by the output current of the inductor and the DCR.

The power loss of the inductor can be approximated by the output current of the inductor and the DCR.

The maximum junction temperature of the AOZ1021 is 150°C, limiting the maximum load current capability. See the thermal derating curve for the maximum load current of AOZ1021 at different ambient temperatures.

The thermal performance of aoz1021 is greatly affected by the layout of the PCB. During the design process, the user should take extra care to ensure that the integrated circuit operates under the recommended environmental conditions.

1. Do not use thermal connections for V and PGND pins. Pour the largest copper area into the PGND pin and VIN pin to help with heat dissipation.

2. The input capacitor should be placed as close as possible to the V pin and PGND pin.

3. It is recommended to use the ground plane. If no ground plane is used, separate pgnd from agnd and connect them at only one point to avoid pgnd pin noise coupling to agnd pin.

4. Keep the current trace from the lx pin to l to c to pgnd as short as possible.

5. Pour copper planes on all unused board areas and connect them to stable DC nodes such as V, GND, or V.

6. The lx pin is connected to the internal pfet drain. They are a low resistance thermal conduction path and the noisiest switching node. Connect a copper plane to the LX pin to help with heat dissipation. This copper plane should not be too large or switching noise may couple to other parts of the circuit.

7. Keep the sensitive signal trace away from the LX pin.