The AD7520 and AD7521 are monolithic, high precision, low cost, 10- and 12-bit resolution, multiplying digital-to-analog converters (DACs). Intersil's thin films on CMOS processes offer up to 10-bit accuracy in TTL/CMOS compatible operation. The digital inputs are fully protected against electrostatic discharge by diode-to-ground and positive supply.

Typical applications include digital/analog interfaces, multiplication and division, programmable power supplies, crt character generation, digitally controlled gain circuits, integrators and attenuators, and more.

Absolute Maximum Ratings

Supply voltage (V+ to ground)………………+17V; Voltage………………………………±25V

Digital Input Voltage Range ……………………V+ to GND; Output Voltage Compliance to Ground …………-100mV to V+

operating conditions

temperature range

JN, LN version………………………… 0C to 70Coo

Hot information

Thermal Resistance (Typical, Note 1) θja(c/w) θjc(c/w)oo; 16 LD PDIP package 90 not applicable; 18 LD PDIP package 80 not applicable

Maximum connection temperature (plastic package) …….150℃; Maximum storage temperature range………………- 65C to 150C; Maximum lead temperature (soldering 10s) ………… 300 ℃

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and is not meant to operate under these or any other conditions above those shown in the operating section of this specification.

The digital control inputs are zener protected, however, permanent damage to unconnected units may occur under high energy electrostatic fields. Always keep unused units in conductive foam.

Do not apply a voltage DD higher than V or less than ground potential on any terminal (except V).

1. θja is measured in free air with components mounted on an inefficient thermal conductivity test board.

Pin Description

Nonlinearity: Error caused by the deviation of the DAC transfer function from the "best straight line" in the actual plot of the transfer function. Usually expressed as a percentage of full scale range or as a (sub)multiple of 1 lsb. Resolution: It accounts for the smallest variation of different analog outputs that a D/A converter can produce. It is usually expressed as converter bits. A converter with n-bit resolution can resolve an output change of 2 over the full-scale range, e.g. 2 vref for unipolar conversions. Resolution by no means means linearity. -NN

Settling time: For a given digital input change, i.e. all digital inputs going low to high and high to low, the time it takes for the output of the DAC to settle around its final value (e.g. /2lsb) to the specified error band.

Gain Error: The difference between the actual and ideal analog output values over the full scale range, i.e. all digital inputs in the high state. It is expressed as a percentage of full scale range or as a (sub)multiple of 1 lsb.

Feedthrough Error: Error caused by capacitive coupling between VREF and IOUT1 when all digital inputs are low.

Output capacitor: IOUT1 and IOUT2 terminal to ground capacitance.

Output leakage current: The current that appears on the IOUT1 terminal when all digital inputs are low, or the current that appears on the IOUT2 terminal when all digital inputs are high.

Detailed description

The AD7520 and AD7521 are monolithic multiplying D/A converters. The highly stable thin film r-2r resistor ladder network and nmos-spdt switch form the basis of the converter circuit, and the cmos level shifter allows low power ttl/cmos compatible operation. An external voltage or current reference and op amp are all that is required for most voltage output applications.

The simplified equivalent circuit of the DAC is given in the functional diagram. The nmos spdt switch controls the ladder current between the iout1 and iout2 buses, which must be held at ground potential. This configuration maintains a constant current in each run independent of the input code.

Converter errors are further reduced by using separate metal interconnects between the main bits and the output. Using a high threshold switch reduces offset (leakage) errors to negligible levels.

The level shifter circuit consists of three positive feedback inverters from the second output to the first output, see Figure 1. This construction makes it TTL/CMOS compatible and operates over the entire military temperature range. In a level-shifter-driven trapezoidal spdt switch, each switch is quadratic weighted by an on-resistance proportional to its respective trapezoidal branch current. This ensures a constant voltage drop across each switch, creating equipotential terminations for 2R resistor ladders and high precision branch currents.

Test Circuit The following test circuit applies to the AD7520. The AD7521 also uses a similar circuit.

Test Circuit The following test circuit applies to the AD7520. The AD7521 also uses a similar circuit.

Unipolar Binary Operations Applications

The circuit configuration for operating the AD7520 in unipolar mode is shown in Figure 8. A similar circuit can be used for the AD7521. With positive and negative VREF values, the circuit is capable of 2-quadrant multiplication.

Zero offset adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjustment trimmer of the output op amp to 0V.

Gain adjustment

1. Connect all digital inputs to V+.

2. Monitor the A-VREF(1-2) reading of VOUT. (n=8 for AD7520, n=10 for AD7521). -N

3. To reduce the voltage output, connect a series resistor (0 to 250Ω) between the reference voltage and the VREF terminal.

4. To increase the output voltage, connect a series resistor (0 to 250Ω) in the feedback loop of the IOUT1 amplifier.

Bipolar (biased binary) operation

Figure 9 shows the circuit configuration for operating the AD7520 in bipolar mode. A similar circuit can be used for the AD7521. Four-quadrant multiplication can be achieved using an offset binary digital input code and positive and negative reference voltage values. "Digital Input Code/Analog Output Value" for bipolar mode.

A "logic 1" input at any digital input forces the corresponding ladder switch to divert the bit current to the IOUT1 bus. The "logic 0" input forces the bit current to the IOUT2 bus. For any code, the iout1 and iout2 bus currents are complementary to each other. The current amplifier at iout2 changes the polarity of the iout2 current and the transconductance amplifier at iout1 adds the two currents. This configuration doubles the output range. The differential current generated by the zero-offset binary code (msb = "logic 1", all other bits are "logic 0") is corrected from VREF to IOUT2 using an external resistor (10MW).

Gain adjustment

1. Connect all digital inputs to V+.

2. Monitor if VOUT is -VREF (1-2 volt reading. (n=8 for AD7520, n=10 for AD7521.)-(n-1)

3. To increase the output voltage, connect a series resistor up to 250 ohms between the output voltage and the feedback voltage.

4. To reduce the voltage output, connect a series resistor up to 250Ω between the reference voltage and the VREF terminal.