General Instructions
The w25q64cv (64m-bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. The flexibility and performance of the 25Q series far exceeds that of ordinary serial flash devices. They are great for code tracing to RAM, executing code directly from dual/quad spi (xip), and storing speech, text and data. The device operates on a 2.7V to 3.6V supply with current consumption as low as 4mA active and 1 microA off.
W25Q64 cv supports standard serial peripheral interface (SPI), high performance dual/quad output and dual/quad I/O SPI: serial clock, chip select, serial data I/O0 (DI), I/O1 (DO) , I/O2 (/WP) and I/O3 (/HOLD). Supports SPI clock frequencies up to 80MHz, allowing dual I/O equivalent clock frequencies of 160MHz (80MHz x 2) and quad I/O equivalent clock frequencies when using fast-read dual/quad I/O instructions is 320MHz (80MHz x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash. Continuous read mode allows efficient memory access, and the instruction overhead of reading a 24-bit address is only 8 clocks, allowing true xip (execute-in-place) operations.
feature
Spiflash Memory Family – W25Q64cv: 64Mbits/8Mbytes (8388608)
– Standard spi: clk, /cs, di, do, /wp, /hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /HOLD
– Four SPIs: CLK, /CS, IO0, IO1, IO2, IO3
Highest Performance Serial Flash – 80MHz Dual/Quad SPI Clock – 160/320MHz Equivalent Dual/Quad SPI
– 40MB/s sequential data transfer rate – Up to 8 times faster than normal serial flash – Over 100,000 erase/program cycles (1)
– Over 20 years of data retention Efficient "Continuous Read Mode"
– Low instruction overhead – Consecutive reads, 8/16/32/64 byte wraps – Only 8 clocks to address memory – Allows true xip (execute in place) operations – Better than x16 parallel flash efficient” "Continuous Read Mode" – Single 2.7 to 3.6V Supply – 4MA Active Current, <1µA Power Down (Typical)
-40°C to +85°C Operating Range Flexible Architecture with 4KB Sectors - Unified Sector/Block Erase (4/32/64K Bytes)
– Program 1 to 256 bytes – Erase/Program Suspend and Resume Advanced Security Features – Software and Hardware Write Protection – Top/Bottom, 4KB Supplemental Array Protection – Power Lock and OTP Protection – 64-bit Unique ID per Device
– Found Parameter (SFDP) Register – 3x256 Byte Security Register with OTP Lock – Volatile and Non-Volatile Status Register Bit Space Saving Pack – 8-pin SOIC 208 mil
– 8 pad wson 6x5 mm/8x6 mm (2)
– 16-pin SOIC 300 mil
– 8-pin PDIP 300 mil
– 24 Ball TFBGA 8x6mm – Contact Winbond for KGD and other options Note 1. Over 100,000 block erase/program cycles for industrial and automotive temperatures; over 10,000 full chip erase/program cycles per AEC-Q100 test.
Package Type and Pin Configuration

1 chip select (/cs)
The spi chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (do or io0, io1, io2, io3) pins are at high impedance. When deselected, device power consumption is in standby unless an internal erase, program, or write status register cycle is in progress. When /cs is lowered, the device will be selected, power consumption will increase to the active level, and commands can be written to and data read from the device. After power up, /cs must transition from high to low in order to accept new commands. The /CS input must track the VCC supply level at power-up (see "Write Protection" and Figure 38). This can be done using the pull resistor on /cs if desired.
Serial data input, output and IOS (DI, DO and IO0, IO1, IO2, IO3)
W25Q64cv supports standard SPI, dual SPI and quad SPI operation. Standard SPI instructions use a unidirectional DI (input) pin to serially write an instruction, address, or data to the device on the rising edge of the serial clock (CLK) input pin. Standard SPIs also use a unidirectional do (output) to read data or status from the device on the falling edge of clk.
Dual SPI and Quad SPI instructions use bidirectional IO pins to serially write commands, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set. When qe=1, the /wp pin becomes io2, and the /hold pin becomes io3.
Write Protect (/wp)
The write protect (/wp) pin can be used to prevent writing to the status register. Used in conjunction with the block protection (cmp, sec, tb, bp2, bp1, and bp0) bits of the status register and the status register protection (srp) bit, sectors as small as 4kb or part of an entire memory array can be hardware protected. The /WP pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /wp pin function is not available because this pin is used for io 2. The pin configuration for quad I/O operation is shown in Figure 1A-E.
keep (/hold)
The /hold pin allows to hold the device while it is active. When /hold goes low, when /cs goes low, the do pin will be in high impedance and the signals on the di and clk pins will be ignored (don't care). When /HOLD is high, device operation can resume. The /hold function is useful when multiple devices share the same spi signal. The /HOLD pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /hold pin function is not available since this pin is used for io3. The pin configuration for quad I/O operation is shown in Figure 1A-E.
Serial Clock (CLK)
The SPI serial clock input (CLK) pin provides the timing of serial input and output operations. ("See SPI Operation")

Function description
SPI Operation Standard SPI Description
The w25q64cv is accessed through an SPI-compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data in (di), and serial data out (do). The standard SPI instruction uses the DI input pin to serially write an instruction, address, or data to the device on the rising edge of clk. The do output pin is used to read data or status from the device on the falling edge of clk.
SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. The main difference between Mode 0 and Mode 3 is the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the serial flash. For mode 0, the clk signal is typically low on the falling and rising edges of /cs. For Mode 3, the CLK signal is normally high on the falling and rising edges of /cs.
Dual SPI Instructions W25Q64cv supports dual SPI operations when using the "Fast Read Dual Output (3BH)" and "Fast Read Dual I/O (BBH)" instructions. These instructions allow data to be transferred to and from the device at 2 to 3 times the rate of normal serial flash devices. Dual SPI read instructions are great for quickly downloading code to RAM (code shadowing) at power up or executing non-speed critical code directly from the SPI bus (XIP). When using the dual SPI instruction, the di and do pins become bidirectional I/O pins: io0 and io1.
Quad SPI instructions when using "Fast Read Quad Output (6BH)", "Fast Read Quad I/O (EBH)", "Word Read Quad I/O (E7H)" and "Octal Word Read" Quad I/O (E3H)" command, W25Q64cv supports quad SPI operation. These instructions allow data to be transferred to and from the device at 4 to 6 times the rate of normal serial flash. Quad-read instructions provide significant improvements in sequential and random access transfer rates, allowing fast code tracing directly to RAM or execution from the SPI bus (XIP). When using the quad spi instruction, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3, respectively. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set.
Hold function For standard SPI and dual SPI operation, the /hold signal allows w25q64cv operation to be suspended when activated (when /cs is low). The /hold function may be useful in situations where spi data and clock signals are shared with other devices. For example, when priority interrupts need to use the SPI bus, consider whether the page buffer is only partially written. In this case, the /hold function can save the state of the instruction and data in a buffer so that programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and dual SPI operation, not quad SPI operation.
To initiate the A/HOLD condition, a device with /CS low must be selected. If the CLK signal is already low, the A/HOLD state will activate on the falling edge of the /HOLD signal. If CLK is not already low, the /hold condition will activate after the next falling edge of CLK. If the CLK signal is already low, the /HOLD condition will terminate on the rising edge of the /HOLD signal. If CLK is not low, the /hold condition will terminate after the next falling edge of CLK. In the A/HOLD state, the serial data output (do) is high impedance and the serial data input (di) and serial clock (clk) are ignored. The chip select (/cs) signal should remain active (low) for the entire duration of the /hold operation to avoid resetting the device's internal logic state.
Write-protecting applications using non-volatile memory must consider the possibility of noise and other adverse system conditions that could compromise data integrity. To solve this problem, w25q64cv provides several ways to protect data from accidental writes.
Write-Protect Feature Time-delayed write-disable after device reset when VCC is below threshold Power-off command write-protect lock-out write-protect until next power-on One-Time Program (OTP) write-protect*
NOTE: This feature is available on special order. Please contact Winbond for details.
On power-up or power-down, the W25Q64Cv will remain in reset when VCC is below the threshold of VWI (see power-up timing and voltage levels and Figure 38). When reset, all operations are disabled and no commands are recognized. All program and erase related instructions are further disabled due to the time delay of TPUW during power up and after VCC voltage exceeds VWI. This includes Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instructions. Note that the chip select pin (/cs) must track the VCC supply level at power-up until the VCC minimum level and TVSL delay are reached. This can be done using a pull-up resistor on /cs if desired.
After power-up, the device is automatically in a write-disabled state with the Status Register Write Enable Latch (WEL) set to 0. Before accepting a Page Program, Sector Erase, Block Erase, Chip Erase, or Write Status Register command, the Allow Write command must be issued. The Write Enable Latch (WEL) is automatically cleared to a writable state of 0 upon completion of a program, erase or write instruction.
Software-controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protection (srp0, srp1) and Block Protection (cmp, sec, tb, bp2, bp1, and bp0) bits. These settings allow parts or the entire memory array to be configured as read-only for sectors as small as 4KB. Used in conjunction with the write-protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. See the Status Register section for more information. In addition, the power-down command provides an additional level of write protection because all commands except the release power-down command are ignored.
Status Registers and Instructions The Read Status Register-1 and Status Register-2 instructions can be used to provide status of flash array availability, write protection status if the device has write enabled or disabled, quad SPI setup, security register lock status and erase/ Program suspended state. The Write Status Register command can be used to configure the device write protection feature, quad SPI settings and security register OTP lock. Write access to the status register is controlled by the state of the nonvolatile status register protection bits (srp0, srp1), the write enable instruction, and the /WP pin during standard/dual SPI operation.
Status register busy status (busy)
busy is a read-only bit in the Status Register (s0), when the device executes a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, or Erase/Program Security Register instructions, This bit is set to 1 state. During this time, the device will ignore instructions other than Read Status Register and Erase/Program Suspend instructions (see tw, tpp, tse, tbe, and tce in AC Characteristics). When a program, erase or write status/secure register instruction completes, the busy bit will be cleared to the 0 state, indicating that the device is ready for further instructions.
Write Enable Latch Status (WEL)
The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that is set to 1 after a Write Enable instruction is executed. When the device write is disabled, the WEL status bit is cleared to 0. The write disable state occurs at power-up or after any of the following commands: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register, and Program Security Register.
Block protection bits (bp2, bp1, bp0)
The block protection bits (bp2, bp1, bp0) are non-volatile read/write bits in the status registers (s4, s3, and s2) that provide write protection control and status. The block protection bits can be set using the Write Status Register instruction (see tw in AC Characteristics). All, none or part of the memory array can be protected from program and erase instructions (see Status Register Memory Protection Table). The factory default setting of the block protection bit is 0, there is no protected array.
Upper/lower block protection bits (TB)
The non-volatile top/bottom bit (tb) controls whether the block protection bits (bp2, bp1, bp0) are protected from the top (tb=0) or bottom (tb=1) of the array, as shown in the Status Register Memory Protection table . The factory default setting is tb=0. The tb bit can be set with the write status register instruction according to the state of the srp0, srp1 and wel bits.
Sector/Block Protection Bits (sec)
The non-volatile sector/block protection bits (seconds) control whether the block protection bits (bp2, bp1, bp0) protect 4kb sectors (sec=1) at the top (tb=0) or bottom (tb=1) of the array (sec=1) or 64kb blocks (sec=0) as shown in the Status Register Memory Protection table. The default setting is sec=0.
Two's complement protection bit (CMP)
The complement protection bit (cmp) is a non-volatile read/write bit in the status register (s14). It is used in combination with the sec, tb, bp2, bp1 and bp0 bits to provide greater flexibility for array protection. Once CMP is set to 1, the array protection previously set by SEC, TB, BP2, BP1 and BP0 will be reversed. For example, when cmp=0, the top 4KB sectors can be protected while the rest of the array is not; when cmp=1, the top 4KB sectors become unprotected and the rest of the array becomes Read only.

Note:
1. When srp1, srp0 = (1, 0), power off, power cycle will change srp1, srp0 to (0, 0) state. 2. This feature is available on special order. Please contact Winbond for details.
Erase/Program Suspended Status (SUS)
The Suspend Status bit is a read-only bit in the Status Register (s15) that is set to 1 after an Erase/Program Suspend (75h) instruction is executed. The SUS status bit is cleared to 0 by the Erase/Program Resume (7AH) instruction and power down and power cycle.
Security Register Lock Bits (lb3, lb2, lb1)
The secure register lock bits (lb3, lb2, lb1) are non-volatile one-time program (otp) bits in the status registers (s13, s12, s11) that provide write protection control and status to the secure registers. The default state of lb[3:1] is 0 and the security registers are unlocked. lb[3:1] can be individually set to 1 using the write status register instruction. LB[3:1] are one-time programmable (OTP), once set to 1, the corresponding 256-byte security register will permanently become read-only.
Four Enable Bits (QE)
The quad enable (qe) bit is a non-volatile read/write bit in the status register (S9) that enables quad spi operation. When the qe bit is set to the 0 state (factory default), the /wp pin and /hold are enabled. When the qe bit is set to 1, the four io2 and io3 pins are enabled and the /wp and /hold functions are disabled.
Warning: The QE bit should not be set to 1 if the /wp or /hold pins are connected directly to power or ground during standard spi or dual spi operation.